1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1046a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 ethernet7 = &enet7; 33 rtc1 = &ftm_alarm0; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a72"; 43 reg = <0x0>; 44 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 45 next-level-cache = <&l2>; 46 cpu-idle-states = <&CPU_PH20>; 47 #cooling-cells = <2>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a72"; 53 reg = <0x1>; 54 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 55 next-level-cache = <&l2>; 56 cpu-idle-states = <&CPU_PH20>; 57 #cooling-cells = <2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a72"; 63 reg = <0x2>; 64 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 65 next-level-cache = <&l2>; 66 cpu-idle-states = <&CPU_PH20>; 67 #cooling-cells = <2>; 68 }; 69 70 cpu3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a72"; 73 reg = <0x3>; 74 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 75 next-level-cache = <&l2>; 76 cpu-idle-states = <&CPU_PH20>; 77 #cooling-cells = <2>; 78 }; 79 80 l2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 }; 85 }; 86 87 idle-states { 88 /* 89 * PSCI node is not added default, U-boot will add missing 90 * parts if it determines to use PSCI. 91 */ 92 entry-method = "psci"; 93 94 CPU_PH20: cpu-ph20 { 95 compatible = "arm,idle-state"; 96 idle-state-name = "PH20"; 97 arm,psci-suspend-param = <0x0>; 98 entry-latency-us = <1000>; 99 exit-latency-us = <1000>; 100 min-residency-us = <3000>; 101 }; 102 }; 103 104 memory@80000000 { 105 device_type = "memory"; 106 /* Real size will be filled by bootloader */ 107 reg = <0x0 0x80000000 0x0 0x0>; 108 }; 109 110 sysclk: sysclk { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <100000000>; 114 clock-output-names = "sysclk"; 115 }; 116 117 reboot { 118 compatible = "syscon-reboot"; 119 regmap = <&dcfg>; 120 offset = <0xb0>; 121 mask = <0x02>; 122 }; 123 124 thermal-zones { 125 ddr-controller { 126 polling-delay-passive = <1000>; 127 polling-delay = <5000>; 128 thermal-sensors = <&tmu 0>; 129 130 trips { 131 ddr-ctrler-alert { 132 temperature = <85000>; 133 hysteresis = <2000>; 134 type = "passive"; 135 }; 136 137 ddr-ctrler-crit { 138 temperature = <95000>; 139 hysteresis = <2000>; 140 type = "critical"; 141 }; 142 }; 143 }; 144 145 serdes { 146 polling-delay-passive = <1000>; 147 polling-delay = <5000>; 148 thermal-sensors = <&tmu 1>; 149 150 trips { 151 serdes-alert { 152 temperature = <85000>; 153 hysteresis = <2000>; 154 type = "passive"; 155 }; 156 157 serdes-crit { 158 temperature = <95000>; 159 hysteresis = <2000>; 160 type = "critical"; 161 }; 162 }; 163 }; 164 165 fman { 166 polling-delay-passive = <1000>; 167 polling-delay = <5000>; 168 thermal-sensors = <&tmu 2>; 169 170 trips { 171 fman-alert { 172 temperature = <85000>; 173 hysteresis = <2000>; 174 type = "passive"; 175 }; 176 177 fman-crit { 178 temperature = <95000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 }; 184 185 core-cluster { 186 polling-delay-passive = <1000>; 187 polling-delay = <5000>; 188 thermal-sensors = <&tmu 3>; 189 190 trips { 191 core_cluster_alert: core-cluster-alert { 192 temperature = <85000>; 193 hysteresis = <2000>; 194 type = "passive"; 195 }; 196 197 core_cluster_crit: core-cluster-crit { 198 temperature = <95000>; 199 hysteresis = <2000>; 200 type = "critical"; 201 }; 202 }; 203 204 cooling-maps { 205 map0 { 206 trip = <&core_cluster_alert>; 207 cooling-device = 208 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 }; 214 }; 215 216 sec { 217 polling-delay-passive = <1000>; 218 polling-delay = <5000>; 219 thermal-sensors = <&tmu 4>; 220 221 trips { 222 sec-alert { 223 temperature = <85000>; 224 hysteresis = <2000>; 225 type = "passive"; 226 }; 227 228 sec-crit { 229 temperature = <95000>; 230 hysteresis = <2000>; 231 type = "critical"; 232 }; 233 }; 234 }; 235 }; 236 237 timer { 238 compatible = "arm,armv8-timer"; 239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 240 IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 242 IRQ_TYPE_LEVEL_LOW)>, 243 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 244 IRQ_TYPE_LEVEL_LOW)>, 245 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 246 IRQ_TYPE_LEVEL_LOW)>; 247 }; 248 249 pmu { 250 compatible = "arm,cortex-a72-pmu"; 251 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-affinity = <&cpu0>, 256 <&cpu1>, 257 <&cpu2>, 258 <&cpu3>; 259 }; 260 261 gic: interrupt-controller@1400000 { 262 compatible = "arm,gic-400"; 263 #interrupt-cells = <3>; 264 interrupt-controller; 265 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 266 <0x0 0x1420000 0 0x20000>, /* GICC */ 267 <0x0 0x1440000 0 0x20000>, /* GICH */ 268 <0x0 0x1460000 0 0x20000>; /* GICV */ 269 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 270 IRQ_TYPE_LEVEL_LOW)>; 271 }; 272 273 soc: soc { 274 compatible = "simple-bus"; 275 #address-cells = <2>; 276 #size-cells = <2>; 277 ranges; 278 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 279 dma-coherent; 280 281 ddr: memory-controller@1080000 { 282 compatible = "fsl,qoriq-memory-controller"; 283 reg = <0x0 0x1080000 0x0 0x1000>; 284 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 285 big-endian; 286 }; 287 288 ifc: memory-controller@1530000 { 289 compatible = "fsl,ifc"; 290 reg = <0x0 0x1530000 0x0 0x10000>; 291 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 292 status = "disabled"; 293 }; 294 295 qspi: spi@1550000 { 296 compatible = "fsl,ls1021a-qspi"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0 0x1550000 0x0 0x10000>, 300 <0x0 0x40000000 0x0 0x10000000>; 301 reg-names = "QuadSPI", "QuadSPI-memory"; 302 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 303 clock-names = "qspi_en", "qspi"; 304 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 305 QORIQ_CLK_PLL_DIV(2)>, 306 <&clockgen QORIQ_CLK_PLATFORM_PLL 307 QORIQ_CLK_PLL_DIV(2)>; 308 status = "disabled"; 309 }; 310 311 esdhc: esdhc@1560000 { 312 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 313 reg = <0x0 0x1560000 0x0 0x10000>; 314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 316 voltage-ranges = <1800 1800 3300 3300>; 317 sdhci,auto-cmd12; 318 big-endian; 319 bus-width = <4>; 320 }; 321 322 scfg: scfg@1570000 { 323 compatible = "fsl,ls1046a-scfg", "syscon"; 324 reg = <0x0 0x1570000 0x0 0x10000>; 325 big-endian; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0x0 0x0 0x1570000 0x10000>; 329 330 extirq: interrupt-controller@1ac { 331 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; 332 #interrupt-cells = <2>; 333 #address-cells = <0>; 334 interrupt-controller; 335 reg = <0x1ac 4>; 336 interrupt-map = 337 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 338 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 339 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 340 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 341 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 342 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 343 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 344 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 345 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 346 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 347 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 348 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 349 interrupt-map-mask = <0xf 0x0>; 350 }; 351 }; 352 353 crypto: crypto@1700000 { 354 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 355 "fsl,sec-v4.0"; 356 fsl,sec-era = <8>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0x0 0x00 0x1700000 0x100000>; 360 reg = <0x00 0x1700000 0x0 0x100000>; 361 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 362 363 sec_jr0: jr@10000 { 364 compatible = "fsl,sec-v5.4-job-ring", 365 "fsl,sec-v5.0-job-ring", 366 "fsl,sec-v4.0-job-ring"; 367 reg = <0x10000 0x10000>; 368 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 369 }; 370 371 sec_jr1: jr@20000 { 372 compatible = "fsl,sec-v5.4-job-ring", 373 "fsl,sec-v5.0-job-ring", 374 "fsl,sec-v4.0-job-ring"; 375 reg = <0x20000 0x10000>; 376 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 377 }; 378 379 sec_jr2: jr@30000 { 380 compatible = "fsl,sec-v5.4-job-ring", 381 "fsl,sec-v5.0-job-ring", 382 "fsl,sec-v4.0-job-ring"; 383 reg = <0x30000 0x10000>; 384 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 385 }; 386 387 sec_jr3: jr@40000 { 388 compatible = "fsl,sec-v5.4-job-ring", 389 "fsl,sec-v5.0-job-ring", 390 "fsl,sec-v4.0-job-ring"; 391 reg = <0x40000 0x10000>; 392 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 }; 395 396 qman: qman@1880000 { 397 compatible = "fsl,qman"; 398 reg = <0x0 0x1880000 0x0 0x10000>; 399 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 400 memory-region = <&qman_fqd &qman_pfdr>; 401 402 }; 403 404 bman: bman@1890000 { 405 compatible = "fsl,bman"; 406 reg = <0x0 0x1890000 0x0 0x10000>; 407 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 408 memory-region = <&bman_fbpr>; 409 410 }; 411 412 qportals: qman-portals@500000000 { 413 ranges = <0x0 0x5 0x00000000 0x8000000>; 414 }; 415 416 bportals: bman-portals@508000000 { 417 ranges = <0x0 0x5 0x08000000 0x8000000>; 418 }; 419 420 sfp: efuse@1e80000 { 421 compatible = "fsl,ls1021a-sfp"; 422 reg = <0x0 0x1e80000 0x0 0x10000>; 423 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 424 QORIQ_CLK_PLL_DIV(4)>; 425 clock-names = "sfp"; 426 }; 427 428 dcfg: dcfg@1ee0000 { 429 compatible = "fsl,ls1046a-dcfg", "syscon"; 430 reg = <0x0 0x1ee0000 0x0 0x1000>; 431 big-endian; 432 }; 433 434 clockgen: clocking@1ee1000 { 435 compatible = "fsl,ls1046a-clockgen"; 436 reg = <0x0 0x1ee1000 0x0 0x1000>; 437 #clock-cells = <2>; 438 clocks = <&sysclk>; 439 }; 440 441 tmu: tmu@1f00000 { 442 compatible = "fsl,qoriq-tmu"; 443 reg = <0x0 0x1f00000 0x0 0x10000>; 444 interrupts = <0 33 0x4>; 445 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 446 fsl,tmu-calibration = 447 /* Calibration data group 1 */ 448 <0x00000000 0x00000023>, 449 <0x00000001 0x00000029>, 450 <0x00000002 0x0000002f>, 451 <0x00000003 0x00000036>, 452 <0x00000004 0x0000003c>, 453 <0x00000005 0x00000042>, 454 <0x00000006 0x00000049>, 455 <0x00000007 0x0000004f>, 456 <0x00000008 0x00000055>, 457 <0x00000009 0x0000005c>, 458 <0x0000000a 0x00000062>, 459 <0x0000000b 0x00000068>, 460 /* Calibration data group 2 */ 461 <0x00010000 0x00000022>, 462 <0x00010001 0x0000002a>, 463 <0x00010002 0x00000032>, 464 <0x00010003 0x0000003a>, 465 <0x00010004 0x00000042>, 466 <0x00010005 0x0000004a>, 467 <0x00010006 0x00000052>, 468 <0x00010007 0x0000005a>, 469 <0x00010008 0x00000062>, 470 <0x00010009 0x0000006a>, 471 /* Calibration data group 3 */ 472 <0x00020000 0x00000021>, 473 <0x00020001 0x0000002b>, 474 <0x00020002 0x00000035>, 475 <0x00020003 0x0000003e>, 476 <0x00020004 0x00000048>, 477 <0x00020005 0x00000052>, 478 <0x00020006 0x0000005c>, 479 /* Calibration data group 4 */ 480 <0x00030000 0x00000011>, 481 <0x00030001 0x0000001a>, 482 <0x00030002 0x00000024>, 483 <0x00030003 0x0000002e>, 484 <0x00030004 0x00000038>, 485 <0x00030005 0x00000042>, 486 <0x00030006 0x0000004c>, 487 <0x00030007 0x00000056>; 488 #thermal-sensor-cells = <1>; 489 }; 490 491 dspi: spi@2100000 { 492 compatible = "fsl,ls1021a-v1.0-dspi"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 reg = <0x0 0x2100000 0x0 0x10000>; 496 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 497 clock-names = "dspi"; 498 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 499 QORIQ_CLK_PLL_DIV(2)>; 500 spi-num-chipselects = <5>; 501 big-endian; 502 status = "disabled"; 503 }; 504 505 i2c0: i2c@2180000 { 506 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <0x0 0x2180000 0x0 0x10000>; 510 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 512 QORIQ_CLK_PLL_DIV(2)>; 513 dmas = <&edma0 1 38>, 514 <&edma0 1 39>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 i2c1: i2c@2190000 { 520 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 reg = <0x0 0x2190000 0x0 0x10000>; 524 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 526 QORIQ_CLK_PLL_DIV(2)>; 527 scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 528 status = "disabled"; 529 }; 530 531 i2c2: i2c@21a0000 { 532 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 reg = <0x0 0x21a0000 0x0 0x10000>; 536 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 538 QORIQ_CLK_PLL_DIV(2)>; 539 scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 540 status = "disabled"; 541 }; 542 543 i2c3: i2c@21b0000 { 544 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0x0 0x21b0000 0x0 0x10000>; 548 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 550 QORIQ_CLK_PLL_DIV(2)>; 551 scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 552 status = "disabled"; 553 }; 554 555 duart0: serial@21c0500 { 556 compatible = "fsl,ns16550", "ns16550a"; 557 reg = <0x00 0x21c0500 0x0 0x100>; 558 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 560 QORIQ_CLK_PLL_DIV(2)>; 561 status = "disabled"; 562 }; 563 564 duart1: serial@21c0600 { 565 compatible = "fsl,ns16550", "ns16550a"; 566 reg = <0x00 0x21c0600 0x0 0x100>; 567 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 569 QORIQ_CLK_PLL_DIV(2)>; 570 status = "disabled"; 571 }; 572 573 duart2: serial@21d0500 { 574 compatible = "fsl,ns16550", "ns16550a"; 575 reg = <0x0 0x21d0500 0x0 0x100>; 576 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 578 QORIQ_CLK_PLL_DIV(2)>; 579 status = "disabled"; 580 }; 581 582 duart3: serial@21d0600 { 583 compatible = "fsl,ns16550", "ns16550a"; 584 reg = <0x0 0x21d0600 0x0 0x100>; 585 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 587 QORIQ_CLK_PLL_DIV(2)>; 588 status = "disabled"; 589 }; 590 591 gpio0: gpio@2300000 { 592 compatible = "fsl,qoriq-gpio"; 593 reg = <0x0 0x2300000 0x0 0x10000>; 594 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 595 gpio-controller; 596 #gpio-cells = <2>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 }; 600 601 gpio1: gpio@2310000 { 602 compatible = "fsl,qoriq-gpio"; 603 reg = <0x0 0x2310000 0x0 0x10000>; 604 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 605 gpio-controller; 606 #gpio-cells = <2>; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 611 gpio2: gpio@2320000 { 612 compatible = "fsl,qoriq-gpio"; 613 reg = <0x0 0x2320000 0x0 0x10000>; 614 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 615 gpio-controller; 616 #gpio-cells = <2>; 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 }; 620 621 gpio3: gpio@2330000 { 622 compatible = "fsl,qoriq-gpio"; 623 reg = <0x0 0x2330000 0x0 0x10000>; 624 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 625 gpio-controller; 626 #gpio-cells = <2>; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 }; 630 631 lpuart0: serial@2950000 { 632 compatible = "fsl,ls1021a-lpuart"; 633 reg = <0x0 0x2950000 0x0 0x1000>; 634 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 636 QORIQ_CLK_PLL_DIV(1)>; 637 clock-names = "ipg"; 638 status = "disabled"; 639 }; 640 641 lpuart1: serial@2960000 { 642 compatible = "fsl,ls1021a-lpuart"; 643 reg = <0x0 0x2960000 0x0 0x1000>; 644 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 646 QORIQ_CLK_PLL_DIV(2)>; 647 clock-names = "ipg"; 648 status = "disabled"; 649 }; 650 651 lpuart2: serial@2970000 { 652 compatible = "fsl,ls1021a-lpuart"; 653 reg = <0x0 0x2970000 0x0 0x1000>; 654 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 656 QORIQ_CLK_PLL_DIV(2)>; 657 clock-names = "ipg"; 658 status = "disabled"; 659 }; 660 661 lpuart3: serial@2980000 { 662 compatible = "fsl,ls1021a-lpuart"; 663 reg = <0x0 0x2980000 0x0 0x1000>; 664 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 666 QORIQ_CLK_PLL_DIV(2)>; 667 clock-names = "ipg"; 668 status = "disabled"; 669 }; 670 671 lpuart4: serial@2990000 { 672 compatible = "fsl,ls1021a-lpuart"; 673 reg = <0x0 0x2990000 0x0 0x1000>; 674 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 676 QORIQ_CLK_PLL_DIV(2)>; 677 clock-names = "ipg"; 678 status = "disabled"; 679 }; 680 681 lpuart5: serial@29a0000 { 682 compatible = "fsl,ls1021a-lpuart"; 683 reg = <0x0 0x29a0000 0x0 0x1000>; 684 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 686 QORIQ_CLK_PLL_DIV(2)>; 687 clock-names = "ipg"; 688 status = "disabled"; 689 }; 690 691 wdog0: watchdog@2ad0000 { 692 compatible = "fsl,imx21-wdt"; 693 reg = <0x0 0x2ad0000 0x0 0x10000>; 694 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 696 QORIQ_CLK_PLL_DIV(2)>; 697 big-endian; 698 }; 699 700 edma0: dma-controller@2c00000 { 701 #dma-cells = <2>; 702 compatible = "fsl,vf610-edma"; 703 reg = <0x0 0x2c00000 0x0 0x10000>, 704 <0x0 0x2c10000 0x0 0x10000>, 705 <0x0 0x2c20000 0x0 0x10000>; 706 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "edma-tx", "edma-err"; 709 dma-channels = <32>; 710 big-endian; 711 clock-names = "dmamux0", "dmamux1"; 712 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 713 QORIQ_CLK_PLL_DIV(2)>, 714 <&clockgen QORIQ_CLK_PLATFORM_PLL 715 QORIQ_CLK_PLL_DIV(2)>; 716 }; 717 718 aux_bus: aux_bus { 719 #address-cells = <2>; 720 #size-cells = <2>; 721 compatible = "simple-bus"; 722 ranges; 723 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 724 725 usb0: usb@2f00000 { 726 compatible = "snps,dwc3"; 727 reg = <0x0 0x2f00000 0x0 0x10000>; 728 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 729 dr_mode = "host"; 730 snps,quirk-frame-length-adjustment = <0x20>; 731 snps,dis_rxdet_inp3_quirk; 732 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 733 usb3-lpm-capable; 734 }; 735 736 usb1: usb@3000000 { 737 compatible = "snps,dwc3"; 738 reg = <0x0 0x3000000 0x0 0x10000>; 739 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 740 dr_mode = "host"; 741 snps,quirk-frame-length-adjustment = <0x20>; 742 snps,dis_rxdet_inp3_quirk; 743 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 744 usb3-lpm-capable; 745 }; 746 747 usb2: usb@3100000 { 748 compatible = "snps,dwc3"; 749 reg = <0x0 0x3100000 0x0 0x10000>; 750 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 751 dr_mode = "host"; 752 snps,quirk-frame-length-adjustment = <0x20>; 753 snps,dis_rxdet_inp3_quirk; 754 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 755 usb3-lpm-capable; 756 }; 757 758 sata: sata@3200000 { 759 compatible = "fsl,ls1046a-ahci"; 760 reg = <0x0 0x3200000 0x0 0x10000>, 761 <0x0 0x20140520 0x0 0x4>; 762 reg-names = "ahci", "sata-ecc"; 763 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 765 QORIQ_CLK_PLL_DIV(2)>; 766 }; 767 }; 768 769 msi1: msi-controller@1580000 { 770 compatible = "fsl,ls1046a-msi"; 771 msi-controller; 772 reg = <0x0 0x1580000 0x0 0x10000>; 773 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 777 }; 778 779 msi2: msi-controller@1590000 { 780 compatible = "fsl,ls1046a-msi"; 781 msi-controller; 782 reg = <0x0 0x1590000 0x0 0x10000>; 783 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 787 }; 788 789 msi3: msi-controller@15a0000 { 790 compatible = "fsl,ls1046a-msi"; 791 msi-controller; 792 reg = <0x0 0x15a0000 0x0 0x10000>; 793 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 797 }; 798 799 pcie1: pcie@3400000 { 800 compatible = "fsl,ls1046a-pcie"; 801 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 802 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 803 reg-names = "regs", "config"; 804 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 805 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 806 interrupt-names = "aer", "pme"; 807 #address-cells = <3>; 808 #size-cells = <2>; 809 device_type = "pci"; 810 num-viewport = <8>; 811 bus-range = <0x0 0xff>; 812 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 813 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 814 msi-parent = <&msi1>, <&msi2>, <&msi3>; 815 #interrupt-cells = <1>; 816 interrupt-map-mask = <0 0 0 7>; 817 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 818 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 819 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 820 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 821 big-endian; 822 status = "disabled"; 823 }; 824 825 pcie_ep1: pcie_ep@3400000 { 826 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 827 reg = <0x00 0x03400000 0x0 0x00100000>, 828 <0x40 0x00000000 0x8 0x00000000>; 829 reg-names = "regs", "addr_space"; 830 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "pme"; 832 num-ib-windows = <6>; 833 num-ob-windows = <8>; 834 big-endian; 835 status = "disabled"; 836 }; 837 838 pcie2: pcie@3500000 { 839 compatible = "fsl,ls1046a-pcie"; 840 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 841 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 842 reg-names = "regs", "config"; 843 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 844 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 845 interrupt-names = "aer", "pme"; 846 #address-cells = <3>; 847 #size-cells = <2>; 848 device_type = "pci"; 849 num-viewport = <8>; 850 bus-range = <0x0 0xff>; 851 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 852 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 853 msi-parent = <&msi2>, <&msi3>, <&msi1>; 854 #interrupt-cells = <1>; 855 interrupt-map-mask = <0 0 0 7>; 856 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 857 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 858 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 859 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 860 big-endian; 861 status = "disabled"; 862 }; 863 864 pcie_ep2: pcie_ep@3500000 { 865 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 866 reg = <0x00 0x03500000 0x0 0x00100000>, 867 <0x48 0x00000000 0x8 0x00000000>; 868 reg-names = "regs", "addr_space"; 869 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "pme"; 871 num-ib-windows = <6>; 872 num-ob-windows = <8>; 873 big-endian; 874 status = "disabled"; 875 }; 876 877 pcie3: pcie@3600000 { 878 compatible = "fsl,ls1046a-pcie"; 879 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 880 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 881 reg-names = "regs", "config"; 882 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 883 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 884 interrupt-names = "aer", "pme"; 885 #address-cells = <3>; 886 #size-cells = <2>; 887 device_type = "pci"; 888 num-viewport = <8>; 889 bus-range = <0x0 0xff>; 890 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 891 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 892 msi-parent = <&msi3>, <&msi1>, <&msi2>; 893 #interrupt-cells = <1>; 894 interrupt-map-mask = <0 0 0 7>; 895 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 896 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 897 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 898 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 899 big-endian; 900 status = "disabled"; 901 }; 902 903 pcie_ep3: pcie_ep@3600000 { 904 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 905 reg = <0x00 0x03600000 0x0 0x00100000>, 906 <0x50 0x00000000 0x8 0x00000000>; 907 reg-names = "regs", "addr_space"; 908 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 909 interrupt-names = "pme"; 910 num-ib-windows = <6>; 911 num-ob-windows = <8>; 912 big-endian; 913 status = "disabled"; 914 }; 915 916 qdma: dma-controller@8380000 { 917 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 918 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 919 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 920 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 921 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "qdma-error", "qdma-queue0", 927 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 928 dma-channels = <8>; 929 block-number = <1>; 930 block-offset = <0x10000>; 931 fsl,dma-queues = <2>; 932 status-sizes = <64>; 933 queue-sizes = <64 64>; 934 big-endian; 935 }; 936 937 rcpm: power-controller@1ee2140 { 938 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 939 reg = <0x0 0x1ee2140 0x0 0x4>; 940 #fsl,rcpm-wakeup-cells = <1>; 941 }; 942 943 ftm_alarm0: timer@29d0000 { 944 compatible = "fsl,ls1046a-ftm-alarm"; 945 reg = <0x0 0x29d0000 0x0 0x10000>; 946 fsl,rcpm-wakeup = <&rcpm 0x20000>; 947 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 948 big-endian; 949 }; 950 }; 951 952 reserved-memory { 953 #address-cells = <2>; 954 #size-cells = <2>; 955 ranges; 956 957 bman_fbpr: bman-fbpr { 958 compatible = "shared-dma-pool"; 959 size = <0 0x1000000>; 960 alignment = <0 0x1000000>; 961 no-map; 962 }; 963 964 qman_fqd: qman-fqd { 965 compatible = "shared-dma-pool"; 966 size = <0 0x800000>; 967 alignment = <0 0x800000>; 968 no-map; 969 }; 970 971 qman_pfdr: qman-pfdr { 972 compatible = "shared-dma-pool"; 973 size = <0 0x2000000>; 974 alignment = <0 0x2000000>; 975 no-map; 976 }; 977 }; 978 979 firmware { 980 optee { 981 compatible = "linaro,optee-tz"; 982 method = "smc"; 983 }; 984 }; 985}; 986 987#include "qoriq-qman-portals.dtsi" 988#include "qoriq-bman-portals.dtsi" 989