1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018 NXP 7 * 8 * Shaohui Xie <Shaohui.Xie@nxp.com> 9 */ 10 11/dts-v1/; 12 13#include "fsl-ls1046a.dtsi" 14 15/ { 16 model = "LS1046A QDS Board"; 17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 serial0 = &duart0; 25 serial1 = &duart1; 26 serial2 = &duart2; 27 serial3 = &duart3; 28 }; 29 30 chosen { 31 stdout-path = "serial0:115200n8"; 32 }; 33}; 34 35&dspi { 36 bus-num = <0>; 37 status = "okay"; 38 39 flash@0 { 40 #address-cells = <1>; 41 #size-cells = <1>; 42 compatible = "n25q128a11", "jedec,spi-nor"; 43 reg = <0>; 44 spi-max-frequency = <10000000>; 45 }; 46 47 flash@1 { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "sst25wf040b", "jedec,spi-nor"; 51 spi-cpol; 52 spi-cpha; 53 reg = <1>; 54 spi-max-frequency = <10000000>; 55 }; 56 57 flash@2 { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "en25s64", "jedec,spi-nor"; 61 spi-cpol; 62 spi-cpha; 63 reg = <2>; 64 spi-max-frequency = <10000000>; 65 }; 66}; 67 68&duart0 { 69 status = "okay"; 70}; 71 72&duart1 { 73 status = "okay"; 74}; 75 76&i2c0 { 77 status = "okay"; 78 79 pca9547@77 { 80 compatible = "nxp,pca9547"; 81 reg = <0x77>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 i2c@2 { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 reg = <0x2>; 89 90 ina220@40 { 91 compatible = "ti,ina220"; 92 reg = <0x40>; 93 shunt-resistor = <1000>; 94 }; 95 96 ina220@41 { 97 compatible = "ti,ina220"; 98 reg = <0x41>; 99 shunt-resistor = <1000>; 100 }; 101 }; 102 103 i2c@3 { 104 #address-cells = <1>; 105 #size-cells = <0>; 106 reg = <0x3>; 107 108 rtc@51 { 109 compatible = "nxp,pcf2129"; 110 reg = <0x51>; 111 /* IRQ10_B */ 112 interrupts = <0 150 0x4>; 113 }; 114 115 eeprom@56 { 116 compatible = "atmel,24c512"; 117 reg = <0x56>; 118 }; 119 120 eeprom@57 { 121 compatible = "atmel,24c512"; 122 reg = <0x57>; 123 }; 124 125 temp-sensor@4c { 126 compatible = "adi,adt7461a"; 127 reg = <0x4c>; 128 }; 129 }; 130 }; 131}; 132 133&ifc { 134 #address-cells = <2>; 135 #size-cells = <1>; 136 /* NOR, NAND Flashes and FPGA on board */ 137 ranges = <0x0 0x0 0x0 0x60000000 0x08000000 138 0x1 0x0 0x0 0x7e800000 0x00010000 139 0x2 0x0 0x0 0x7fb00000 0x00000100>; 140 status = "okay"; 141 142 nor@0,0 { 143 compatible = "cfi-flash"; 144 reg = <0x0 0x0 0x8000000>; 145 big-endian; 146 bank-width = <2>; 147 device-width = <1>; 148 }; 149 150 nand@1,0 { 151 compatible = "fsl,ifc-nand"; 152 reg = <0x1 0x0 0x10000>; 153 }; 154 155 fpga: board-control@2,0 { 156 compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; 157 reg = <0x2 0x0 0x0000100>; 158 }; 159}; 160 161&lpuart0 { 162 status = "okay"; 163}; 164 165&qspi { 166 status = "okay"; 167 168 qflash0: flash@0 { 169 compatible = "spansion,m25p80"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 spi-max-frequency = <20000000>; 173 spi-rx-bus-width = <4>; 174 spi-tx-bus-width = <4>; 175 reg = <0>; 176 }; 177}; 178 179#include "fsl-ls1046-post.dtsi" 180