1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 4 * 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <Mingkai.hu@freescale.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1043a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 rtc1 = &ftm_alarm0; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 /* 40 * We expect the enable-method for cpu's to be "psci", but this 41 * is dependent on the SoC FW, which will fill this in. 42 * 43 * Currently supported enable-method is psci v0.2 44 */ 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 50 next-level-cache = <&l2>; 51 cpu-idle-states = <&CPU_PH20>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x1>; 59 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 60 next-level-cache = <&l2>; 61 cpu-idle-states = <&CPU_PH20>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x2>; 69 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 70 next-level-cache = <&l2>; 71 cpu-idle-states = <&CPU_PH20>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x3>; 79 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 80 next-level-cache = <&l2>; 81 cpu-idle-states = <&CPU_PH20>; 82 #cooling-cells = <2>; 83 }; 84 85 l2: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 }; 89 }; 90 91 idle-states { 92 /* 93 * PSCI node is not added default, U-boot will add missing 94 * parts if it determines to use PSCI. 95 */ 96 entry-method = "psci"; 97 98 CPU_PH20: cpu-ph20 { 99 compatible = "arm,idle-state"; 100 idle-state-name = "PH20"; 101 arm,psci-suspend-param = <0x0>; 102 entry-latency-us = <1000>; 103 exit-latency-us = <1000>; 104 min-residency-us = <3000>; 105 }; 106 }; 107 108 memory@80000000 { 109 device_type = "memory"; 110 reg = <0x0 0x80000000 0 0x80000000>; 111 /* DRAM space 1, size: 2GiB DRAM */ 112 }; 113 114 reserved-memory { 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 119 bman_fbpr: bman-fbpr { 120 compatible = "shared-dma-pool"; 121 size = <0 0x1000000>; 122 alignment = <0 0x1000000>; 123 no-map; 124 }; 125 126 qman_fqd: qman-fqd { 127 compatible = "shared-dma-pool"; 128 size = <0 0x400000>; 129 alignment = <0 0x400000>; 130 no-map; 131 }; 132 133 qman_pfdr: qman-pfdr { 134 compatible = "shared-dma-pool"; 135 size = <0 0x2000000>; 136 alignment = <0 0x2000000>; 137 no-map; 138 }; 139 }; 140 141 sysclk: sysclk { 142 compatible = "fixed-clock"; 143 #clock-cells = <0>; 144 clock-frequency = <100000000>; 145 clock-output-names = "sysclk"; 146 }; 147 148 reboot { 149 compatible = "syscon-reboot"; 150 regmap = <&dcfg>; 151 offset = <0xb0>; 152 mask = <0x02>; 153 }; 154 155 thermal-zones { 156 ddr-controller { 157 polling-delay-passive = <1000>; 158 polling-delay = <5000>; 159 thermal-sensors = <&tmu 0>; 160 161 trips { 162 ddr-ctrler-alert { 163 temperature = <85000>; 164 hysteresis = <2000>; 165 type = "passive"; 166 }; 167 168 ddr-ctrler-crit { 169 temperature = <95000>; 170 hysteresis = <2000>; 171 type = "critical"; 172 }; 173 }; 174 }; 175 176 serdes { 177 polling-delay-passive = <1000>; 178 polling-delay = <5000>; 179 thermal-sensors = <&tmu 1>; 180 181 trips { 182 serdes-alert { 183 temperature = <85000>; 184 hysteresis = <2000>; 185 type = "passive"; 186 }; 187 188 serdes-crit { 189 temperature = <95000>; 190 hysteresis = <2000>; 191 type = "critical"; 192 }; 193 }; 194 }; 195 196 fman { 197 polling-delay-passive = <1000>; 198 polling-delay = <5000>; 199 thermal-sensors = <&tmu 2>; 200 201 trips { 202 fman-alert { 203 temperature = <85000>; 204 hysteresis = <2000>; 205 type = "passive"; 206 }; 207 208 fman-crit { 209 temperature = <95000>; 210 hysteresis = <2000>; 211 type = "critical"; 212 }; 213 }; 214 }; 215 216 core-cluster { 217 polling-delay-passive = <1000>; 218 polling-delay = <5000>; 219 thermal-sensors = <&tmu 3>; 220 221 trips { 222 core_cluster_alert: core-cluster-alert { 223 temperature = <85000>; 224 hysteresis = <2000>; 225 type = "passive"; 226 }; 227 228 core_cluster_crit: core-cluster-crit { 229 temperature = <95000>; 230 hysteresis = <2000>; 231 type = "critical"; 232 }; 233 }; 234 235 cooling-maps { 236 map0 { 237 trip = <&core_cluster_alert>; 238 cooling-device = 239 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 240 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 241 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 242 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 243 }; 244 }; 245 }; 246 247 sec { 248 polling-delay-passive = <1000>; 249 polling-delay = <5000>; 250 thermal-sensors = <&tmu 4>; 251 252 trips { 253 sec-alert { 254 temperature = <85000>; 255 hysteresis = <2000>; 256 type = "passive"; 257 }; 258 259 sec-crit { 260 temperature = <95000>; 261 hysteresis = <2000>; 262 type = "critical"; 263 }; 264 }; 265 }; 266 }; 267 268 timer { 269 compatible = "arm,armv8-timer"; 270 interrupts = <1 13 0xf08>, /* Physical Secure PPI */ 271 <1 14 0xf08>, /* Physical Non-Secure PPI */ 272 <1 11 0xf08>, /* Virtual PPI */ 273 <1 10 0xf08>; /* Hypervisor PPI */ 274 fsl,erratum-a008585; 275 }; 276 277 pmu { 278 compatible = "arm,armv8-pmuv3"; 279 interrupts = <0 106 0x4>, 280 <0 107 0x4>, 281 <0 95 0x4>, 282 <0 97 0x4>; 283 interrupt-affinity = <&cpu0>, 284 <&cpu1>, 285 <&cpu2>, 286 <&cpu3>; 287 }; 288 289 gic: interrupt-controller@1400000 { 290 compatible = "arm,gic-400"; 291 #interrupt-cells = <3>; 292 interrupt-controller; 293 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 294 <0x0 0x1402000 0 0x2000>, /* GICC */ 295 <0x0 0x1404000 0 0x2000>, /* GICH */ 296 <0x0 0x1406000 0 0x2000>; /* GICV */ 297 interrupts = <1 9 0xf08>; 298 }; 299 300 soc: soc { 301 compatible = "simple-bus"; 302 #address-cells = <2>; 303 #size-cells = <2>; 304 ranges; 305 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 306 dma-coherent; 307 308 clockgen: clocking@1ee1000 { 309 compatible = "fsl,ls1043a-clockgen"; 310 reg = <0x0 0x1ee1000 0x0 0x1000>; 311 #clock-cells = <2>; 312 clocks = <&sysclk>; 313 }; 314 315 scfg: scfg@1570000 { 316 compatible = "fsl,ls1043a-scfg", "syscon"; 317 reg = <0x0 0x1570000 0x0 0x10000>; 318 big-endian; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 ranges = <0x0 0x0 0x1570000 0x10000>; 322 323 extirq: interrupt-controller@1ac { 324 compatible = "fsl,ls1043a-extirq"; 325 #interrupt-cells = <2>; 326 #address-cells = <0>; 327 interrupt-controller; 328 reg = <0x1ac 4>; 329 interrupt-map = 330 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 331 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 332 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 333 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 334 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 335 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 336 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 337 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 338 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 339 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 340 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 341 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-map-mask = <0xf 0x0>; 343 }; 344 }; 345 346 crypto: crypto@1700000 { 347 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 348 "fsl,sec-v4.0"; 349 fsl,sec-era = <3>; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 ranges = <0x0 0x00 0x1700000 0x100000>; 353 reg = <0x00 0x1700000 0x0 0x100000>; 354 interrupts = <0 75 0x4>; 355 dma-coherent; 356 357 sec_jr0: jr@10000 { 358 compatible = "fsl,sec-v5.4-job-ring", 359 "fsl,sec-v5.0-job-ring", 360 "fsl,sec-v4.0-job-ring"; 361 reg = <0x10000 0x10000>; 362 interrupts = <0 71 0x4>; 363 }; 364 365 sec_jr1: jr@20000 { 366 compatible = "fsl,sec-v5.4-job-ring", 367 "fsl,sec-v5.0-job-ring", 368 "fsl,sec-v4.0-job-ring"; 369 reg = <0x20000 0x10000>; 370 interrupts = <0 72 0x4>; 371 }; 372 373 sec_jr2: jr@30000 { 374 compatible = "fsl,sec-v5.4-job-ring", 375 "fsl,sec-v5.0-job-ring", 376 "fsl,sec-v4.0-job-ring"; 377 reg = <0x30000 0x10000>; 378 interrupts = <0 73 0x4>; 379 }; 380 381 sec_jr3: jr@40000 { 382 compatible = "fsl,sec-v5.4-job-ring", 383 "fsl,sec-v5.0-job-ring", 384 "fsl,sec-v4.0-job-ring"; 385 reg = <0x40000 0x10000>; 386 interrupts = <0 74 0x4>; 387 }; 388 }; 389 390 sfp: efuse@1e80000 { 391 compatible = "fsl,ls1021a-sfp"; 392 reg = <0x0 0x1e80000 0x0 0x10000>; 393 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 394 QORIQ_CLK_PLL_DIV(4)>; 395 clock-names = "sfp"; 396 }; 397 398 dcfg: dcfg@1ee0000 { 399 compatible = "fsl,ls1043a-dcfg", "syscon"; 400 reg = <0x0 0x1ee0000 0x0 0x1000>; 401 big-endian; 402 }; 403 404 ifc: memory-controller@1530000 { 405 compatible = "fsl,ifc"; 406 reg = <0x0 0x1530000 0x0 0x10000>; 407 interrupts = <0 43 0x4>; 408 }; 409 410 qspi: spi@1550000 { 411 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <0x0 0x1550000 0x0 0x10000>, 415 <0x0 0x40000000 0x0 0x4000000>; 416 reg-names = "QuadSPI", "QuadSPI-memory"; 417 interrupts = <0 99 0x4>; 418 clock-names = "qspi_en", "qspi"; 419 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 420 QORIQ_CLK_PLL_DIV(1)>, 421 <&clockgen QORIQ_CLK_PLATFORM_PLL 422 QORIQ_CLK_PLL_DIV(1)>; 423 status = "disabled"; 424 }; 425 426 esdhc: esdhc@1560000 { 427 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 428 reg = <0x0 0x1560000 0x0 0x10000>; 429 interrupts = <0 62 0x4>; 430 clock-frequency = <0>; 431 voltage-ranges = <1800 1800 3300 3300>; 432 sdhci,auto-cmd12; 433 big-endian; 434 bus-width = <4>; 435 }; 436 437 ddr: memory-controller@1080000 { 438 compatible = "fsl,qoriq-memory-controller"; 439 reg = <0x0 0x1080000 0x0 0x1000>; 440 interrupts = <0 144 0x4>; 441 big-endian; 442 }; 443 444 tmu: tmu@1f00000 { 445 compatible = "fsl,qoriq-tmu"; 446 reg = <0x0 0x1f00000 0x0 0x10000>; 447 interrupts = <0 33 0x4>; 448 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 449 fsl,tmu-calibration = <0x00000000 0x00000023 450 0x00000001 0x0000002a 451 0x00000002 0x00000031 452 0x00000003 0x00000037 453 0x00000004 0x0000003e 454 0x00000005 0x00000044 455 0x00000006 0x0000004b 456 0x00000007 0x00000051 457 0x00000008 0x00000058 458 0x00000009 0x0000005e 459 0x0000000a 0x00000065 460 0x0000000b 0x0000006b 461 462 0x00010000 0x00000023 463 0x00010001 0x0000002b 464 0x00010002 0x00000033 465 0x00010003 0x0000003b 466 0x00010004 0x00000043 467 0x00010005 0x0000004b 468 0x00010006 0x00000054 469 0x00010007 0x0000005c 470 0x00010008 0x00000064 471 0x00010009 0x0000006c 472 473 0x00020000 0x00000021 474 0x00020001 0x0000002c 475 0x00020002 0x00000036 476 0x00020003 0x00000040 477 0x00020004 0x0000004b 478 0x00020005 0x00000055 479 0x00020006 0x0000005f 480 481 0x00030000 0x00000013 482 0x00030001 0x0000001d 483 0x00030002 0x00000028 484 0x00030003 0x00000032 485 0x00030004 0x0000003d 486 0x00030005 0x00000047 487 0x00030006 0x00000052 488 0x00030007 0x0000005c>; 489 #thermal-sensor-cells = <1>; 490 }; 491 492 qman: qman@1880000 { 493 compatible = "fsl,qman"; 494 reg = <0x0 0x1880000 0x0 0x10000>; 495 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 496 memory-region = <&qman_fqd &qman_pfdr>; 497 }; 498 499 bman: bman@1890000 { 500 compatible = "fsl,bman"; 501 reg = <0x0 0x1890000 0x0 0x10000>; 502 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 503 memory-region = <&bman_fbpr>; 504 }; 505 506 bportals: bman-portals@508000000 { 507 ranges = <0x0 0x5 0x08000000 0x8000000>; 508 }; 509 510 qportals: qman-portals@500000000 { 511 ranges = <0x0 0x5 0x00000000 0x8000000>; 512 }; 513 514 dspi0: spi@2100000 { 515 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 reg = <0x0 0x2100000 0x0 0x10000>; 519 interrupts = <0 64 0x4>; 520 clock-names = "dspi"; 521 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 522 QORIQ_CLK_PLL_DIV(1)>; 523 spi-num-chipselects = <5>; 524 big-endian; 525 status = "disabled"; 526 }; 527 528 dspi1: spi@2110000 { 529 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 reg = <0x0 0x2110000 0x0 0x10000>; 533 interrupts = <0 65 0x4>; 534 clock-names = "dspi"; 535 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 536 QORIQ_CLK_PLL_DIV(1)>; 537 spi-num-chipselects = <5>; 538 big-endian; 539 status = "disabled"; 540 }; 541 542 i2c0: i2c@2180000 { 543 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 reg = <0x0 0x2180000 0x0 0x10000>; 547 interrupts = <0 56 0x4>; 548 clock-names = "i2c"; 549 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 550 QORIQ_CLK_PLL_DIV(1)>; 551 dmas = <&edma0 1 38>, 552 <&edma0 1 39>; 553 dma-names = "rx", "tx"; 554 status = "disabled"; 555 }; 556 557 i2c1: i2c@2190000 { 558 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 reg = <0x0 0x2190000 0x0 0x10000>; 562 interrupts = <0 57 0x4>; 563 clock-names = "i2c"; 564 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 565 QORIQ_CLK_PLL_DIV(1)>; 566 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 567 status = "disabled"; 568 }; 569 570 i2c2: i2c@21a0000 { 571 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 reg = <0x0 0x21a0000 0x0 0x10000>; 575 interrupts = <0 58 0x4>; 576 clock-names = "i2c"; 577 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 578 QORIQ_CLK_PLL_DIV(1)>; 579 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 580 status = "disabled"; 581 }; 582 583 i2c3: i2c@21b0000 { 584 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 reg = <0x0 0x21b0000 0x0 0x10000>; 588 interrupts = <0 59 0x4>; 589 clock-names = "i2c"; 590 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 591 QORIQ_CLK_PLL_DIV(1)>; 592 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 593 status = "disabled"; 594 }; 595 596 duart0: serial@21c0500 { 597 compatible = "fsl,ns16550", "ns16550a"; 598 reg = <0x00 0x21c0500 0x0 0x100>; 599 interrupts = <0 54 0x4>; 600 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 601 QORIQ_CLK_PLL_DIV(1)>; 602 }; 603 604 duart1: serial@21c0600 { 605 compatible = "fsl,ns16550", "ns16550a"; 606 reg = <0x00 0x21c0600 0x0 0x100>; 607 interrupts = <0 54 0x4>; 608 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 609 QORIQ_CLK_PLL_DIV(1)>; 610 }; 611 612 duart2: serial@21d0500 { 613 compatible = "fsl,ns16550", "ns16550a"; 614 reg = <0x0 0x21d0500 0x0 0x100>; 615 interrupts = <0 55 0x4>; 616 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 617 QORIQ_CLK_PLL_DIV(1)>; 618 }; 619 620 duart3: serial@21d0600 { 621 compatible = "fsl,ns16550", "ns16550a"; 622 reg = <0x0 0x21d0600 0x0 0x100>; 623 interrupts = <0 55 0x4>; 624 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 625 QORIQ_CLK_PLL_DIV(1)>; 626 }; 627 628 gpio1: gpio@2300000 { 629 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 630 reg = <0x0 0x2300000 0x0 0x10000>; 631 interrupts = <0 66 0x4>; 632 gpio-controller; 633 #gpio-cells = <2>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 }; 637 638 gpio2: gpio@2310000 { 639 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 640 reg = <0x0 0x2310000 0x0 0x10000>; 641 interrupts = <0 67 0x4>; 642 gpio-controller; 643 #gpio-cells = <2>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 648 gpio3: gpio@2320000 { 649 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 650 reg = <0x0 0x2320000 0x0 0x10000>; 651 interrupts = <0 68 0x4>; 652 gpio-controller; 653 #gpio-cells = <2>; 654 interrupt-controller; 655 #interrupt-cells = <2>; 656 }; 657 658 gpio4: gpio@2330000 { 659 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 660 reg = <0x0 0x2330000 0x0 0x10000>; 661 interrupts = <0 134 0x4>; 662 gpio-controller; 663 #gpio-cells = <2>; 664 interrupt-controller; 665 #interrupt-cells = <2>; 666 }; 667 668 uqe: uqe@2400000 { 669 #address-cells = <1>; 670 #size-cells = <1>; 671 compatible = "fsl,qe", "simple-bus"; 672 ranges = <0x0 0x0 0x2400000 0x40000>; 673 reg = <0x0 0x2400000 0x0 0x480>; 674 brg-frequency = <100000000>; 675 bus-frequency = <200000000>; 676 fsl,qe-num-riscs = <1>; 677 fsl,qe-num-snums = <28>; 678 679 qeic: qeic@80 { 680 compatible = "fsl,qe-ic"; 681 reg = <0x80 0x80>; 682 #address-cells = <0>; 683 interrupt-controller; 684 #interrupt-cells = <1>; 685 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 687 }; 688 689 si1: si@700 { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 compatible = "fsl,ls1043-qe-si", 693 "fsl,t1040-qe-si"; 694 reg = <0x700 0x80>; 695 }; 696 697 siram1: siram@1000 { 698 #address-cells = <1>; 699 #size-cells = <1>; 700 compatible = "fsl,ls1043-qe-siram", 701 "fsl,t1040-qe-siram"; 702 reg = <0x1000 0x800>; 703 }; 704 705 ucc@2000 { 706 cell-index = <1>; 707 reg = <0x2000 0x200>; 708 interrupts = <32>; 709 interrupt-parent = <&qeic>; 710 }; 711 712 ucc@2200 { 713 cell-index = <3>; 714 reg = <0x2200 0x200>; 715 interrupts = <34>; 716 interrupt-parent = <&qeic>; 717 }; 718 719 muram@10000 { 720 #address-cells = <1>; 721 #size-cells = <1>; 722 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 723 ranges = <0x0 0x10000 0x6000>; 724 725 data-only@0 { 726 compatible = "fsl,qe-muram-data", 727 "fsl,cpm-muram-data"; 728 reg = <0x0 0x6000>; 729 }; 730 }; 731 }; 732 733 lpuart0: serial@2950000 { 734 compatible = "fsl,ls1021a-lpuart"; 735 reg = <0x0 0x2950000 0x0 0x1000>; 736 interrupts = <0 48 0x4>; 737 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; 738 clock-names = "ipg"; 739 status = "disabled"; 740 }; 741 742 lpuart1: serial@2960000 { 743 compatible = "fsl,ls1021a-lpuart"; 744 reg = <0x0 0x2960000 0x0 0x1000>; 745 interrupts = <0 49 0x4>; 746 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 747 QORIQ_CLK_PLL_DIV(1)>; 748 clock-names = "ipg"; 749 status = "disabled"; 750 }; 751 752 lpuart2: serial@2970000 { 753 compatible = "fsl,ls1021a-lpuart"; 754 reg = <0x0 0x2970000 0x0 0x1000>; 755 interrupts = <0 50 0x4>; 756 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 757 QORIQ_CLK_PLL_DIV(1)>; 758 clock-names = "ipg"; 759 status = "disabled"; 760 }; 761 762 lpuart3: serial@2980000 { 763 compatible = "fsl,ls1021a-lpuart"; 764 reg = <0x0 0x2980000 0x0 0x1000>; 765 interrupts = <0 51 0x4>; 766 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 767 QORIQ_CLK_PLL_DIV(1)>; 768 clock-names = "ipg"; 769 status = "disabled"; 770 }; 771 772 lpuart4: serial@2990000 { 773 compatible = "fsl,ls1021a-lpuart"; 774 reg = <0x0 0x2990000 0x0 0x1000>; 775 interrupts = <0 52 0x4>; 776 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 777 QORIQ_CLK_PLL_DIV(1)>; 778 clock-names = "ipg"; 779 status = "disabled"; 780 }; 781 782 lpuart5: serial@29a0000 { 783 compatible = "fsl,ls1021a-lpuart"; 784 reg = <0x0 0x29a0000 0x0 0x1000>; 785 interrupts = <0 53 0x4>; 786 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 787 QORIQ_CLK_PLL_DIV(1)>; 788 clock-names = "ipg"; 789 status = "disabled"; 790 }; 791 792 wdog0: watchdog@2ad0000 { 793 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 794 reg = <0x0 0x2ad0000 0x0 0x10000>; 795 interrupts = <0 83 0x4>; 796 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 797 QORIQ_CLK_PLL_DIV(1)>; 798 clock-names = "wdog"; 799 big-endian; 800 }; 801 802 edma0: dma-controller@2c00000 { 803 #dma-cells = <2>; 804 compatible = "fsl,vf610-edma"; 805 reg = <0x0 0x2c00000 0x0 0x10000>, 806 <0x0 0x2c10000 0x0 0x10000>, 807 <0x0 0x2c20000 0x0 0x10000>; 808 interrupts = <0 103 0x4>, 809 <0 103 0x4>; 810 interrupt-names = "edma-tx", "edma-err"; 811 dma-channels = <32>; 812 big-endian; 813 clock-names = "dmamux0", "dmamux1"; 814 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 815 QORIQ_CLK_PLL_DIV(1)>, 816 <&clockgen QORIQ_CLK_PLATFORM_PLL 817 QORIQ_CLK_PLL_DIV(1)>; 818 }; 819 820 aux_bus: aux_bus { 821 #address-cells = <2>; 822 #size-cells = <2>; 823 compatible = "simple-bus"; 824 ranges; 825 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 826 827 usb0: usb@2f00000 { 828 compatible = "snps,dwc3"; 829 reg = <0x0 0x2f00000 0x0 0x10000>; 830 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; 831 dr_mode = "host"; 832 snps,quirk-frame-length-adjustment = <0x20>; 833 snps,dis_rxdet_inp3_quirk; 834 usb3-lpm-capable; 835 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 836 status = "disabled"; 837 }; 838 839 usb1: usb@3000000 { 840 compatible = "snps,dwc3"; 841 reg = <0x0 0x3000000 0x0 0x10000>; 842 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 843 dr_mode = "host"; 844 snps,quirk-frame-length-adjustment = <0x20>; 845 snps,dis_rxdet_inp3_quirk; 846 usb3-lpm-capable; 847 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 848 status = "disabled"; 849 }; 850 851 usb2: usb@3100000 { 852 compatible = "snps,dwc3"; 853 reg = <0x0 0x3100000 0x0 0x10000>; 854 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 855 dr_mode = "host"; 856 snps,quirk-frame-length-adjustment = <0x20>; 857 snps,dis_rxdet_inp3_quirk; 858 usb3-lpm-capable; 859 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 860 status = "disabled"; 861 }; 862 863 sata: sata@3200000 { 864 compatible = "fsl,ls1043a-ahci"; 865 reg = <0x0 0x3200000 0x0 0x10000>, 866 <0x0 0x20140520 0x0 0x4>; 867 reg-names = "ahci", "sata-ecc"; 868 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 870 QORIQ_CLK_PLL_DIV(1)>; 871 dma-coherent; 872 }; 873 }; 874 875 msi1: msi-controller1@1571000 { 876 compatible = "fsl,ls1043a-msi"; 877 reg = <0x0 0x1571000 0x0 0x8>; 878 msi-controller; 879 interrupts = <0 116 0x4>; 880 }; 881 882 msi2: msi-controller2@1572000 { 883 compatible = "fsl,ls1043a-msi"; 884 reg = <0x0 0x1572000 0x0 0x8>; 885 msi-controller; 886 interrupts = <0 126 0x4>; 887 }; 888 889 msi3: msi-controller3@1573000 { 890 compatible = "fsl,ls1043a-msi"; 891 reg = <0x0 0x1573000 0x0 0x8>; 892 msi-controller; 893 interrupts = <0 160 0x4>; 894 }; 895 896 pcie1: pcie@3400000 { 897 compatible = "fsl,ls1043a-pcie"; 898 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 899 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 900 reg-names = "regs", "config"; 901 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>, 902 <0 118 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "pme", "aer"; 904 #address-cells = <3>; 905 #size-cells = <2>; 906 device_type = "pci"; 907 num-viewport = <6>; 908 bus-range = <0x0 0xff>; 909 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 910 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 911 msi-parent = <&msi1>, <&msi2>, <&msi3>; 912 #interrupt-cells = <1>; 913 interrupt-map-mask = <0 0 0 7>; 914 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, 915 <0000 0 0 2 &gic 0 111 0x4>, 916 <0000 0 0 3 &gic 0 112 0x4>, 917 <0000 0 0 4 &gic 0 113 0x4>; 918 fsl,pcie-scfg = <&scfg 0>; 919 big-endian; 920 status = "disabled"; 921 }; 922 923 pcie2: pcie@3500000 { 924 compatible = "fsl,ls1043a-pcie"; 925 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 926 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 927 reg-names = "regs", "config"; 928 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>, 929 <0 128 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "pme", "aer"; 931 #address-cells = <3>; 932 #size-cells = <2>; 933 device_type = "pci"; 934 num-viewport = <6>; 935 bus-range = <0x0 0xff>; 936 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 937 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 938 msi-parent = <&msi1>, <&msi2>, <&msi3>; 939 #interrupt-cells = <1>; 940 interrupt-map-mask = <0 0 0 7>; 941 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, 942 <0000 0 0 2 &gic 0 121 0x4>, 943 <0000 0 0 3 &gic 0 122 0x4>, 944 <0000 0 0 4 &gic 0 123 0x4>; 945 fsl,pcie-scfg = <&scfg 1>; 946 big-endian; 947 status = "disabled"; 948 }; 949 950 pcie3: pcie@3600000 { 951 compatible = "fsl,ls1043a-pcie"; 952 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 953 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 954 reg-names = "regs", "config"; 955 interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>, 956 <0 162 IRQ_TYPE_LEVEL_HIGH>; 957 interrupt-names = "pme", "aer"; 958 #address-cells = <3>; 959 #size-cells = <2>; 960 device_type = "pci"; 961 num-viewport = <6>; 962 bus-range = <0x0 0xff>; 963 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 964 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 965 msi-parent = <&msi1>, <&msi2>, <&msi3>; 966 #interrupt-cells = <1>; 967 interrupt-map-mask = <0 0 0 7>; 968 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, 969 <0000 0 0 2 &gic 0 155 0x4>, 970 <0000 0 0 3 &gic 0 156 0x4>, 971 <0000 0 0 4 &gic 0 157 0x4>; 972 fsl,pcie-scfg = <&scfg 2>; 973 big-endian; 974 status = "disabled"; 975 }; 976 977 qdma: dma-controller@8380000 { 978 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; 979 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 980 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 981 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 982 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 987 interrupt-names = "qdma-error", "qdma-queue0", 988 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 989 dma-channels = <8>; 990 block-number = <1>; 991 block-offset = <0x10000>; 992 fsl,dma-queues = <2>; 993 status-sizes = <64>; 994 queue-sizes = <64 64>; 995 big-endian; 996 }; 997 998 rcpm: power-controller@1ee2140 { 999 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1000 reg = <0x0 0x1ee2140 0x0 0x4>; 1001 #fsl,rcpm-wakeup-cells = <1>; 1002 }; 1003 1004 ftm_alarm0: timer@29d0000 { 1005 compatible = "fsl,ls1043a-ftm-alarm"; 1006 reg = <0x0 0x29d0000 0x0 0x10000>; 1007 fsl,rcpm-wakeup = <&rcpm 0x20000>; 1008 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1009 big-endian; 1010 }; 1011 }; 1012 1013 firmware { 1014 optee { 1015 compatible = "linaro,optee-tz"; 1016 method = "smc"; 1017 }; 1018 }; 1019 1020}; 1021 1022#include "qoriq-qman-portals.dtsi" 1023#include "qoriq-bman-portals.dtsi" 1024