1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 4 * 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <Mingkai.hu@freescale.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1043a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 rtc1 = &ftm_alarm0; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 /* 40 * We expect the enable-method for cpu's to be "psci", but this 41 * is dependent on the SoC FW, which will fill this in. 42 * 43 * Currently supported enable-method is psci v0.2 44 */ 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 50 next-level-cache = <&l2>; 51 cpu-idle-states = <&CPU_PH20>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x1>; 59 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 60 next-level-cache = <&l2>; 61 cpu-idle-states = <&CPU_PH20>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x2>; 69 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 70 next-level-cache = <&l2>; 71 cpu-idle-states = <&CPU_PH20>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x3>; 79 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 80 next-level-cache = <&l2>; 81 cpu-idle-states = <&CPU_PH20>; 82 #cooling-cells = <2>; 83 }; 84 85 l2: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 }; 90 }; 91 92 idle-states { 93 /* 94 * PSCI node is not added default, U-boot will add missing 95 * parts if it determines to use PSCI. 96 */ 97 entry-method = "psci"; 98 99 CPU_PH20: cpu-ph20 { 100 compatible = "arm,idle-state"; 101 idle-state-name = "PH20"; 102 arm,psci-suspend-param = <0x0>; 103 entry-latency-us = <1000>; 104 exit-latency-us = <1000>; 105 min-residency-us = <3000>; 106 }; 107 }; 108 109 memory@80000000 { 110 device_type = "memory"; 111 reg = <0x0 0x80000000 0 0x80000000>; 112 /* DRAM space 1, size: 2GiB DRAM */ 113 }; 114 115 reserved-memory { 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges; 119 120 bman_fbpr: bman-fbpr { 121 compatible = "shared-dma-pool"; 122 size = <0 0x1000000>; 123 alignment = <0 0x1000000>; 124 no-map; 125 }; 126 127 qman_fqd: qman-fqd { 128 compatible = "shared-dma-pool"; 129 size = <0 0x400000>; 130 alignment = <0 0x400000>; 131 no-map; 132 }; 133 134 qman_pfdr: qman-pfdr { 135 compatible = "shared-dma-pool"; 136 size = <0 0x2000000>; 137 alignment = <0 0x2000000>; 138 no-map; 139 }; 140 }; 141 142 sysclk: sysclk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 clock-frequency = <100000000>; 146 clock-output-names = "sysclk"; 147 }; 148 149 reboot { 150 compatible = "syscon-reboot"; 151 regmap = <&dcfg>; 152 offset = <0xb0>; 153 mask = <0x02>; 154 }; 155 156 thermal-zones { 157 ddr-thermal { 158 polling-delay-passive = <1000>; 159 polling-delay = <5000>; 160 thermal-sensors = <&tmu 0>; 161 162 trips { 163 ddr-ctrler-alert { 164 temperature = <85000>; 165 hysteresis = <2000>; 166 type = "passive"; 167 }; 168 169 ddr-ctrler-crit { 170 temperature = <95000>; 171 hysteresis = <2000>; 172 type = "critical"; 173 }; 174 }; 175 }; 176 177 serdes-thermal { 178 polling-delay-passive = <1000>; 179 polling-delay = <5000>; 180 thermal-sensors = <&tmu 1>; 181 182 trips { 183 serdes-alert { 184 temperature = <85000>; 185 hysteresis = <2000>; 186 type = "passive"; 187 }; 188 189 serdes-crit { 190 temperature = <95000>; 191 hysteresis = <2000>; 192 type = "critical"; 193 }; 194 }; 195 }; 196 197 fman-thermal { 198 polling-delay-passive = <1000>; 199 polling-delay = <5000>; 200 thermal-sensors = <&tmu 2>; 201 202 trips { 203 fman-alert { 204 temperature = <85000>; 205 hysteresis = <2000>; 206 type = "passive"; 207 }; 208 209 fman-crit { 210 temperature = <95000>; 211 hysteresis = <2000>; 212 type = "critical"; 213 }; 214 }; 215 }; 216 217 cluster-thermal { 218 polling-delay-passive = <1000>; 219 polling-delay = <5000>; 220 thermal-sensors = <&tmu 3>; 221 222 trips { 223 core_cluster_alert: core-cluster-alert { 224 temperature = <85000>; 225 hysteresis = <2000>; 226 type = "passive"; 227 }; 228 229 core_cluster_crit: core-cluster-crit { 230 temperature = <95000>; 231 hysteresis = <2000>; 232 type = "critical"; 233 }; 234 }; 235 236 cooling-maps { 237 map0 { 238 trip = <&core_cluster_alert>; 239 cooling-device = 240 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 241 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 242 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 243 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 244 }; 245 }; 246 }; 247 248 sec-thermal { 249 polling-delay-passive = <1000>; 250 polling-delay = <5000>; 251 thermal-sensors = <&tmu 4>; 252 253 trips { 254 sec-alert { 255 temperature = <85000>; 256 hysteresis = <2000>; 257 type = "passive"; 258 }; 259 260 sec-crit { 261 temperature = <95000>; 262 hysteresis = <2000>; 263 type = "critical"; 264 }; 265 }; 266 }; 267 }; 268 269 timer { 270 compatible = "arm,armv8-timer"; 271 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 272 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 273 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 274 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 275 fsl,erratum-a008585; 276 }; 277 278 pmu { 279 compatible = "arm,cortex-a53-pmu"; 280 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-affinity = <&cpu0>, 285 <&cpu1>, 286 <&cpu2>, 287 <&cpu3>; 288 }; 289 290 gic: interrupt-controller@1400000 { 291 compatible = "arm,gic-400"; 292 #interrupt-cells = <3>; 293 interrupt-controller; 294 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 295 <0x0 0x1402000 0 0x2000>, /* GICC */ 296 <0x0 0x1404000 0 0x2000>, /* GICH */ 297 <0x0 0x1406000 0 0x2000>; /* GICV */ 298 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 299 }; 300 301 soc: soc { 302 compatible = "simple-bus"; 303 #address-cells = <2>; 304 #size-cells = <2>; 305 ranges; 306 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 307 dma-coherent; 308 309 clockgen: clocking@1ee1000 { 310 compatible = "fsl,ls1043a-clockgen"; 311 reg = <0x0 0x1ee1000 0x0 0x1000>; 312 #clock-cells = <2>; 313 clocks = <&sysclk>; 314 }; 315 316 scfg: scfg@1570000 { 317 compatible = "fsl,ls1043a-scfg", "syscon"; 318 reg = <0x0 0x1570000 0x0 0x10000>; 319 big-endian; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges = <0x0 0x0 0x1570000 0x10000>; 323 324 extirq: interrupt-controller@1ac { 325 compatible = "fsl,ls1043a-extirq"; 326 #interrupt-cells = <2>; 327 #address-cells = <0>; 328 interrupt-controller; 329 reg = <0x1ac 4>; 330 interrupt-map = 331 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 332 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 333 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 334 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 335 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 336 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 337 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 338 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 339 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 340 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 341 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 342 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-map-mask = <0xf 0x0>; 344 }; 345 }; 346 347 crypto: crypto@1700000 { 348 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 349 "fsl,sec-v4.0"; 350 fsl,sec-era = <3>; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges = <0x0 0x00 0x1700000 0x100000>; 354 reg = <0x00 0x1700000 0x0 0x100000>; 355 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 356 dma-coherent; 357 358 sec_jr0: jr@10000 { 359 compatible = "fsl,sec-v5.4-job-ring", 360 "fsl,sec-v5.0-job-ring", 361 "fsl,sec-v4.0-job-ring"; 362 reg = <0x10000 0x10000>; 363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 }; 365 366 sec_jr1: jr@20000 { 367 compatible = "fsl,sec-v5.4-job-ring", 368 "fsl,sec-v5.0-job-ring", 369 "fsl,sec-v4.0-job-ring"; 370 reg = <0x20000 0x10000>; 371 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 372 }; 373 374 sec_jr2: jr@30000 { 375 compatible = "fsl,sec-v5.4-job-ring", 376 "fsl,sec-v5.0-job-ring", 377 "fsl,sec-v4.0-job-ring"; 378 reg = <0x30000 0x10000>; 379 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 380 }; 381 382 sec_jr3: jr@40000 { 383 compatible = "fsl,sec-v5.4-job-ring", 384 "fsl,sec-v5.0-job-ring", 385 "fsl,sec-v4.0-job-ring"; 386 reg = <0x40000 0x10000>; 387 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 388 }; 389 }; 390 391 sfp: efuse@1e80000 { 392 compatible = "fsl,ls1021a-sfp"; 393 reg = <0x0 0x1e80000 0x0 0x10000>; 394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 395 QORIQ_CLK_PLL_DIV(4)>; 396 clock-names = "sfp"; 397 }; 398 399 dcfg: dcfg@1ee0000 { 400 compatible = "fsl,ls1043a-dcfg", "syscon"; 401 reg = <0x0 0x1ee0000 0x0 0x1000>; 402 big-endian; 403 }; 404 405 ifc: memory-controller@1530000 { 406 compatible = "fsl,ifc"; 407 reg = <0x0 0x1530000 0x0 0x10000>; 408 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 409 }; 410 411 qspi: spi@1550000 { 412 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0x0 0x1550000 0x0 0x10000>, 416 <0x0 0x40000000 0x0 0x4000000>; 417 reg-names = "QuadSPI", "QuadSPI-memory"; 418 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 419 clock-names = "qspi_en", "qspi"; 420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 421 QORIQ_CLK_PLL_DIV(1)>, 422 <&clockgen QORIQ_CLK_PLATFORM_PLL 423 QORIQ_CLK_PLL_DIV(1)>; 424 status = "disabled"; 425 }; 426 427 esdhc: mmc@1560000 { 428 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 429 reg = <0x0 0x1560000 0x0 0x10000>; 430 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 431 clock-frequency = <0>; 432 voltage-ranges = <1800 1800 3300 3300>; 433 sdhci,auto-cmd12; 434 bus-width = <4>; 435 }; 436 437 ddr: memory-controller@1080000 { 438 compatible = "fsl,qoriq-memory-controller"; 439 reg = <0x0 0x1080000 0x0 0x1000>; 440 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 441 }; 442 443 tmu: tmu@1f00000 { 444 compatible = "fsl,qoriq-tmu"; 445 reg = <0x0 0x1f00000 0x0 0x10000>; 446 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 447 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 448 fsl,tmu-calibration = 449 <0x00000000 0x00000023>, 450 <0x00000001 0x0000002a>, 451 <0x00000002 0x00000031>, 452 <0x00000003 0x00000037>, 453 <0x00000004 0x0000003e>, 454 <0x00000005 0x00000044>, 455 <0x00000006 0x0000004b>, 456 <0x00000007 0x00000051>, 457 <0x00000008 0x00000058>, 458 <0x00000009 0x0000005e>, 459 <0x0000000a 0x00000065>, 460 <0x0000000b 0x0000006b>, 461 462 <0x00010000 0x00000023>, 463 <0x00010001 0x0000002b>, 464 <0x00010002 0x00000033>, 465 <0x00010003 0x0000003b>, 466 <0x00010004 0x00000043>, 467 <0x00010005 0x0000004b>, 468 <0x00010006 0x00000054>, 469 <0x00010007 0x0000005c>, 470 <0x00010008 0x00000064>, 471 <0x00010009 0x0000006c>, 472 473 <0x00020000 0x00000021>, 474 <0x00020001 0x0000002c>, 475 <0x00020002 0x00000036>, 476 <0x00020003 0x00000040>, 477 <0x00020004 0x0000004b>, 478 <0x00020005 0x00000055>, 479 <0x00020006 0x0000005f>, 480 481 <0x00030000 0x00000013>, 482 <0x00030001 0x0000001d>, 483 <0x00030002 0x00000028>, 484 <0x00030003 0x00000032>, 485 <0x00030004 0x0000003d>, 486 <0x00030005 0x00000047>, 487 <0x00030006 0x00000052>, 488 <0x00030007 0x0000005c>; 489 #thermal-sensor-cells = <1>; 490 }; 491 492 qman: qman@1880000 { 493 compatible = "fsl,qman"; 494 reg = <0x0 0x1880000 0x0 0x10000>; 495 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 496 memory-region = <&qman_fqd &qman_pfdr>; 497 }; 498 499 bman: bman@1890000 { 500 compatible = "fsl,bman"; 501 reg = <0x0 0x1890000 0x0 0x10000>; 502 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 503 memory-region = <&bman_fbpr>; 504 }; 505 506 bportals: bman-portals-bus@508000000 { 507 ranges = <0x0 0x5 0x08000000 0x8000000>; 508 }; 509 510 qportals: qman-portals-bus@500000000 { 511 ranges = <0x0 0x5 0x00000000 0x8000000>; 512 }; 513 514 dspi0: spi@2100000 { 515 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 reg = <0x0 0x2100000 0x0 0x10000>; 519 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 520 clock-names = "dspi"; 521 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 522 QORIQ_CLK_PLL_DIV(1)>; 523 spi-num-chipselects = <5>; 524 big-endian; 525 status = "disabled"; 526 }; 527 528 i2c0: i2c@2180000 { 529 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 reg = <0x0 0x2180000 0x0 0x10000>; 533 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 534 clock-names = "ipg"; 535 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 536 QORIQ_CLK_PLL_DIV(1)>; 537 dmas = <&edma0 1 38>, 538 <&edma0 1 39>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 i2c1: i2c@2190000 { 544 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0x0 0x2190000 0x0 0x10000>; 548 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 549 clock-names = "ipg"; 550 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 551 QORIQ_CLK_PLL_DIV(1)>; 552 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 553 dmas = <&edma0 1 36>, 554 <&edma0 1 37>; 555 dma-names = "rx", "tx"; 556 status = "disabled"; 557 }; 558 559 i2c2: i2c@21a0000 { 560 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 reg = <0x0 0x21a0000 0x0 0x10000>; 564 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 565 clock-names = "ipg"; 566 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 567 QORIQ_CLK_PLL_DIV(1)>; 568 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 569 dmas = <&edma0 1 34>, 570 <&edma0 1 35>; 571 dma-names = "rx", "tx"; 572 status = "disabled"; 573 }; 574 575 i2c3: i2c@21b0000 { 576 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 reg = <0x0 0x21b0000 0x0 0x10000>; 580 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 581 clock-names = "ipg"; 582 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 583 QORIQ_CLK_PLL_DIV(1)>; 584 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 585 dmas = <&edma0 1 40>, 586 <&edma0 1 41>; 587 dma-names = "rx", "tx"; 588 status = "disabled"; 589 }; 590 591 duart0: serial@21c0500 { 592 compatible = "fsl,ns16550", "ns16550a"; 593 reg = <0x00 0x21c0500 0x0 0x100>; 594 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 596 QORIQ_CLK_PLL_DIV(1)>; 597 }; 598 599 duart1: serial@21c0600 { 600 compatible = "fsl,ns16550", "ns16550a"; 601 reg = <0x00 0x21c0600 0x0 0x100>; 602 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 604 QORIQ_CLK_PLL_DIV(1)>; 605 }; 606 607 duart2: serial@21d0500 { 608 compatible = "fsl,ns16550", "ns16550a"; 609 reg = <0x0 0x21d0500 0x0 0x100>; 610 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 612 QORIQ_CLK_PLL_DIV(1)>; 613 }; 614 615 duart3: serial@21d0600 { 616 compatible = "fsl,ns16550", "ns16550a"; 617 reg = <0x0 0x21d0600 0x0 0x100>; 618 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 620 QORIQ_CLK_PLL_DIV(1)>; 621 }; 622 623 gpio1: gpio@2300000 { 624 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 625 reg = <0x0 0x2300000 0x0 0x10000>; 626 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 }; 632 633 gpio2: gpio@2310000 { 634 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 635 reg = <0x0 0x2310000 0x0 0x10000>; 636 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 637 gpio-controller; 638 #gpio-cells = <2>; 639 interrupt-controller; 640 #interrupt-cells = <2>; 641 }; 642 643 gpio3: gpio@2320000 { 644 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 645 reg = <0x0 0x2320000 0x0 0x10000>; 646 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 647 gpio-controller; 648 #gpio-cells = <2>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 }; 652 653 gpio4: gpio@2330000 { 654 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 655 reg = <0x0 0x2330000 0x0 0x10000>; 656 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 657 gpio-controller; 658 #gpio-cells = <2>; 659 interrupt-controller; 660 #interrupt-cells = <2>; 661 }; 662 663 uqe: uqe-bus@2400000 { 664 #address-cells = <1>; 665 #size-cells = <1>; 666 compatible = "fsl,qe", "simple-bus"; 667 ranges = <0x0 0x0 0x2400000 0x40000>; 668 reg = <0x0 0x2400000 0x0 0x480>; 669 brg-frequency = <100000000>; 670 bus-frequency = <200000000>; 671 fsl,qe-num-riscs = <1>; 672 fsl,qe-num-snums = <28>; 673 674 qeic: qeic@80 { 675 compatible = "fsl,qe-ic"; 676 reg = <0x80 0x80>; 677 interrupt-controller; 678 #interrupt-cells = <1>; 679 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 681 }; 682 683 si1: si@700 { 684 compatible = "fsl,ls1043-qe-si", 685 "fsl,t1040-qe-si"; 686 reg = <0x700 0x80>; 687 }; 688 689 siram1: siram@1000 { 690 compatible = "fsl,ls1043-qe-siram", 691 "fsl,t1040-qe-siram"; 692 reg = <0x1000 0x800>; 693 }; 694 695 ucc@2000 { 696 cell-index = <1>; 697 reg = <0x2000 0x200>; 698 interrupts = <32>; 699 interrupt-parent = <&qeic>; 700 }; 701 702 ucc@2200 { 703 cell-index = <3>; 704 reg = <0x2200 0x200>; 705 interrupts = <34>; 706 interrupt-parent = <&qeic>; 707 }; 708 709 muram@10000 { 710 #address-cells = <1>; 711 #size-cells = <1>; 712 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 713 ranges = <0x0 0x10000 0x6000>; 714 715 data-only@0 { 716 compatible = "fsl,qe-muram-data", 717 "fsl,cpm-muram-data"; 718 reg = <0x0 0x6000>; 719 }; 720 }; 721 }; 722 723 lpuart0: serial@2950000 { 724 compatible = "fsl,ls1021a-lpuart"; 725 reg = <0x0 0x2950000 0x0 0x1000>; 726 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; 728 clock-names = "ipg"; 729 dmas = <&edma0 1 32>, 730 <&edma0 1 33>; 731 dma-names = "rx", "tx"; 732 status = "disabled"; 733 }; 734 735 lpuart1: serial@2960000 { 736 compatible = "fsl,ls1021a-lpuart"; 737 reg = <0x0 0x2960000 0x0 0x1000>; 738 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 740 QORIQ_CLK_PLL_DIV(1)>; 741 clock-names = "ipg"; 742 dmas = <&edma0 1 30>, 743 <&edma0 1 31>; 744 dma-names = "rx", "tx"; 745 status = "disabled"; 746 }; 747 748 lpuart2: serial@2970000 { 749 compatible = "fsl,ls1021a-lpuart"; 750 reg = <0x0 0x2970000 0x0 0x1000>; 751 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 753 QORIQ_CLK_PLL_DIV(1)>; 754 clock-names = "ipg"; 755 dmas = <&edma0 1 28>, 756 <&edma0 1 29>; 757 dma-names = "rx", "tx"; 758 status = "disabled"; 759 }; 760 761 lpuart3: serial@2980000 { 762 compatible = "fsl,ls1021a-lpuart"; 763 reg = <0x0 0x2980000 0x0 0x1000>; 764 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 766 QORIQ_CLK_PLL_DIV(1)>; 767 clock-names = "ipg"; 768 dmas = <&edma0 1 26>, 769 <&edma0 1 27>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 lpuart4: serial@2990000 { 775 compatible = "fsl,ls1021a-lpuart"; 776 reg = <0x0 0x2990000 0x0 0x1000>; 777 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 779 QORIQ_CLK_PLL_DIV(1)>; 780 clock-names = "ipg"; 781 dmas = <&edma0 1 24>, 782 <&edma0 1 25>; 783 dma-names = "rx", "tx"; 784 status = "disabled"; 785 }; 786 787 lpuart5: serial@29a0000 { 788 compatible = "fsl,ls1021a-lpuart"; 789 reg = <0x0 0x29a0000 0x0 0x1000>; 790 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 792 QORIQ_CLK_PLL_DIV(1)>; 793 clock-names = "ipg"; 794 dmas = <&edma0 1 22>, 795 <&edma0 1 23>; 796 dma-names = "rx", "tx"; 797 status = "disabled"; 798 }; 799 800 wdog0: watchdog@2ad0000 { 801 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 802 reg = <0x0 0x2ad0000 0x0 0x10000>; 803 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 805 QORIQ_CLK_PLL_DIV(1)>; 806 big-endian; 807 }; 808 809 edma0: dma-controller@2c00000 { 810 #dma-cells = <2>; 811 compatible = "fsl,vf610-edma"; 812 reg = <0x0 0x2c00000 0x0 0x10000>, 813 <0x0 0x2c10000 0x0 0x10000>, 814 <0x0 0x2c20000 0x0 0x10000>; 815 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "edma-tx", "edma-err"; 818 dma-channels = <32>; 819 big-endian; 820 clock-names = "dmamux0", "dmamux1"; 821 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 822 QORIQ_CLK_PLL_DIV(1)>, 823 <&clockgen QORIQ_CLK_PLATFORM_PLL 824 QORIQ_CLK_PLL_DIV(1)>; 825 }; 826 827 aux_bus: bus { 828 #address-cells = <2>; 829 #size-cells = <2>; 830 compatible = "simple-bus"; 831 ranges; 832 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 833 834 usb0: usb@2f00000 { 835 compatible = "snps,dwc3"; 836 reg = <0x0 0x2f00000 0x0 0x10000>; 837 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 838 dr_mode = "host"; 839 snps,quirk-frame-length-adjustment = <0x20>; 840 snps,dis_rxdet_inp3_quirk; 841 usb3-lpm-capable; 842 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 843 status = "disabled"; 844 }; 845 846 usb1: usb@3000000 { 847 compatible = "snps,dwc3"; 848 reg = <0x0 0x3000000 0x0 0x10000>; 849 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 850 dr_mode = "host"; 851 snps,quirk-frame-length-adjustment = <0x20>; 852 snps,dis_rxdet_inp3_quirk; 853 usb3-lpm-capable; 854 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 855 status = "disabled"; 856 }; 857 858 usb2: usb@3100000 { 859 compatible = "snps,dwc3"; 860 reg = <0x0 0x3100000 0x0 0x10000>; 861 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 862 dr_mode = "host"; 863 snps,quirk-frame-length-adjustment = <0x20>; 864 snps,dis_rxdet_inp3_quirk; 865 usb3-lpm-capable; 866 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 867 status = "disabled"; 868 }; 869 870 sata: sata@3200000 { 871 compatible = "fsl,ls1043a-ahci"; 872 reg = <0x0 0x3200000 0x0 0x10000>, 873 <0x0 0x20140520 0x0 0x4>; 874 reg-names = "ahci", "sata-ecc"; 875 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 877 QORIQ_CLK_PLL_DIV(1)>; 878 dma-coherent; 879 }; 880 }; 881 882 msi1: msi-controller1@1571000 { 883 compatible = "fsl,ls1043a-msi"; 884 reg = <0x0 0x1571000 0x0 0x8>; 885 msi-controller; 886 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 887 }; 888 889 msi2: msi-controller2@1572000 { 890 compatible = "fsl,ls1043a-msi"; 891 reg = <0x0 0x1572000 0x0 0x8>; 892 msi-controller; 893 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 894 }; 895 896 msi3: msi-controller3@1573000 { 897 compatible = "fsl,ls1043a-msi"; 898 reg = <0x0 0x1573000 0x0 0x8>; 899 msi-controller; 900 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 901 }; 902 903 pcie1: pcie@3400000 { 904 compatible = "fsl,ls1043a-pcie"; 905 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 906 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 907 reg-names = "regs", "config"; 908 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 910 interrupt-names = "pme", "aer"; 911 #address-cells = <3>; 912 #size-cells = <2>; 913 device_type = "pci"; 914 num-viewport = <6>; 915 bus-range = <0x0 0xff>; 916 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 917 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 918 msi-parent = <&msi1>, <&msi2>, <&msi3>; 919 #interrupt-cells = <1>; 920 interrupt-map-mask = <0 0 0 7>; 921 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, 922 <0000 0 0 2 &gic 0 111 0x4>, 923 <0000 0 0 3 &gic 0 112 0x4>, 924 <0000 0 0 4 &gic 0 113 0x4>; 925 fsl,pcie-scfg = <&scfg 0>; 926 big-endian; 927 status = "disabled"; 928 }; 929 930 pcie2: pcie@3500000 { 931 compatible = "fsl,ls1043a-pcie"; 932 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 933 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 934 reg-names = "regs", "config"; 935 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "pme", "aer"; 938 #address-cells = <3>; 939 #size-cells = <2>; 940 device_type = "pci"; 941 num-viewport = <6>; 942 bus-range = <0x0 0xff>; 943 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 944 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 945 msi-parent = <&msi1>, <&msi2>, <&msi3>; 946 #interrupt-cells = <1>; 947 interrupt-map-mask = <0 0 0 7>; 948 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, 949 <0000 0 0 2 &gic 0 121 0x4>, 950 <0000 0 0 3 &gic 0 122 0x4>, 951 <0000 0 0 4 &gic 0 123 0x4>; 952 fsl,pcie-scfg = <&scfg 1>; 953 big-endian; 954 status = "disabled"; 955 }; 956 957 pcie3: pcie@3600000 { 958 compatible = "fsl,ls1043a-pcie"; 959 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 960 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 961 reg-names = "regs", "config"; 962 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 964 interrupt-names = "pme", "aer"; 965 #address-cells = <3>; 966 #size-cells = <2>; 967 device_type = "pci"; 968 num-viewport = <6>; 969 bus-range = <0x0 0xff>; 970 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 971 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 972 msi-parent = <&msi1>, <&msi2>, <&msi3>; 973 #interrupt-cells = <1>; 974 interrupt-map-mask = <0 0 0 7>; 975 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, 976 <0000 0 0 2 &gic 0 155 0x4>, 977 <0000 0 0 3 &gic 0 156 0x4>, 978 <0000 0 0 4 &gic 0 157 0x4>; 979 fsl,pcie-scfg = <&scfg 2>; 980 big-endian; 981 status = "disabled"; 982 }; 983 984 qdma: dma-controller@8380000 { 985 compatible = "fsl,ls1043a-qdma", "fsl,ls1021a-qdma"; 986 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 987 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 988 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 989 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 994 interrupt-names = "qdma-error", "qdma-queue0", 995 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 996 #dma-cells = <1>; 997 dma-channels = <8>; 998 block-number = <1>; 999 block-offset = <0x10000>; 1000 fsl,dma-queues = <2>; 1001 status-sizes = <64>; 1002 queue-sizes = <64 64>; 1003 big-endian; 1004 }; 1005 1006 rcpm: wakeup-controller@1ee2140 { 1007 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1008 reg = <0x0 0x1ee2140 0x0 0x4>; 1009 #fsl,rcpm-wakeup-cells = <1>; 1010 }; 1011 1012 ftm_alarm0: rtc@29d0000 { 1013 compatible = "fsl,ls1043a-ftm-alarm"; 1014 reg = <0x0 0x29d0000 0x0 0x10000>; 1015 fsl,rcpm-wakeup = <&rcpm 0x20000>; 1016 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1017 big-endian; 1018 }; 1019 }; 1020 1021 firmware { 1022 optee { 1023 compatible = "linaro,optee-tz"; 1024 method = "smc"; 1025 }; 1026 }; 1027 1028}; 1029 1030#include "qoriq-qman-portals.dtsi" 1031#include "qoriq-bman-portals.dtsi" 1032