1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 rtc1 = &ftm_alarm0; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a72"; 32 reg = <0x0>; 33 enable-method = "psci"; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 next-level-cache = <&l2>; 36 cpu-idle-states = <&CPU_PW20>; 37 #cooling-cells = <2>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a72"; 43 reg = <0x1>; 44 enable-method = "psci"; 45 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 46 next-level-cache = <&l2>; 47 cpu-idle-states = <&CPU_PW20>; 48 #cooling-cells = <2>; 49 }; 50 51 l2: l2-cache { 52 compatible = "cache"; 53 }; 54 }; 55 56 idle-states { 57 /* 58 * PSCI node is not added default, U-boot will add missing 59 * parts if it determines to use PSCI. 60 */ 61 entry-method = "psci"; 62 63 CPU_PW20: cpu-pw20 { 64 compatible = "arm,idle-state"; 65 idle-state-name = "PW20"; 66 arm,psci-suspend-param = <0x0>; 67 entry-latency-us = <2000>; 68 exit-latency-us = <2000>; 69 min-residency-us = <6000>; 70 }; 71 }; 72 73 sysclk: clock-sysclk { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <100000000>; 77 clock-output-names = "sysclk"; 78 }; 79 80 osc_27m: clock-osc-27m { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <27000000>; 84 clock-output-names = "phy_27m"; 85 }; 86 87 dpclk: clock-controller@f1f0000 { 88 compatible = "fsl,ls1028a-plldig"; 89 reg = <0x0 0xf1f0000 0x0 0xffff>; 90 #clock-cells = <0>; 91 clocks = <&osc_27m>; 92 }; 93 94 firmware { 95 optee { 96 compatible = "linaro,optee-tz"; 97 method = "smc"; 98 status = "disabled"; 99 }; 100 }; 101 102 reboot { 103 compatible ="syscon-reboot"; 104 regmap = <&rst>; 105 offset = <0>; 106 mask = <0x02>; 107 }; 108 109 timer { 110 compatible = "arm,armv8-timer"; 111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 112 IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 114 IRQ_TYPE_LEVEL_LOW)>, 115 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 116 IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 118 IRQ_TYPE_LEVEL_LOW)>; 119 }; 120 121 pmu { 122 compatible = "arm,cortex-a72-pmu"; 123 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 124 }; 125 126 gic: interrupt-controller@6000000 { 127 compatible= "arm,gic-v3"; 128 #address-cells = <2>; 129 #size-cells = <2>; 130 ranges; 131 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 132 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 133 #interrupt-cells= <3>; 134 interrupt-controller; 135 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 136 IRQ_TYPE_LEVEL_LOW)>; 137 its: gic-its@6020000 { 138 compatible = "arm,gic-v3-its"; 139 msi-controller; 140 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 141 }; 142 }; 143 144 thermal-zones { 145 ddr-controller { 146 polling-delay-passive = <1000>; 147 polling-delay = <5000>; 148 thermal-sensors = <&tmu 0>; 149 150 trips { 151 ddr-ctrler-alert { 152 temperature = <85000>; 153 hysteresis = <2000>; 154 type = "passive"; 155 }; 156 157 ddr-ctrler-crit { 158 temperature = <95000>; 159 hysteresis = <2000>; 160 type = "critical"; 161 }; 162 }; 163 }; 164 165 core-cluster { 166 polling-delay-passive = <1000>; 167 polling-delay = <5000>; 168 thermal-sensors = <&tmu 1>; 169 170 trips { 171 core_cluster_alert: core-cluster-alert { 172 temperature = <85000>; 173 hysteresis = <2000>; 174 type = "passive"; 175 }; 176 177 core_cluster_crit: core-cluster-crit { 178 temperature = <95000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 184 cooling-maps { 185 map0 { 186 trip = <&core_cluster_alert>; 187 cooling-device = 188 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 189 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 190 }; 191 }; 192 }; 193 }; 194 195 soc: soc { 196 compatible = "simple-bus"; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 ddr: memory-controller@1080000 { 202 compatible = "fsl,qoriq-memory-controller"; 203 reg = <0x0 0x1080000 0x0 0x1000>; 204 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 205 big-endian; 206 }; 207 208 dcfg: syscon@1e00000 { 209 #address-cells = <1>; 210 #size-cells = <1>; 211 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 212 reg = <0x0 0x1e00000 0x0 0x10000>; 213 ranges = <0x0 0x0 0x1e00000 0x10000>; 214 little-endian; 215 216 fspi_clk: clock-controller@900 { 217 compatible = "fsl,ls1028a-flexspi-clk"; 218 reg = <0x900 0x4>; 219 #clock-cells = <0>; 220 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 221 clock-output-names = "fspi_clk"; 222 }; 223 }; 224 225 rst: syscon@1e60000 { 226 compatible = "syscon"; 227 reg = <0x0 0x1e60000 0x0 0x10000>; 228 little-endian; 229 }; 230 231 scfg: syscon@1fc0000 { 232 compatible = "fsl,ls1028a-scfg", "syscon"; 233 reg = <0x0 0x1fc0000 0x0 0x10000>; 234 big-endian; 235 }; 236 237 clockgen: clock-controller@1300000 { 238 compatible = "fsl,ls1028a-clockgen"; 239 reg = <0x0 0x1300000 0x0 0xa0000>; 240 #clock-cells = <2>; 241 clocks = <&sysclk>; 242 }; 243 244 i2c0: i2c@2000000 { 245 compatible = "fsl,vf610-i2c"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <0x0 0x2000000 0x0 0x10000>; 249 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 251 QORIQ_CLK_PLL_DIV(4)>; 252 status = "disabled"; 253 }; 254 255 i2c1: i2c@2010000 { 256 compatible = "fsl,vf610-i2c"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 reg = <0x0 0x2010000 0x0 0x10000>; 260 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 262 QORIQ_CLK_PLL_DIV(4)>; 263 status = "disabled"; 264 }; 265 266 i2c2: i2c@2020000 { 267 compatible = "fsl,vf610-i2c"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 reg = <0x0 0x2020000 0x0 0x10000>; 271 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 273 QORIQ_CLK_PLL_DIV(4)>; 274 status = "disabled"; 275 }; 276 277 i2c3: i2c@2030000 { 278 compatible = "fsl,vf610-i2c"; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 reg = <0x0 0x2030000 0x0 0x10000>; 282 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 284 QORIQ_CLK_PLL_DIV(4)>; 285 status = "disabled"; 286 }; 287 288 i2c4: i2c@2040000 { 289 compatible = "fsl,vf610-i2c"; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <0x0 0x2040000 0x0 0x10000>; 293 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 295 QORIQ_CLK_PLL_DIV(4)>; 296 status = "disabled"; 297 }; 298 299 i2c5: i2c@2050000 { 300 compatible = "fsl,vf610-i2c"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg = <0x0 0x2050000 0x0 0x10000>; 304 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 306 QORIQ_CLK_PLL_DIV(4)>; 307 status = "disabled"; 308 }; 309 310 i2c6: i2c@2060000 { 311 compatible = "fsl,vf610-i2c"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x0 0x2060000 0x0 0x10000>; 315 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 317 QORIQ_CLK_PLL_DIV(4)>; 318 status = "disabled"; 319 }; 320 321 i2c7: i2c@2070000 { 322 compatible = "fsl,vf610-i2c"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 reg = <0x0 0x2070000 0x0 0x10000>; 326 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 328 QORIQ_CLK_PLL_DIV(4)>; 329 status = "disabled"; 330 }; 331 332 fspi: spi@20c0000 { 333 compatible = "nxp,lx2160a-fspi"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0x0 0x20c0000 0x0 0x10000>, 337 <0x0 0x20000000 0x0 0x10000000>; 338 reg-names = "fspi_base", "fspi_mmap"; 339 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&fspi_clk>, <&fspi_clk>; 341 clock-names = "fspi_en", "fspi"; 342 status = "disabled"; 343 }; 344 345 dspi0: spi@2100000 { 346 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 reg = <0x0 0x2100000 0x0 0x10000>; 350 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 351 clock-names = "dspi"; 352 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 353 QORIQ_CLK_PLL_DIV(2)>; 354 dmas = <&edma0 0 62>, <&edma0 0 60>; 355 dma-names = "tx", "rx"; 356 spi-num-chipselects = <4>; 357 little-endian; 358 status = "disabled"; 359 }; 360 361 dspi1: spi@2110000 { 362 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <0x0 0x2110000 0x0 0x10000>; 366 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 367 clock-names = "dspi"; 368 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 369 QORIQ_CLK_PLL_DIV(2)>; 370 dmas = <&edma0 0 58>, <&edma0 0 56>; 371 dma-names = "tx", "rx"; 372 spi-num-chipselects = <4>; 373 little-endian; 374 status = "disabled"; 375 }; 376 377 dspi2: spi@2120000 { 378 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 reg = <0x0 0x2120000 0x0 0x10000>; 382 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 383 clock-names = "dspi"; 384 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 385 QORIQ_CLK_PLL_DIV(2)>; 386 dmas = <&edma0 0 54>, <&edma0 0 2>; 387 dma-names = "tx", "rx"; 388 spi-num-chipselects = <3>; 389 little-endian; 390 status = "disabled"; 391 }; 392 393 esdhc: mmc@2140000 { 394 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 395 reg = <0x0 0x2140000 0x0 0x10000>; 396 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 397 clock-frequency = <0>; /* fixed up by bootloader */ 398 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 399 voltage-ranges = <1800 1800 3300 3300>; 400 sdhci,auto-cmd12; 401 little-endian; 402 bus-width = <4>; 403 status = "disabled"; 404 }; 405 406 esdhc1: mmc@2150000 { 407 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 408 reg = <0x0 0x2150000 0x0 0x10000>; 409 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 410 clock-frequency = <0>; /* fixed up by bootloader */ 411 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 412 voltage-ranges = <1800 1800 3300 3300>; 413 sdhci,auto-cmd12; 414 broken-cd; 415 little-endian; 416 bus-width = <4>; 417 status = "disabled"; 418 }; 419 420 can0: can@2180000 { 421 compatible = "fsl,lx2160ar1-flexcan"; 422 reg = <0x0 0x2180000 0x0 0x10000>; 423 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 425 QORIQ_CLK_PLL_DIV(2)>, 426 <&clockgen QORIQ_CLK_PLATFORM_PLL 427 QORIQ_CLK_PLL_DIV(2)>; 428 clock-names = "ipg", "per"; 429 status = "disabled"; 430 }; 431 432 can1: can@2190000 { 433 compatible = "fsl,lx2160ar1-flexcan"; 434 reg = <0x0 0x2190000 0x0 0x10000>; 435 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 437 QORIQ_CLK_PLL_DIV(2)>, 438 <&clockgen QORIQ_CLK_PLATFORM_PLL 439 QORIQ_CLK_PLL_DIV(2)>; 440 clock-names = "ipg", "per"; 441 status = "disabled"; 442 }; 443 444 duart0: serial@21c0500 { 445 compatible = "fsl,ns16550", "ns16550a"; 446 reg = <0x00 0x21c0500 0x0 0x100>; 447 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 449 QORIQ_CLK_PLL_DIV(2)>; 450 status = "disabled"; 451 }; 452 453 duart1: serial@21c0600 { 454 compatible = "fsl,ns16550", "ns16550a"; 455 reg = <0x00 0x21c0600 0x0 0x100>; 456 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 458 QORIQ_CLK_PLL_DIV(2)>; 459 status = "disabled"; 460 }; 461 462 463 lpuart0: serial@2260000 { 464 compatible = "fsl,ls1028a-lpuart"; 465 reg = <0x0 0x2260000 0x0 0x1000>; 466 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 468 QORIQ_CLK_PLL_DIV(2)>; 469 clock-names = "ipg"; 470 dma-names = "rx","tx"; 471 dmas = <&edma0 1 32>, 472 <&edma0 1 33>; 473 status = "disabled"; 474 }; 475 476 lpuart1: serial@2270000 { 477 compatible = "fsl,ls1028a-lpuart"; 478 reg = <0x0 0x2270000 0x0 0x1000>; 479 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 481 QORIQ_CLK_PLL_DIV(2)>; 482 clock-names = "ipg"; 483 dma-names = "rx","tx"; 484 dmas = <&edma0 1 30>, 485 <&edma0 1 31>; 486 status = "disabled"; 487 }; 488 489 lpuart2: serial@2280000 { 490 compatible = "fsl,ls1028a-lpuart"; 491 reg = <0x0 0x2280000 0x0 0x1000>; 492 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 494 QORIQ_CLK_PLL_DIV(2)>; 495 clock-names = "ipg"; 496 dma-names = "rx","tx"; 497 dmas = <&edma0 1 28>, 498 <&edma0 1 29>; 499 status = "disabled"; 500 }; 501 502 lpuart3: serial@2290000 { 503 compatible = "fsl,ls1028a-lpuart"; 504 reg = <0x0 0x2290000 0x0 0x1000>; 505 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 507 QORIQ_CLK_PLL_DIV(2)>; 508 clock-names = "ipg"; 509 dma-names = "rx","tx"; 510 dmas = <&edma0 1 26>, 511 <&edma0 1 27>; 512 status = "disabled"; 513 }; 514 515 lpuart4: serial@22a0000 { 516 compatible = "fsl,ls1028a-lpuart"; 517 reg = <0x0 0x22a0000 0x0 0x1000>; 518 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 520 QORIQ_CLK_PLL_DIV(2)>; 521 clock-names = "ipg"; 522 dma-names = "rx","tx"; 523 dmas = <&edma0 1 24>, 524 <&edma0 1 25>; 525 status = "disabled"; 526 }; 527 528 lpuart5: serial@22b0000 { 529 compatible = "fsl,ls1028a-lpuart"; 530 reg = <0x0 0x22b0000 0x0 0x1000>; 531 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 533 QORIQ_CLK_PLL_DIV(2)>; 534 clock-names = "ipg"; 535 dma-names = "rx","tx"; 536 dmas = <&edma0 1 22>, 537 <&edma0 1 23>; 538 status = "disabled"; 539 }; 540 541 edma0: dma-controller@22c0000 { 542 #dma-cells = <2>; 543 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 544 reg = <0x0 0x22c0000 0x0 0x10000>, 545 <0x0 0x22d0000 0x0 0x10000>, 546 <0x0 0x22e0000 0x0 0x10000>; 547 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "edma-tx", "edma-err"; 550 dma-channels = <32>; 551 clock-names = "dmamux0", "dmamux1"; 552 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 553 QORIQ_CLK_PLL_DIV(2)>, 554 <&clockgen QORIQ_CLK_PLATFORM_PLL 555 QORIQ_CLK_PLL_DIV(2)>; 556 }; 557 558 gpio1: gpio@2300000 { 559 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 560 reg = <0x0 0x2300000 0x0 0x10000>; 561 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 little-endian; 567 }; 568 569 gpio2: gpio@2310000 { 570 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 571 reg = <0x0 0x2310000 0x0 0x10000>; 572 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 573 gpio-controller; 574 #gpio-cells = <2>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 little-endian; 578 }; 579 580 gpio3: gpio@2320000 { 581 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 582 reg = <0x0 0x2320000 0x0 0x10000>; 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 584 gpio-controller; 585 #gpio-cells = <2>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 little-endian; 589 }; 590 591 usb0: usb@3100000 { 592 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 593 reg = <0x0 0x3100000 0x0 0x10000>; 594 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 595 dr_mode = "host"; 596 snps,dis_rxdet_inp3_quirk; 597 snps,quirk-frame-length-adjustment = <0x20>; 598 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 599 }; 600 601 usb1: usb@3110000 { 602 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 603 reg = <0x0 0x3110000 0x0 0x10000>; 604 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 605 dr_mode = "host"; 606 snps,dis_rxdet_inp3_quirk; 607 snps,quirk-frame-length-adjustment = <0x20>; 608 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 609 }; 610 611 sata: sata@3200000 { 612 compatible = "fsl,ls1028a-ahci"; 613 reg = <0x0 0x3200000 0x0 0x10000>, 614 <0x7 0x100520 0x0 0x4>; 615 reg-names = "ahci", "sata-ecc"; 616 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 618 QORIQ_CLK_PLL_DIV(2)>; 619 status = "disabled"; 620 }; 621 622 pcie1: pcie@3400000 { 623 compatible = "fsl,ls1028a-pcie"; 624 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 625 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 626 reg-names = "regs", "config"; 627 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 628 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 629 interrupt-names = "pme", "aer"; 630 #address-cells = <3>; 631 #size-cells = <2>; 632 device_type = "pci"; 633 dma-coherent; 634 num-viewport = <8>; 635 bus-range = <0x0 0xff>; 636 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 637 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 638 msi-parent = <&its>; 639 #interrupt-cells = <1>; 640 interrupt-map-mask = <0 0 0 7>; 641 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 642 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 643 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 644 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 645 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 646 status = "disabled"; 647 }; 648 649 pcie2: pcie@3500000 { 650 compatible = "fsl,ls1028a-pcie"; 651 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 652 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 653 reg-names = "regs", "config"; 654 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 656 interrupt-names = "pme", "aer"; 657 #address-cells = <3>; 658 #size-cells = <2>; 659 device_type = "pci"; 660 dma-coherent; 661 num-viewport = <8>; 662 bus-range = <0x0 0xff>; 663 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 664 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 665 msi-parent = <&its>; 666 #interrupt-cells = <1>; 667 interrupt-map-mask = <0 0 0 7>; 668 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 669 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 670 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 671 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 672 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 673 status = "disabled"; 674 }; 675 676 smmu: iommu@5000000 { 677 compatible = "arm,mmu-500"; 678 reg = <0 0x5000000 0 0x800000>; 679 #global-interrupts = <8>; 680 #iommu-cells = <1>; 681 stream-match-mask = <0x7c00>; 682 /* global secure fault */ 683 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 684 /* combined secure interrupt */ 685 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 686 /* global non-secure fault */ 687 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 688 /* combined non-secure interrupt */ 689 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 690 /* performance counter interrupts 0-7 */ 691 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 693 /* per context interrupt, 64 interrupts */ 694 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 726 }; 727 728 crypto: crypto@8000000 { 729 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 730 fsl,sec-era = <10>; 731 #address-cells = <1>; 732 #size-cells = <1>; 733 ranges = <0x0 0x00 0x8000000 0x100000>; 734 reg = <0x00 0x8000000 0x0 0x100000>; 735 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 736 dma-coherent; 737 738 sec_jr0: jr@10000 { 739 compatible = "fsl,sec-v5.0-job-ring", 740 "fsl,sec-v4.0-job-ring"; 741 reg = <0x10000 0x10000>; 742 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 743 }; 744 745 sec_jr1: jr@20000 { 746 compatible = "fsl,sec-v5.0-job-ring", 747 "fsl,sec-v4.0-job-ring"; 748 reg = <0x20000 0x10000>; 749 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 750 }; 751 752 sec_jr2: jr@30000 { 753 compatible = "fsl,sec-v5.0-job-ring", 754 "fsl,sec-v4.0-job-ring"; 755 reg = <0x30000 0x10000>; 756 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 757 }; 758 759 sec_jr3: jr@40000 { 760 compatible = "fsl,sec-v5.0-job-ring", 761 "fsl,sec-v4.0-job-ring"; 762 reg = <0x40000 0x10000>; 763 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 764 }; 765 }; 766 767 qdma: dma-controller@8380000 { 768 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 769 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 770 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 771 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 772 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "qdma-error", "qdma-queue0", 778 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 779 dma-channels = <8>; 780 block-number = <1>; 781 block-offset = <0x10000>; 782 fsl,dma-queues = <2>; 783 status-sizes = <64>; 784 queue-sizes = <64 64>; 785 }; 786 787 cluster1_core0_watchdog: watchdog@c000000 { 788 compatible = "arm,sp805", "arm,primecell"; 789 reg = <0x0 0xc000000 0x0 0x1000>; 790 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 791 QORIQ_CLK_PLL_DIV(16)>, 792 <&clockgen QORIQ_CLK_PLATFORM_PLL 793 QORIQ_CLK_PLL_DIV(16)>; 794 clock-names = "wdog_clk", "apb_pclk"; 795 }; 796 797 cluster1_core1_watchdog: watchdog@c010000 { 798 compatible = "arm,sp805", "arm,primecell"; 799 reg = <0x0 0xc010000 0x0 0x1000>; 800 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 801 QORIQ_CLK_PLL_DIV(16)>, 802 <&clockgen QORIQ_CLK_PLATFORM_PLL 803 QORIQ_CLK_PLL_DIV(16)>; 804 clock-names = "wdog_clk", "apb_pclk"; 805 }; 806 807 sai1: audio-controller@f100000 { 808 #sound-dai-cells = <0>; 809 compatible = "fsl,vf610-sai"; 810 reg = <0x0 0xf100000 0x0 0x10000>; 811 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 813 QORIQ_CLK_PLL_DIV(2)>, 814 <&clockgen QORIQ_CLK_PLATFORM_PLL 815 QORIQ_CLK_PLL_DIV(2)>, 816 <&clockgen QORIQ_CLK_PLATFORM_PLL 817 QORIQ_CLK_PLL_DIV(2)>, 818 <&clockgen QORIQ_CLK_PLATFORM_PLL 819 QORIQ_CLK_PLL_DIV(2)>; 820 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 821 dma-names = "tx", "rx"; 822 dmas = <&edma0 1 4>, 823 <&edma0 1 3>; 824 fsl,sai-asynchronous; 825 status = "disabled"; 826 }; 827 828 sai2: audio-controller@f110000 { 829 #sound-dai-cells = <0>; 830 compatible = "fsl,vf610-sai"; 831 reg = <0x0 0xf110000 0x0 0x10000>; 832 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 834 QORIQ_CLK_PLL_DIV(2)>, 835 <&clockgen QORIQ_CLK_PLATFORM_PLL 836 QORIQ_CLK_PLL_DIV(2)>, 837 <&clockgen QORIQ_CLK_PLATFORM_PLL 838 QORIQ_CLK_PLL_DIV(2)>, 839 <&clockgen QORIQ_CLK_PLATFORM_PLL 840 QORIQ_CLK_PLL_DIV(2)>; 841 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 842 dma-names = "tx", "rx"; 843 dmas = <&edma0 1 6>, 844 <&edma0 1 5>; 845 fsl,sai-asynchronous; 846 status = "disabled"; 847 }; 848 849 sai3: audio-controller@f120000 { 850 #sound-dai-cells = <0>; 851 compatible = "fsl,vf610-sai"; 852 reg = <0x0 0xf120000 0x0 0x10000>; 853 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 855 QORIQ_CLK_PLL_DIV(2)>, 856 <&clockgen QORIQ_CLK_PLATFORM_PLL 857 QORIQ_CLK_PLL_DIV(2)>, 858 <&clockgen QORIQ_CLK_PLATFORM_PLL 859 QORIQ_CLK_PLL_DIV(2)>, 860 <&clockgen QORIQ_CLK_PLATFORM_PLL 861 QORIQ_CLK_PLL_DIV(2)>; 862 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 863 dma-names = "tx", "rx"; 864 dmas = <&edma0 1 8>, 865 <&edma0 1 7>; 866 fsl,sai-asynchronous; 867 status = "disabled"; 868 }; 869 870 sai4: audio-controller@f130000 { 871 #sound-dai-cells = <0>; 872 compatible = "fsl,vf610-sai"; 873 reg = <0x0 0xf130000 0x0 0x10000>; 874 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 876 QORIQ_CLK_PLL_DIV(2)>, 877 <&clockgen QORIQ_CLK_PLATFORM_PLL 878 QORIQ_CLK_PLL_DIV(2)>, 879 <&clockgen QORIQ_CLK_PLATFORM_PLL 880 QORIQ_CLK_PLL_DIV(2)>, 881 <&clockgen QORIQ_CLK_PLATFORM_PLL 882 QORIQ_CLK_PLL_DIV(2)>; 883 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 884 dma-names = "tx", "rx"; 885 dmas = <&edma0 1 10>, 886 <&edma0 1 9>; 887 fsl,sai-asynchronous; 888 status = "disabled"; 889 }; 890 891 sai5: audio-controller@f140000 { 892 #sound-dai-cells = <0>; 893 compatible = "fsl,vf610-sai"; 894 reg = <0x0 0xf140000 0x0 0x10000>; 895 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 897 QORIQ_CLK_PLL_DIV(2)>, 898 <&clockgen QORIQ_CLK_PLATFORM_PLL 899 QORIQ_CLK_PLL_DIV(2)>, 900 <&clockgen QORIQ_CLK_PLATFORM_PLL 901 QORIQ_CLK_PLL_DIV(2)>, 902 <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(2)>; 904 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 905 dma-names = "tx", "rx"; 906 dmas = <&edma0 1 12>, 907 <&edma0 1 11>; 908 fsl,sai-asynchronous; 909 status = "disabled"; 910 }; 911 912 sai6: audio-controller@f150000 { 913 #sound-dai-cells = <0>; 914 compatible = "fsl,vf610-sai"; 915 reg = <0x0 0xf150000 0x0 0x10000>; 916 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 918 QORIQ_CLK_PLL_DIV(2)>, 919 <&clockgen QORIQ_CLK_PLATFORM_PLL 920 QORIQ_CLK_PLL_DIV(2)>, 921 <&clockgen QORIQ_CLK_PLATFORM_PLL 922 QORIQ_CLK_PLL_DIV(2)>, 923 <&clockgen QORIQ_CLK_PLATFORM_PLL 924 QORIQ_CLK_PLL_DIV(2)>; 925 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 926 dma-names = "tx", "rx"; 927 dmas = <&edma0 1 14>, 928 <&edma0 1 13>; 929 fsl,sai-asynchronous; 930 status = "disabled"; 931 }; 932 933 tmu: tmu@1f80000 { 934 compatible = "fsl,qoriq-tmu"; 935 reg = <0x0 0x1f80000 0x0 0x10000>; 936 interrupts = <0 23 0x4>; 937 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 938 fsl,tmu-calibration = <0x00000000 0x00000024 939 0x00000001 0x0000002b 940 0x00000002 0x00000031 941 0x00000003 0x00000038 942 0x00000004 0x0000003f 943 0x00000005 0x00000045 944 0x00000006 0x0000004c 945 0x00000007 0x00000053 946 0x00000008 0x00000059 947 0x00000009 0x00000060 948 0x0000000a 0x00000066 949 0x0000000b 0x0000006d 950 951 0x00010000 0x0000001c 952 0x00010001 0x00000024 953 0x00010002 0x0000002c 954 0x00010003 0x00000035 955 0x00010004 0x0000003d 956 0x00010005 0x00000045 957 0x00010006 0x0000004d 958 0x00010007 0x00000055 959 0x00010008 0x0000005e 960 0x00010009 0x00000066 961 0x0001000a 0x0000006e 962 963 0x00020000 0x00000018 964 0x00020001 0x00000022 965 0x00020002 0x0000002d 966 0x00020003 0x00000038 967 0x00020004 0x00000043 968 0x00020005 0x0000004d 969 0x00020006 0x00000058 970 0x00020007 0x00000063 971 0x00020008 0x0000006e 972 973 0x00030000 0x00000010 974 0x00030001 0x0000001c 975 0x00030002 0x00000029 976 0x00030003 0x00000036 977 0x00030004 0x00000042 978 0x00030005 0x0000004f 979 0x00030006 0x0000005b 980 0x00030007 0x00000068>; 981 little-endian; 982 #thermal-sensor-cells = <1>; 983 }; 984 985 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 986 compatible = "pci-host-ecam-generic"; 987 reg = <0x01 0xf0000000 0x0 0x100000>; 988 #address-cells = <3>; 989 #size-cells = <2>; 990 msi-parent = <&its>; 991 device_type = "pci"; 992 bus-range = <0x0 0x0>; 993 dma-coherent; 994 msi-map = <0 &its 0x17 0xe>; 995 iommu-map = <0 &smmu 0x17 0xe>; 996 /* PF0-6 BAR0 - non-prefetchable memory */ 997 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 998 /* PF0-6 BAR2 - prefetchable memory */ 999 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 1000 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1001 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 1002 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1003 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 1004 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1005 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 1006 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1007 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 1008 /* BAR4 (PF5) - non-prefetchable memory */ 1009 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; 1010 1011 enetc_port0: ethernet@0,0 { 1012 compatible = "fsl,enetc"; 1013 reg = <0x000000 0 0 0 0>; 1014 status = "disabled"; 1015 }; 1016 1017 enetc_port1: ethernet@0,1 { 1018 compatible = "fsl,enetc"; 1019 reg = <0x000100 0 0 0 0>; 1020 status = "disabled"; 1021 }; 1022 1023 enetc_port2: ethernet@0,2 { 1024 compatible = "fsl,enetc"; 1025 reg = <0x000200 0 0 0 0>; 1026 phy-mode = "internal"; 1027 status = "disabled"; 1028 1029 fixed-link { 1030 speed = <1000>; 1031 full-duplex; 1032 }; 1033 }; 1034 1035 enetc_mdio_pf3: mdio@0,3 { 1036 compatible = "fsl,enetc-mdio"; 1037 reg = <0x000300 0 0 0 0>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 }; 1041 1042 ethernet@0,4 { 1043 compatible = "fsl,enetc-ptp"; 1044 reg = <0x000400 0 0 0 0>; 1045 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1046 little-endian; 1047 fsl,extts-fifo; 1048 }; 1049 1050 mscc_felix: ethernet-switch@0,5 { 1051 reg = <0x000500 0 0 0 0>; 1052 /* IEP INT_B */ 1053 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1054 status = "disabled"; 1055 1056 ports { 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 1060 /* External ports */ 1061 mscc_felix_port0: port@0 { 1062 reg = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 mscc_felix_port1: port@1 { 1067 reg = <1>; 1068 status = "disabled"; 1069 }; 1070 1071 mscc_felix_port2: port@2 { 1072 reg = <2>; 1073 status = "disabled"; 1074 }; 1075 1076 mscc_felix_port3: port@3 { 1077 reg = <3>; 1078 status = "disabled"; 1079 }; 1080 1081 /* Internal ports */ 1082 mscc_felix_port4: port@4 { 1083 reg = <4>; 1084 phy-mode = "internal"; 1085 status = "disabled"; 1086 1087 fixed-link { 1088 speed = <2500>; 1089 full-duplex; 1090 }; 1091 }; 1092 1093 mscc_felix_port5: port@5 { 1094 reg = <5>; 1095 phy-mode = "internal"; 1096 status = "disabled"; 1097 1098 fixed-link { 1099 speed = <1000>; 1100 full-duplex; 1101 }; 1102 }; 1103 }; 1104 }; 1105 1106 enetc_port3: ethernet@0,6 { 1107 compatible = "fsl,enetc"; 1108 reg = <0x000600 0 0 0 0>; 1109 phy-mode = "internal"; 1110 status = "disabled"; 1111 1112 fixed-link { 1113 speed = <1000>; 1114 full-duplex; 1115 }; 1116 }; 1117 }; 1118 1119 rcpm: power-controller@1e34040 { 1120 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1121 reg = <0x0 0x1e34040 0x0 0x1c>; 1122 #fsl,rcpm-wakeup-cells = <7>; 1123 little-endian; 1124 }; 1125 1126 ftm_alarm0: timer@2800000 { 1127 compatible = "fsl,ls1028a-ftm-alarm"; 1128 reg = <0x0 0x2800000 0x0 0x10000>; 1129 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1130 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1131 }; 1132 }; 1133 1134 malidp0: display@f080000 { 1135 compatible = "arm,mali-dp500"; 1136 reg = <0x0 0xf080000 0x0 0x10000>; 1137 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 1138 <0 223 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-names = "DE", "SE"; 1140 clocks = <&dpclk>, 1141 <&clockgen QORIQ_CLK_HWACCEL 2>, 1142 <&clockgen QORIQ_CLK_HWACCEL 2>, 1143 <&clockgen QORIQ_CLK_HWACCEL 2>; 1144 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 1145 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 1146 arm,malidp-arqos-value = <0xd000d000>; 1147 1148 port { 1149 dp0_out: endpoint { 1150 1151 }; 1152 }; 1153 }; 1154}; 1155