1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a72"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 clocks = <&clockgen 1 0>; 30 next-level-cache = <&l2>; 31 cpu-idle-states = <&CPU_PW20>; 32 #cooling-cells = <2>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a72"; 38 reg = <0x1>; 39 enable-method = "psci"; 40 clocks = <&clockgen 1 0>; 41 next-level-cache = <&l2>; 42 cpu-idle-states = <&CPU_PW20>; 43 #cooling-cells = <2>; 44 }; 45 46 l2: l2-cache { 47 compatible = "cache"; 48 }; 49 }; 50 51 idle-states { 52 /* 53 * PSCI node is not added default, U-boot will add missing 54 * parts if it determines to use PSCI. 55 */ 56 entry-method = "arm,psci"; 57 58 CPU_PW20: cpu-pw20 { 59 compatible = "arm,idle-state"; 60 idle-state-name = "PW20"; 61 arm,psci-suspend-param = <0x0>; 62 entry-latency-us = <2000>; 63 exit-latency-us = <2000>; 64 min-residency-us = <6000>; 65 }; 66 }; 67 68 sysclk: clock-sysclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "sysclk"; 73 }; 74 75 osc_27m: clock-osc-27m { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <27000000>; 79 clock-output-names = "phy_27m"; 80 }; 81 82 dpclk: clock-controller@f1f0000 { 83 compatible = "fsl,ls1028a-plldig"; 84 reg = <0x0 0xf1f0000 0x0 0xffff>; 85 #clock-cells = <0>; 86 clocks = <&osc_27m>; 87 }; 88 89 reboot { 90 compatible ="syscon-reboot"; 91 regmap = <&dcfg>; 92 offset = <0xb0>; 93 mask = <0x02>; 94 }; 95 96 timer { 97 compatible = "arm,armv8-timer"; 98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 99 IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 101 IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 103 IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 105 IRQ_TYPE_LEVEL_LOW)>; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a72-pmu"; 110 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 gic: interrupt-controller@6000000 { 114 compatible= "arm,gic-v3"; 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 119 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 120 #interrupt-cells= <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 123 IRQ_TYPE_LEVEL_LOW)>; 124 its: gic-its@6020000 { 125 compatible = "arm,gic-v3-its"; 126 msi-controller; 127 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 128 }; 129 }; 130 131 thermal-zones { 132 core-cluster { 133 polling-delay-passive = <1000>; 134 polling-delay = <5000>; 135 thermal-sensors = <&tmu 0>; 136 137 trips { 138 core_cluster_alert: core-cluster-alert { 139 temperature = <85000>; 140 hysteresis = <2000>; 141 type = "passive"; 142 }; 143 144 core_cluster_crit: core-cluster-crit { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "critical"; 148 }; 149 }; 150 151 cooling-maps { 152 map0 { 153 trip = <&core_cluster_alert>; 154 cooling-device = 155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 157 }; 158 }; 159 }; 160 }; 161 162 soc: soc { 163 compatible = "simple-bus"; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges; 167 168 ddr: memory-controller@1080000 { 169 compatible = "fsl,qoriq-memory-controller"; 170 reg = <0x0 0x1080000 0x0 0x1000>; 171 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 172 big-endian; 173 }; 174 175 dcfg: syscon@1e00000 { 176 compatible = "fsl,ls1028a-dcfg", "syscon"; 177 reg = <0x0 0x1e00000 0x0 0x10000>; 178 big-endian; 179 }; 180 181 scfg: syscon@1fc0000 { 182 compatible = "fsl,ls1028a-scfg", "syscon"; 183 reg = <0x0 0x1fc0000 0x0 0x10000>; 184 big-endian; 185 }; 186 187 clockgen: clock-controller@1300000 { 188 compatible = "fsl,ls1028a-clockgen"; 189 reg = <0x0 0x1300000 0x0 0xa0000>; 190 #clock-cells = <2>; 191 clocks = <&sysclk>; 192 }; 193 194 i2c0: i2c@2000000 { 195 compatible = "fsl,vf610-i2c"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 reg = <0x0 0x2000000 0x0 0x10000>; 199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&clockgen 4 3>; 201 status = "disabled"; 202 }; 203 204 i2c1: i2c@2010000 { 205 compatible = "fsl,vf610-i2c"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 reg = <0x0 0x2010000 0x0 0x10000>; 209 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&clockgen 4 3>; 211 status = "disabled"; 212 }; 213 214 i2c2: i2c@2020000 { 215 compatible = "fsl,vf610-i2c"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 reg = <0x0 0x2020000 0x0 0x10000>; 219 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&clockgen 4 3>; 221 status = "disabled"; 222 }; 223 224 i2c3: i2c@2030000 { 225 compatible = "fsl,vf610-i2c"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 reg = <0x0 0x2030000 0x0 0x10000>; 229 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&clockgen 4 3>; 231 status = "disabled"; 232 }; 233 234 i2c4: i2c@2040000 { 235 compatible = "fsl,vf610-i2c"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 reg = <0x0 0x2040000 0x0 0x10000>; 239 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clockgen 4 3>; 241 status = "disabled"; 242 }; 243 244 i2c5: i2c@2050000 { 245 compatible = "fsl,vf610-i2c"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <0x0 0x2050000 0x0 0x10000>; 249 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clockgen 4 3>; 251 status = "disabled"; 252 }; 253 254 i2c6: i2c@2060000 { 255 compatible = "fsl,vf610-i2c"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0x0 0x2060000 0x0 0x10000>; 259 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clockgen 4 3>; 261 status = "disabled"; 262 }; 263 264 i2c7: i2c@2070000 { 265 compatible = "fsl,vf610-i2c"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 reg = <0x0 0x2070000 0x0 0x10000>; 269 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clockgen 4 3>; 271 status = "disabled"; 272 }; 273 274 esdhc: mmc@2140000 { 275 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 276 reg = <0x0 0x2140000 0x0 0x10000>; 277 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 278 clock-frequency = <0>; /* fixed up by bootloader */ 279 clocks = <&clockgen 2 1>; 280 voltage-ranges = <1800 1800 3300 3300>; 281 sdhci,auto-cmd12; 282 little-endian; 283 bus-width = <4>; 284 status = "disabled"; 285 }; 286 287 esdhc1: mmc@2150000 { 288 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 289 reg = <0x0 0x2150000 0x0 0x10000>; 290 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 291 clock-frequency = <0>; /* fixed up by bootloader */ 292 clocks = <&clockgen 2 1>; 293 voltage-ranges = <1800 1800 3300 3300>; 294 sdhci,auto-cmd12; 295 broken-cd; 296 little-endian; 297 bus-width = <4>; 298 status = "disabled"; 299 }; 300 301 duart0: serial@21c0500 { 302 compatible = "fsl,ns16550", "ns16550a"; 303 reg = <0x00 0x21c0500 0x0 0x100>; 304 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clockgen 4 1>; 306 status = "disabled"; 307 }; 308 309 duart1: serial@21c0600 { 310 compatible = "fsl,ns16550", "ns16550a"; 311 reg = <0x00 0x21c0600 0x0 0x100>; 312 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&clockgen 4 1>; 314 status = "disabled"; 315 }; 316 317 edma0: dma-controller@22c0000 { 318 #dma-cells = <2>; 319 compatible = "fsl,vf610-edma"; 320 reg = <0x0 0x22c0000 0x0 0x10000>, 321 <0x0 0x22d0000 0x0 0x10000>, 322 <0x0 0x22e0000 0x0 0x10000>; 323 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 325 interrupt-names = "edma-tx", "edma-err"; 326 dma-channels = <32>; 327 clock-names = "dmamux0", "dmamux1"; 328 clocks = <&clockgen 4 1>, 329 <&clockgen 4 1>; 330 }; 331 332 gpio1: gpio@2300000 { 333 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 334 reg = <0x0 0x2300000 0x0 0x10000>; 335 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 little-endian; 341 }; 342 343 gpio2: gpio@2310000 { 344 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 345 reg = <0x0 0x2310000 0x0 0x10000>; 346 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 little-endian; 352 }; 353 354 gpio3: gpio@2320000 { 355 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 356 reg = <0x0 0x2320000 0x0 0x10000>; 357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 interrupt-controller; 361 #interrupt-cells = <2>; 362 little-endian; 363 }; 364 365 usb0: usb@3100000 { 366 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 367 reg = <0x0 0x3100000 0x0 0x10000>; 368 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 369 dr_mode = "host"; 370 snps,dis_rxdet_inp3_quirk; 371 snps,quirk-frame-length-adjustment = <0x20>; 372 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 373 }; 374 375 usb1: usb@3110000 { 376 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 377 reg = <0x0 0x3110000 0x0 0x10000>; 378 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 379 dr_mode = "host"; 380 snps,dis_rxdet_inp3_quirk; 381 snps,quirk-frame-length-adjustment = <0x20>; 382 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 383 }; 384 385 sata: sata@3200000 { 386 compatible = "fsl,ls1028a-ahci"; 387 reg = <0x0 0x3200000 0x0 0x10000>, 388 <0x7 0x100520 0x0 0x4>; 389 reg-names = "ahci", "sata-ecc"; 390 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&clockgen 4 1>; 392 status = "disabled"; 393 }; 394 395 smmu: iommu@5000000 { 396 compatible = "arm,mmu-500"; 397 reg = <0 0x5000000 0 0x800000>; 398 #global-interrupts = <8>; 399 #iommu-cells = <1>; 400 stream-match-mask = <0x7c00>; 401 /* global secure fault */ 402 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 403 /* combined secure interrupt */ 404 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 405 /* global non-secure fault */ 406 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 407 /* combined non-secure interrupt */ 408 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 409 /* performance counter interrupts 0-7 */ 410 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 412 /* per context interrupt, 64 interrupts */ 413 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 445 }; 446 447 crypto: crypto@8000000 { 448 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 449 fsl,sec-era = <10>; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 ranges = <0x0 0x00 0x8000000 0x100000>; 453 reg = <0x00 0x8000000 0x0 0x100000>; 454 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 455 dma-coherent; 456 457 sec_jr0: jr@10000 { 458 compatible = "fsl,sec-v5.0-job-ring", 459 "fsl,sec-v4.0-job-ring"; 460 reg = <0x10000 0x10000>; 461 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 462 }; 463 464 sec_jr1: jr@20000 { 465 compatible = "fsl,sec-v5.0-job-ring", 466 "fsl,sec-v4.0-job-ring"; 467 reg = <0x20000 0x10000>; 468 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 469 }; 470 471 sec_jr2: jr@30000 { 472 compatible = "fsl,sec-v5.0-job-ring", 473 "fsl,sec-v4.0-job-ring"; 474 reg = <0x30000 0x10000>; 475 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 476 }; 477 478 sec_jr3: jr@40000 { 479 compatible = "fsl,sec-v5.0-job-ring", 480 "fsl,sec-v4.0-job-ring"; 481 reg = <0x40000 0x10000>; 482 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 483 }; 484 }; 485 486 qdma: dma-controller@8380000 { 487 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 488 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 489 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 490 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 491 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "qdma-error", "qdma-queue0", 497 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 498 dma-channels = <8>; 499 block-number = <1>; 500 block-offset = <0x10000>; 501 fsl,dma-queues = <2>; 502 status-sizes = <64>; 503 queue-sizes = <64 64>; 504 }; 505 506 cluster1_core0_watchdog: watchdog@c000000 { 507 compatible = "arm,sp805", "arm,primecell"; 508 reg = <0x0 0xc000000 0x0 0x1000>; 509 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 510 clock-names = "apb_pclk", "wdog_clk"; 511 }; 512 513 cluster1_core1_watchdog: watchdog@c010000 { 514 compatible = "arm,sp805", "arm,primecell"; 515 reg = <0x0 0xc010000 0x0 0x1000>; 516 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 517 clock-names = "apb_pclk", "wdog_clk"; 518 }; 519 520 sai1: audio-controller@f100000 { 521 #sound-dai-cells = <0>; 522 compatible = "fsl,vf610-sai"; 523 reg = <0x0 0xf100000 0x0 0x10000>; 524 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 526 <&clockgen 4 1>, <&clockgen 4 1>; 527 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 528 dma-names = "tx", "rx"; 529 dmas = <&edma0 1 4>, 530 <&edma0 1 3>; 531 status = "disabled"; 532 }; 533 534 sai2: audio-controller@f110000 { 535 #sound-dai-cells = <0>; 536 compatible = "fsl,vf610-sai"; 537 reg = <0x0 0xf110000 0x0 0x10000>; 538 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 540 <&clockgen 4 1>, <&clockgen 4 1>; 541 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 542 dma-names = "tx", "rx"; 543 dmas = <&edma0 1 6>, 544 <&edma0 1 5>; 545 status = "disabled"; 546 }; 547 548 sai4: audio-controller@f130000 { 549 #sound-dai-cells = <0>; 550 compatible = "fsl,vf610-sai"; 551 reg = <0x0 0xf130000 0x0 0x10000>; 552 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 554 <&clockgen 4 1>, <&clockgen 4 1>; 555 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 556 dma-names = "tx", "rx"; 557 dmas = <&edma0 1 10>, 558 <&edma0 1 9>; 559 status = "disabled"; 560 }; 561 562 tmu: tmu@1f80000 { 563 compatible = "fsl,qoriq-tmu"; 564 reg = <0x0 0x1f80000 0x0 0x10000>; 565 interrupts = <0 23 0x4>; 566 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 567 fsl,tmu-calibration = <0x00000000 0x00000024 568 0x00000001 0x0000002b 569 0x00000002 0x00000031 570 0x00000003 0x00000038 571 0x00000004 0x0000003f 572 0x00000005 0x00000045 573 0x00000006 0x0000004c 574 0x00000007 0x00000053 575 0x00000008 0x00000059 576 0x00000009 0x00000060 577 0x0000000a 0x00000066 578 0x0000000b 0x0000006d 579 580 0x00010000 0x0000001c 581 0x00010001 0x00000024 582 0x00010002 0x0000002c 583 0x00010003 0x00000035 584 0x00010004 0x0000003d 585 0x00010005 0x00000045 586 0x00010006 0x0000004d 587 0x00010007 0x00000045 588 0x00010008 0x0000005e 589 0x00010009 0x00000066 590 0x0001000a 0x0000006e 591 592 0x00020000 0x00000018 593 0x00020001 0x00000022 594 0x00020002 0x0000002d 595 0x00020003 0x00000038 596 0x00020004 0x00000043 597 0x00020005 0x0000004d 598 0x00020006 0x00000058 599 0x00020007 0x00000063 600 0x00020008 0x0000006e 601 602 0x00030000 0x00000010 603 0x00030001 0x0000001c 604 0x00030002 0x00000029 605 0x00030003 0x00000036 606 0x00030004 0x00000042 607 0x00030005 0x0000004f 608 0x00030006 0x0000005b 609 0x00030007 0x00000068>; 610 little-endian; 611 #thermal-sensor-cells = <1>; 612 }; 613 614 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 615 compatible = "pci-host-ecam-generic"; 616 reg = <0x01 0xf0000000 0x0 0x100000>; 617 #address-cells = <3>; 618 #size-cells = <2>; 619 #interrupt-cells = <1>; 620 msi-parent = <&its>; 621 device_type = "pci"; 622 bus-range = <0x0 0x0>; 623 dma-coherent; 624 msi-map = <0 &its 0x17 0xe>; 625 iommu-map = <0 &smmu 0x17 0xe>; 626 /* PF0-6 BAR0 - non-prefetchable memory */ 627 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 628 /* PF0-6 BAR2 - prefetchable memory */ 629 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 630 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 631 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 632 /* PF0: VF0-1 BAR2 - prefetchable memory */ 633 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 634 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 635 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 636 /* PF1: VF0-1 BAR2 - prefetchable memory */ 637 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 638 639 enetc_port0: ethernet@0,0 { 640 compatible = "fsl,enetc"; 641 reg = <0x000000 0 0 0 0>; 642 }; 643 enetc_port1: ethernet@0,1 { 644 compatible = "fsl,enetc"; 645 reg = <0x000100 0 0 0 0>; 646 }; 647 enetc_mdio_pf3: mdio@0,3 { 648 compatible = "fsl,enetc-mdio"; 649 reg = <0x000300 0 0 0 0>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 }; 653 ethernet@0,4 { 654 compatible = "fsl,enetc-ptp"; 655 reg = <0x000400 0 0 0 0>; 656 clocks = <&clockgen 4 0>; 657 little-endian; 658 }; 659 }; 660 }; 661 662 malidp0: display@f080000 { 663 compatible = "arm,mali-dp500"; 664 reg = <0x0 0xf080000 0x0 0x10000>; 665 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 666 <0 223 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "DE", "SE"; 668 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 669 <&clockgen 2 2>; 670 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 671 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 672 arm,malidp-arqos-value = <0xd000d000>; 673 674 port { 675 dp0_out: endpoint { 676 677 }; 678 }; 679 }; 680}; 681