1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 i-cache-size = <0xc000>; 32 i-cache-line-size = <64>; 33 i-cache-sets = <256>; 34 d-cache-size = <0x8000>; 35 d-cache-line-size = <64>; 36 d-cache-sets = <256>; 37 next-level-cache = <&l2>; 38 cpu-idle-states = <&CPU_PW20>; 39 #cooling-cells = <2>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a72"; 45 reg = <0x1>; 46 enable-method = "psci"; 47 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 48 i-cache-size = <0xc000>; 49 i-cache-line-size = <64>; 50 i-cache-sets = <256>; 51 d-cache-size = <0x8000>; 52 d-cache-line-size = <64>; 53 d-cache-sets = <256>; 54 next-level-cache = <&l2>; 55 cpu-idle-states = <&CPU_PW20>; 56 #cooling-cells = <2>; 57 }; 58 59 l2: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 cache-size = <0x100000>; 64 cache-line-size = <64>; 65 cache-sets = <1024>; 66 }; 67 }; 68 69 idle-states { 70 /* 71 * PSCI node is not added default, U-boot will add missing 72 * parts if it determines to use PSCI. 73 */ 74 entry-method = "psci"; 75 76 CPU_PW20: cpu-pw20 { 77 compatible = "arm,idle-state"; 78 idle-state-name = "PW20"; 79 arm,psci-suspend-param = <0x0>; 80 entry-latency-us = <2000>; 81 exit-latency-us = <2000>; 82 min-residency-us = <6000>; 83 }; 84 }; 85 86 rtc_clk: rtc-clk { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <32768>; 90 clock-output-names = "rtc_clk"; 91 }; 92 93 sysclk: sysclk { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <100000000>; 97 clock-output-names = "sysclk"; 98 }; 99 100 osc_27m: clock-osc-27m { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <27000000>; 104 clock-output-names = "phy_27m"; 105 }; 106 107 firmware { 108 optee: optee { 109 compatible = "linaro,optee-tz"; 110 method = "smc"; 111 status = "disabled"; 112 }; 113 }; 114 115 timer { 116 compatible = "arm,armv8-timer"; 117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 118 IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 120 IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 122 IRQ_TYPE_LEVEL_LOW)>, 123 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 124 IRQ_TYPE_LEVEL_LOW)>; 125 }; 126 127 pmu { 128 compatible = "arm,cortex-a72-pmu"; 129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 gic: interrupt-controller@6000000 { 133 compatible = "arm,gic-v3"; 134 #address-cells = <2>; 135 #size-cells = <2>; 136 ranges; 137 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 138 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 139 #interrupt-cells = <3>; 140 interrupt-controller; 141 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 142 IRQ_TYPE_LEVEL_LOW)>; 143 its: msi-controller@6020000 { 144 compatible = "arm,gic-v3-its"; 145 msi-controller; 146 #msi-cells = <1>; 147 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 148 }; 149 }; 150 151 thermal-zones { 152 ddr-thermal { 153 polling-delay-passive = <1000>; 154 polling-delay = <5000>; 155 thermal-sensors = <&tmu 0>; 156 157 trips { 158 ddr-ctrler-alert { 159 temperature = <85000>; 160 hysteresis = <2000>; 161 type = "passive"; 162 }; 163 164 ddr-ctrler-crit { 165 temperature = <95000>; 166 hysteresis = <2000>; 167 type = "critical"; 168 }; 169 }; 170 }; 171 172 cluster-thermal { 173 polling-delay-passive = <1000>; 174 polling-delay = <5000>; 175 thermal-sensors = <&tmu 1>; 176 177 trips { 178 core_cluster_alert: core-cluster-alert { 179 temperature = <85000>; 180 hysteresis = <2000>; 181 type = "passive"; 182 }; 183 184 core_cluster_crit: core-cluster-crit { 185 temperature = <95000>; 186 hysteresis = <2000>; 187 type = "critical"; 188 }; 189 }; 190 191 cooling-maps { 192 map0 { 193 trip = <&core_cluster_alert>; 194 cooling-device = 195 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 196 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 197 }; 198 }; 199 }; 200 }; 201 202 soc: soc { 203 compatible = "simple-bus"; 204 #address-cells = <2>; 205 #size-cells = <2>; 206 ranges; 207 208 ddr: memory-controller@1080000 { 209 compatible = "fsl,qoriq-memory-controller"; 210 reg = <0x0 0x1080000 0x0 0x1000>; 211 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 212 little-endian; 213 }; 214 215 dcfg: syscon@1e00000 { 216 #address-cells = <1>; 217 #size-cells = <1>; 218 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 219 reg = <0x0 0x1e00000 0x0 0x10000>; 220 ranges = <0x0 0x0 0x1e00000 0x10000>; 221 little-endian; 222 223 fspi_clk: clock-controller@900 { 224 compatible = "fsl,ls1028a-flexspi-clk"; 225 reg = <0x900 0x4>; 226 #clock-cells = <0>; 227 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 228 clock-output-names = "fspi_clk"; 229 }; 230 }; 231 232 syscon@1e60000 { 233 compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd"; 234 reg = <0x0 0x1e60000 0x0 0x10000>; 235 little-endian; 236 237 reboot { 238 compatible = "syscon-reboot"; 239 offset = <0>; 240 mask = <0x02>; 241 }; 242 }; 243 244 sfp: efuse@1e80000 { 245 compatible = "fsl,ls1028a-sfp"; 246 reg = <0x0 0x1e80000 0x0 0x10000>; 247 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 248 QORIQ_CLK_PLL_DIV(4)>; 249 clock-names = "sfp"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 253 ls1028a_uid: unique-id@1c { 254 reg = <0x1c 0x8>; 255 }; 256 }; 257 258 scfg: syscon@1fc0000 { 259 compatible = "fsl,ls1028a-scfg", "syscon"; 260 reg = <0x0 0x1fc0000 0x0 0x10000>; 261 big-endian; 262 }; 263 264 clockgen: clock-controller@1300000 { 265 compatible = "fsl,ls1028a-clockgen"; 266 reg = <0x0 0x1300000 0x0 0xa0000>; 267 #clock-cells = <2>; 268 clocks = <&sysclk>; 269 }; 270 271 i2c0: i2c@2000000 { 272 compatible = "fsl,vf610-i2c"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 reg = <0x0 0x2000000 0x0 0x10000>; 276 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 278 QORIQ_CLK_PLL_DIV(4)>; 279 status = "disabled"; 280 }; 281 282 i2c1: i2c@2010000 { 283 compatible = "fsl,vf610-i2c"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 reg = <0x0 0x2010000 0x0 0x10000>; 287 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 289 QORIQ_CLK_PLL_DIV(4)>; 290 status = "disabled"; 291 }; 292 293 i2c2: i2c@2020000 { 294 compatible = "fsl,vf610-i2c"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 reg = <0x0 0x2020000 0x0 0x10000>; 298 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 300 QORIQ_CLK_PLL_DIV(4)>; 301 status = "disabled"; 302 }; 303 304 i2c3: i2c@2030000 { 305 compatible = "fsl,vf610-i2c"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x0 0x2030000 0x0 0x10000>; 309 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 311 QORIQ_CLK_PLL_DIV(4)>; 312 status = "disabled"; 313 }; 314 315 i2c4: i2c@2040000 { 316 compatible = "fsl,vf610-i2c"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <0x0 0x2040000 0x0 0x10000>; 320 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 322 QORIQ_CLK_PLL_DIV(4)>; 323 status = "disabled"; 324 }; 325 326 i2c5: i2c@2050000 { 327 compatible = "fsl,vf610-i2c"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 reg = <0x0 0x2050000 0x0 0x10000>; 331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 333 QORIQ_CLK_PLL_DIV(4)>; 334 status = "disabled"; 335 }; 336 337 i2c6: i2c@2060000 { 338 compatible = "fsl,vf610-i2c"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 reg = <0x0 0x2060000 0x0 0x10000>; 342 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 344 QORIQ_CLK_PLL_DIV(4)>; 345 status = "disabled"; 346 }; 347 348 i2c7: i2c@2070000 { 349 compatible = "fsl,vf610-i2c"; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <0x0 0x2070000 0x0 0x10000>; 353 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 355 QORIQ_CLK_PLL_DIV(4)>; 356 status = "disabled"; 357 }; 358 359 fspi: spi@20c0000 { 360 compatible = "nxp,lx2160a-fspi"; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <0x0 0x20c0000 0x0 0x10000>, 364 <0x0 0x20000000 0x0 0x10000000>; 365 reg-names = "fspi_base", "fspi_mmap"; 366 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&fspi_clk>, <&fspi_clk>; 368 clock-names = "fspi_en", "fspi"; 369 status = "disabled"; 370 }; 371 372 dspi0: spi@2100000 { 373 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0x0 0x2100000 0x0 0x10000>; 377 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 378 clock-names = "dspi"; 379 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 380 QORIQ_CLK_PLL_DIV(2)>; 381 dmas = <&edma0 0 62>, <&edma0 0 60>; 382 dma-names = "tx", "rx"; 383 spi-num-chipselects = <4>; 384 status = "disabled"; 385 }; 386 387 dspi1: spi@2110000 { 388 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0x0 0x2110000 0x0 0x10000>; 392 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 393 clock-names = "dspi"; 394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 395 QORIQ_CLK_PLL_DIV(2)>; 396 dmas = <&edma0 0 58>, <&edma0 0 56>; 397 dma-names = "tx", "rx"; 398 spi-num-chipselects = <4>; 399 status = "disabled"; 400 }; 401 402 dspi2: spi@2120000 { 403 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0x0 0x2120000 0x0 0x10000>; 407 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 408 clock-names = "dspi"; 409 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 410 QORIQ_CLK_PLL_DIV(2)>; 411 dmas = <&edma0 0 54>, <&edma0 0 2>; 412 dma-names = "tx", "rx"; 413 spi-num-chipselects = <3>; 414 status = "disabled"; 415 }; 416 417 esdhc: mmc@2140000 { 418 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 419 reg = <0x0 0x2140000 0x0 0x10000>; 420 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <0>; /* fixed up by bootloader */ 422 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 423 voltage-ranges = <1800 1800 3300 3300>; 424 sdhci,auto-cmd12; 425 little-endian; 426 bus-width = <4>; 427 status = "disabled"; 428 }; 429 430 esdhc1: mmc@2150000 { 431 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 432 reg = <0x0 0x2150000 0x0 0x10000>; 433 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 434 clock-frequency = <0>; /* fixed up by bootloader */ 435 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 436 voltage-ranges = <1800 1800>; 437 sdhci,auto-cmd12; 438 non-removable; 439 little-endian; 440 bus-width = <4>; 441 status = "disabled"; 442 }; 443 444 can0: can@2180000 { 445 compatible = "fsl,lx2160ar1-flexcan"; 446 reg = <0x0 0x2180000 0x0 0x10000>; 447 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 449 QORIQ_CLK_PLL_DIV(2)>, 450 <&clockgen QORIQ_CLK_PLATFORM_PLL 451 QORIQ_CLK_PLL_DIV(2)>; 452 clock-names = "ipg", "per"; 453 status = "disabled"; 454 }; 455 456 can1: can@2190000 { 457 compatible = "fsl,lx2160ar1-flexcan"; 458 reg = <0x0 0x2190000 0x0 0x10000>; 459 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 461 QORIQ_CLK_PLL_DIV(2)>, 462 <&clockgen QORIQ_CLK_PLATFORM_PLL 463 QORIQ_CLK_PLL_DIV(2)>; 464 clock-names = "ipg", "per"; 465 status = "disabled"; 466 }; 467 468 duart0: serial@21c0500 { 469 compatible = "fsl,ns16550", "ns16550a"; 470 reg = <0x00 0x21c0500 0x0 0x100>; 471 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 473 QORIQ_CLK_PLL_DIV(2)>; 474 status = "disabled"; 475 }; 476 477 duart1: serial@21c0600 { 478 compatible = "fsl,ns16550", "ns16550a"; 479 reg = <0x00 0x21c0600 0x0 0x100>; 480 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 482 QORIQ_CLK_PLL_DIV(2)>; 483 status = "disabled"; 484 }; 485 486 487 lpuart0: serial@2260000 { 488 compatible = "fsl,ls1028a-lpuart"; 489 reg = <0x0 0x2260000 0x0 0x1000>; 490 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 492 QORIQ_CLK_PLL_DIV(2)>; 493 clock-names = "ipg"; 494 dma-names = "rx","tx"; 495 dmas = <&edma0 1 32>, 496 <&edma0 1 33>; 497 status = "disabled"; 498 }; 499 500 lpuart1: serial@2270000 { 501 compatible = "fsl,ls1028a-lpuart"; 502 reg = <0x0 0x2270000 0x0 0x1000>; 503 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 505 QORIQ_CLK_PLL_DIV(2)>; 506 clock-names = "ipg"; 507 dma-names = "rx","tx"; 508 dmas = <&edma0 1 30>, 509 <&edma0 1 31>; 510 status = "disabled"; 511 }; 512 513 lpuart2: serial@2280000 { 514 compatible = "fsl,ls1028a-lpuart"; 515 reg = <0x0 0x2280000 0x0 0x1000>; 516 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 518 QORIQ_CLK_PLL_DIV(2)>; 519 clock-names = "ipg"; 520 dma-names = "rx","tx"; 521 dmas = <&edma0 1 28>, 522 <&edma0 1 29>; 523 status = "disabled"; 524 }; 525 526 lpuart3: serial@2290000 { 527 compatible = "fsl,ls1028a-lpuart"; 528 reg = <0x0 0x2290000 0x0 0x1000>; 529 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 531 QORIQ_CLK_PLL_DIV(2)>; 532 clock-names = "ipg"; 533 dma-names = "rx","tx"; 534 dmas = <&edma0 1 26>, 535 <&edma0 1 27>; 536 status = "disabled"; 537 }; 538 539 lpuart4: serial@22a0000 { 540 compatible = "fsl,ls1028a-lpuart"; 541 reg = <0x0 0x22a0000 0x0 0x1000>; 542 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 544 QORIQ_CLK_PLL_DIV(2)>; 545 clock-names = "ipg"; 546 dma-names = "rx","tx"; 547 dmas = <&edma0 1 24>, 548 <&edma0 1 25>; 549 status = "disabled"; 550 }; 551 552 lpuart5: serial@22b0000 { 553 compatible = "fsl,ls1028a-lpuart"; 554 reg = <0x0 0x22b0000 0x0 0x1000>; 555 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 557 QORIQ_CLK_PLL_DIV(2)>; 558 clock-names = "ipg"; 559 dma-names = "rx","tx"; 560 dmas = <&edma0 1 22>, 561 <&edma0 1 23>; 562 status = "disabled"; 563 }; 564 565 edma0: dma-controller@22c0000 { 566 #dma-cells = <2>; 567 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 568 reg = <0x0 0x22c0000 0x0 0x10000>, 569 <0x0 0x22d0000 0x0 0x10000>, 570 <0x0 0x22e0000 0x0 0x10000>; 571 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "edma-tx", "edma-err"; 574 dma-channels = <32>; 575 clock-names = "dmamux0", "dmamux1"; 576 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 577 QORIQ_CLK_PLL_DIV(2)>, 578 <&clockgen QORIQ_CLK_PLATFORM_PLL 579 QORIQ_CLK_PLL_DIV(2)>; 580 }; 581 582 gpio1: gpio@2300000 { 583 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 584 reg = <0x0 0x2300000 0x0 0x10000>; 585 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 little-endian; 591 }; 592 593 gpio2: gpio@2310000 { 594 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 595 reg = <0x0 0x2310000 0x0 0x10000>; 596 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 little-endian; 602 }; 603 604 gpio3: gpio@2320000 { 605 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 606 reg = <0x0 0x2320000 0x0 0x10000>; 607 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 608 gpio-controller; 609 #gpio-cells = <2>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 little-endian; 613 }; 614 615 usb0: usb@3100000 { 616 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 617 reg = <0x0 0x3100000 0x0 0x10000>; 618 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 619 snps,dis_rxdet_inp3_quirk; 620 snps,quirk-frame-length-adjustment = <0x20>; 621 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 622 status = "disabled"; 623 }; 624 625 usb1: usb@3110000 { 626 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 627 reg = <0x0 0x3110000 0x0 0x10000>; 628 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 629 snps,dis_rxdet_inp3_quirk; 630 snps,quirk-frame-length-adjustment = <0x20>; 631 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 632 status = "disabled"; 633 }; 634 635 sata: sata@3200000 { 636 compatible = "fsl,ls1028a-ahci"; 637 reg = <0x0 0x3200000 0x0 0x10000>, 638 <0x7 0x100520 0x0 0x4>; 639 reg-names = "ahci", "sata-ecc"; 640 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 642 QORIQ_CLK_PLL_DIV(2)>; 643 status = "disabled"; 644 }; 645 646 pcie1: pcie@3400000 { 647 compatible = "fsl,ls1028a-pcie"; 648 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 649 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 650 reg-names = "regs", "config"; 651 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 652 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 653 interrupt-names = "pme", "aer"; 654 #address-cells = <3>; 655 #size-cells = <2>; 656 device_type = "pci"; 657 dma-coherent; 658 num-viewport = <8>; 659 bus-range = <0x0 0xff>; 660 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 661 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 662 msi-parent = <&its 0>; 663 #interrupt-cells = <1>; 664 interrupt-map-mask = <0 0 0 7>; 665 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 666 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 667 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 668 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 669 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 670 status = "disabled"; 671 }; 672 673 pcie_ep1: pcie-ep@3400000 { 674 compatible = "fsl,ls1028a-pcie-ep"; 675 reg = <0x00 0x03400000 0x0 0x00100000 676 0x80 0x00000000 0x8 0x00000000>; 677 reg-names = "regs", "addr_space"; 678 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 679 interrupt-names = "pme"; 680 num-ib-windows = <6>; 681 num-ob-windows = <8>; 682 status = "disabled"; 683 }; 684 685 pcie2: pcie@3500000 { 686 compatible = "fsl,ls1028a-pcie"; 687 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 688 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 689 reg-names = "regs", "config"; 690 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-names = "pme", "aer"; 693 #address-cells = <3>; 694 #size-cells = <2>; 695 device_type = "pci"; 696 dma-coherent; 697 num-viewport = <8>; 698 bus-range = <0x0 0xff>; 699 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 700 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 701 msi-parent = <&its 0>; 702 #interrupt-cells = <1>; 703 interrupt-map-mask = <0 0 0 7>; 704 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 705 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 706 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 707 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 708 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 709 status = "disabled"; 710 }; 711 712 pcie_ep2: pcie-ep@3500000 { 713 compatible = "fsl,ls1028a-pcie-ep"; 714 reg = <0x00 0x03500000 0x0 0x00100000 715 0x88 0x00000000 0x8 0x00000000>; 716 reg-names = "regs", "addr_space"; 717 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 718 interrupt-names = "pme"; 719 num-ib-windows = <6>; 720 num-ob-windows = <8>; 721 status = "disabled"; 722 }; 723 724 smmu: iommu@5000000 { 725 compatible = "arm,mmu-500"; 726 reg = <0 0x5000000 0 0x800000>; 727 #global-interrupts = <8>; 728 #iommu-cells = <1>; 729 dma-coherent; 730 stream-match-mask = <0x7c00>; 731 /* global secure fault */ 732 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 733 /* combined secure interrupt */ 734 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 735 /* global non-secure fault */ 736 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 737 /* combined non-secure interrupt */ 738 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 739 /* performance counter interrupts 0-7 */ 740 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 742 /* per context interrupt, 64 interrupts */ 743 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 775 }; 776 777 crypto: crypto@8000000 { 778 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 779 fsl,sec-era = <10>; 780 #address-cells = <1>; 781 #size-cells = <1>; 782 ranges = <0x0 0x00 0x8000000 0x100000>; 783 reg = <0x00 0x8000000 0x0 0x100000>; 784 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 785 dma-coherent; 786 787 sec_jr0: jr@10000 { 788 compatible = "fsl,sec-v5.0-job-ring", 789 "fsl,sec-v4.0-job-ring"; 790 reg = <0x10000 0x10000>; 791 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 792 }; 793 794 sec_jr1: jr@20000 { 795 compatible = "fsl,sec-v5.0-job-ring", 796 "fsl,sec-v4.0-job-ring"; 797 reg = <0x20000 0x10000>; 798 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 799 }; 800 801 sec_jr2: jr@30000 { 802 compatible = "fsl,sec-v5.0-job-ring", 803 "fsl,sec-v4.0-job-ring"; 804 reg = <0x30000 0x10000>; 805 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 806 }; 807 808 sec_jr3: jr@40000 { 809 compatible = "fsl,sec-v5.0-job-ring", 810 "fsl,sec-v4.0-job-ring"; 811 reg = <0x40000 0x10000>; 812 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 813 }; 814 }; 815 816 qdma: dma-controller@8380000 { 817 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 818 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 819 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 820 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 821 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-names = "qdma-error", "qdma-queue0", 827 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 828 #dma-cells = <1>; 829 dma-channels = <8>; 830 block-number = <1>; 831 block-offset = <0x10000>; 832 fsl,dma-queues = <2>; 833 status-sizes = <64>; 834 queue-sizes = <64 64>; 835 }; 836 837 cluster1_core0_watchdog: watchdog@c000000 { 838 compatible = "arm,sp805", "arm,primecell"; 839 reg = <0x0 0xc000000 0x0 0x1000>; 840 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 841 QORIQ_CLK_PLL_DIV(16)>, 842 <&clockgen QORIQ_CLK_PLATFORM_PLL 843 QORIQ_CLK_PLL_DIV(16)>; 844 clock-names = "wdog_clk", "apb_pclk"; 845 }; 846 847 cluster1_core1_watchdog: watchdog@c010000 { 848 compatible = "arm,sp805", "arm,primecell"; 849 reg = <0x0 0xc010000 0x0 0x1000>; 850 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 851 QORIQ_CLK_PLL_DIV(16)>, 852 <&clockgen QORIQ_CLK_PLATFORM_PLL 853 QORIQ_CLK_PLL_DIV(16)>; 854 clock-names = "wdog_clk", "apb_pclk"; 855 }; 856 857 malidp0: display@f080000 { 858 compatible = "arm,mali-dp500"; 859 reg = <0x0 0xf080000 0x0 0x10000>; 860 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "DE", "SE"; 863 clocks = <&dpclk>, 864 <&clockgen QORIQ_CLK_HWACCEL 2>, 865 <&clockgen QORIQ_CLK_HWACCEL 2>, 866 <&clockgen QORIQ_CLK_HWACCEL 2>; 867 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 868 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 869 arm,malidp-arqos-value = <0xd000d000>; 870 871 port { 872 dpi0_out: endpoint { 873 874 }; 875 }; 876 }; 877 878 gpu: gpu@f0c0000 { 879 compatible = "vivante,gc"; 880 reg = <0x0 0xf0c0000 0x0 0x10000>; 881 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 883 <&clockgen QORIQ_CLK_HWACCEL 2>, 884 <&clockgen QORIQ_CLK_HWACCEL 2>; 885 clock-names = "core", "shader", "bus"; 886 #cooling-cells = <2>; 887 }; 888 889 sai1: audio-controller@f100000 { 890 #sound-dai-cells = <0>; 891 compatible = "fsl,vf610-sai"; 892 reg = <0x0 0xf100000 0x0 0x10000>; 893 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 895 QORIQ_CLK_PLL_DIV(2)>, 896 <&clockgen QORIQ_CLK_PLATFORM_PLL 897 QORIQ_CLK_PLL_DIV(2)>, 898 <&clockgen QORIQ_CLK_PLATFORM_PLL 899 QORIQ_CLK_PLL_DIV(2)>, 900 <&clockgen QORIQ_CLK_PLATFORM_PLL 901 QORIQ_CLK_PLL_DIV(2)>; 902 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 903 dma-names = "rx", "tx"; 904 dmas = <&edma0 1 3>, 905 <&edma0 1 4>; 906 fsl,sai-asynchronous; 907 status = "disabled"; 908 }; 909 910 sai2: audio-controller@f110000 { 911 #sound-dai-cells = <0>; 912 compatible = "fsl,vf610-sai"; 913 reg = <0x0 0xf110000 0x0 0x10000>; 914 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 916 QORIQ_CLK_PLL_DIV(2)>, 917 <&clockgen QORIQ_CLK_PLATFORM_PLL 918 QORIQ_CLK_PLL_DIV(2)>, 919 <&clockgen QORIQ_CLK_PLATFORM_PLL 920 QORIQ_CLK_PLL_DIV(2)>, 921 <&clockgen QORIQ_CLK_PLATFORM_PLL 922 QORIQ_CLK_PLL_DIV(2)>; 923 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 924 dma-names = "rx", "tx"; 925 dmas = <&edma0 1 5>, 926 <&edma0 1 6>; 927 fsl,sai-asynchronous; 928 status = "disabled"; 929 }; 930 931 sai3: audio-controller@f120000 { 932 #sound-dai-cells = <0>; 933 compatible = "fsl,vf610-sai"; 934 reg = <0x0 0xf120000 0x0 0x10000>; 935 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 937 QORIQ_CLK_PLL_DIV(2)>, 938 <&clockgen QORIQ_CLK_PLATFORM_PLL 939 QORIQ_CLK_PLL_DIV(2)>, 940 <&clockgen QORIQ_CLK_PLATFORM_PLL 941 QORIQ_CLK_PLL_DIV(2)>, 942 <&clockgen QORIQ_CLK_PLATFORM_PLL 943 QORIQ_CLK_PLL_DIV(2)>; 944 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 945 dma-names = "rx", "tx"; 946 dmas = <&edma0 1 7>, 947 <&edma0 1 8>; 948 fsl,sai-asynchronous; 949 status = "disabled"; 950 }; 951 952 sai4: audio-controller@f130000 { 953 #sound-dai-cells = <0>; 954 compatible = "fsl,vf610-sai"; 955 reg = <0x0 0xf130000 0x0 0x10000>; 956 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 958 QORIQ_CLK_PLL_DIV(2)>, 959 <&clockgen QORIQ_CLK_PLATFORM_PLL 960 QORIQ_CLK_PLL_DIV(2)>, 961 <&clockgen QORIQ_CLK_PLATFORM_PLL 962 QORIQ_CLK_PLL_DIV(2)>, 963 <&clockgen QORIQ_CLK_PLATFORM_PLL 964 QORIQ_CLK_PLL_DIV(2)>; 965 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 966 dma-names = "rx", "tx"; 967 dmas = <&edma0 1 9>, 968 <&edma0 1 10>; 969 fsl,sai-asynchronous; 970 status = "disabled"; 971 }; 972 973 sai5: audio-controller@f140000 { 974 #sound-dai-cells = <0>; 975 compatible = "fsl,vf610-sai"; 976 reg = <0x0 0xf140000 0x0 0x10000>; 977 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 979 QORIQ_CLK_PLL_DIV(2)>, 980 <&clockgen QORIQ_CLK_PLATFORM_PLL 981 QORIQ_CLK_PLL_DIV(2)>, 982 <&clockgen QORIQ_CLK_PLATFORM_PLL 983 QORIQ_CLK_PLL_DIV(2)>, 984 <&clockgen QORIQ_CLK_PLATFORM_PLL 985 QORIQ_CLK_PLL_DIV(2)>; 986 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 987 dma-names = "rx", "tx"; 988 dmas = <&edma0 1 11>, 989 <&edma0 1 12>; 990 fsl,sai-asynchronous; 991 status = "disabled"; 992 }; 993 994 sai6: audio-controller@f150000 { 995 #sound-dai-cells = <0>; 996 compatible = "fsl,vf610-sai"; 997 reg = <0x0 0xf150000 0x0 0x10000>; 998 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1000 QORIQ_CLK_PLL_DIV(2)>, 1001 <&clockgen QORIQ_CLK_PLATFORM_PLL 1002 QORIQ_CLK_PLL_DIV(2)>, 1003 <&clockgen QORIQ_CLK_PLATFORM_PLL 1004 QORIQ_CLK_PLL_DIV(2)>, 1005 <&clockgen QORIQ_CLK_PLATFORM_PLL 1006 QORIQ_CLK_PLL_DIV(2)>; 1007 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1008 dma-names = "rx", "tx"; 1009 dmas = <&edma0 1 13>, 1010 <&edma0 1 14>; 1011 fsl,sai-asynchronous; 1012 status = "disabled"; 1013 }; 1014 1015 dpclk: clock-controller@f1f0000 { 1016 compatible = "fsl,ls1028a-plldig"; 1017 reg = <0x0 0xf1f0000 0x0 0x10000>; 1018 #clock-cells = <0>; 1019 clocks = <&osc_27m>; 1020 }; 1021 1022 tmu: tmu@1f80000 { 1023 compatible = "fsl,qoriq-tmu"; 1024 reg = <0x0 0x1f80000 0x0 0x10000>; 1025 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1026 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1027 fsl,tmu-calibration = 1028 <0x00000000 0x00000024>, 1029 <0x00000001 0x0000002b>, 1030 <0x00000002 0x00000031>, 1031 <0x00000003 0x00000038>, 1032 <0x00000004 0x0000003f>, 1033 <0x00000005 0x00000045>, 1034 <0x00000006 0x0000004c>, 1035 <0x00000007 0x00000053>, 1036 <0x00000008 0x00000059>, 1037 <0x00000009 0x00000060>, 1038 <0x0000000a 0x00000066>, 1039 <0x0000000b 0x0000006d>, 1040 1041 <0x00010000 0x0000001c>, 1042 <0x00010001 0x00000024>, 1043 <0x00010002 0x0000002c>, 1044 <0x00010003 0x00000035>, 1045 <0x00010004 0x0000003d>, 1046 <0x00010005 0x00000045>, 1047 <0x00010006 0x0000004d>, 1048 <0x00010007 0x00000055>, 1049 <0x00010008 0x0000005e>, 1050 <0x00010009 0x00000066>, 1051 <0x0001000a 0x0000006e>, 1052 1053 <0x00020000 0x00000018>, 1054 <0x00020001 0x00000022>, 1055 <0x00020002 0x0000002d>, 1056 <0x00020003 0x00000038>, 1057 <0x00020004 0x00000043>, 1058 <0x00020005 0x0000004d>, 1059 <0x00020006 0x00000058>, 1060 <0x00020007 0x00000063>, 1061 <0x00020008 0x0000006e>, 1062 1063 <0x00030000 0x00000010>, 1064 <0x00030001 0x0000001c>, 1065 <0x00030002 0x00000029>, 1066 <0x00030003 0x00000036>, 1067 <0x00030004 0x00000042>, 1068 <0x00030005 0x0000004f>, 1069 <0x00030006 0x0000005b>, 1070 <0x00030007 0x00000068>; 1071 little-endian; 1072 #thermal-sensor-cells = <1>; 1073 }; 1074 1075 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1076 compatible = "pci-host-ecam-generic"; 1077 reg = <0x01 0xf0000000 0x0 0x100000>; 1078 #address-cells = <3>; 1079 #size-cells = <2>; 1080 msi-parent = <&its 0>; 1081 device_type = "pci"; 1082 bus-range = <0x0 0x0>; 1083 dma-coherent; 1084 msi-map = <0 &its 0x17 0xe>; 1085 iommu-map = <0 &smmu 0x17 0xe>; 1086 /* PF0-6 BAR0 - non-prefetchable memory */ 1087 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1088 /* PF0-6 BAR2 - prefetchable memory */ 1089 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1090 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1091 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1092 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1093 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1094 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1095 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1096 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1097 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1098 /* BAR4 (PF5) - non-prefetchable memory */ 1099 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1100 #interrupt-cells = <1>; 1101 interrupt-map-mask = <0 0 0 7>; 1102 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1103 <0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1104 1105 enetc_port0: ethernet@0,0 { 1106 compatible = "pci1957,e100", "fsl,enetc"; 1107 reg = <0x000000 0 0 0 0>; 1108 status = "disabled"; 1109 }; 1110 1111 enetc_port1: ethernet@0,1 { 1112 compatible = "pci1957,e100", "fsl,enetc"; 1113 reg = <0x000100 0 0 0 0>; 1114 status = "disabled"; 1115 }; 1116 1117 enetc_port2: ethernet@0,2 { 1118 compatible = "pci1957,e100", "fsl,enetc"; 1119 reg = <0x000200 0 0 0 0>; 1120 phy-mode = "internal"; 1121 status = "disabled"; 1122 1123 fixed-link { 1124 speed = <2500>; 1125 full-duplex; 1126 pause; 1127 }; 1128 }; 1129 1130 enetc_mdio_pf3: mdio@0,3 { 1131 compatible = "pci1957,ee01", "fsl,enetc-mdio"; 1132 reg = <0x000300 0 0 0 0>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 }; 1136 1137 ethernet@0,4 { 1138 compatible = "pci1957,ee02", "fsl,enetc-ptp"; 1139 reg = <0x000400 0 0 0 0>; 1140 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1141 little-endian; 1142 fsl,extts-fifo; 1143 }; 1144 1145 mscc_felix: ethernet-switch@0,5 { 1146 reg = <0x000500 0 0 0 0>; 1147 /* IEP INT_B */ 1148 interrupts = <2>; 1149 status = "disabled"; 1150 1151 mscc_felix_ports: ports { 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 1155 /* External ports */ 1156 mscc_felix_port0: port@0 { 1157 reg = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 mscc_felix_port1: port@1 { 1162 reg = <1>; 1163 status = "disabled"; 1164 }; 1165 1166 mscc_felix_port2: port@2 { 1167 reg = <2>; 1168 status = "disabled"; 1169 }; 1170 1171 mscc_felix_port3: port@3 { 1172 reg = <3>; 1173 status = "disabled"; 1174 }; 1175 1176 /* Internal ports */ 1177 mscc_felix_port4: port@4 { 1178 reg = <4>; 1179 phy-mode = "internal"; 1180 ethernet = <&enetc_port2>; 1181 status = "disabled"; 1182 1183 fixed-link { 1184 speed = <2500>; 1185 full-duplex; 1186 pause; 1187 }; 1188 }; 1189 1190 mscc_felix_port5: port@5 { 1191 reg = <5>; 1192 phy-mode = "internal"; 1193 ethernet = <&enetc_port3>; 1194 status = "disabled"; 1195 1196 fixed-link { 1197 speed = <1000>; 1198 full-duplex; 1199 pause; 1200 }; 1201 }; 1202 }; 1203 }; 1204 1205 enetc_port3: ethernet@0,6 { 1206 compatible = "pci1957,e100", "fsl,enetc"; 1207 reg = <0x000600 0 0 0 0>; 1208 phy-mode = "internal"; 1209 status = "disabled"; 1210 1211 fixed-link { 1212 speed = <1000>; 1213 full-duplex; 1214 pause; 1215 }; 1216 }; 1217 1218 rcec@1f,0 { 1219 reg = <0x00f800 0 0 0 0>; 1220 /* IEP INT_A */ 1221 interrupts = <1>; 1222 }; 1223 }; 1224 1225 /* Integrated Endpoint Register Block */ 1226 ierb@1f0800000 { 1227 compatible = "fsl,ls1028a-enetc-ierb"; 1228 reg = <0x01 0xf0800000 0x0 0x10000>; 1229 }; 1230 1231 pwm0: pwm@2800000 { 1232 compatible = "fsl,vf610-ftm-pwm"; 1233 #pwm-cells = <3>; 1234 reg = <0x0 0x2800000 0x0 0x10000>; 1235 clock-names = "ftm_sys", "ftm_ext", 1236 "ftm_fix", "ftm_cnt_clk_en"; 1237 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1238 <&rtc_clk>, <&clockgen 4 1>; 1239 status = "disabled"; 1240 }; 1241 1242 pwm1: pwm@2810000 { 1243 compatible = "fsl,vf610-ftm-pwm"; 1244 #pwm-cells = <3>; 1245 reg = <0x0 0x2810000 0x0 0x10000>; 1246 clock-names = "ftm_sys", "ftm_ext", 1247 "ftm_fix", "ftm_cnt_clk_en"; 1248 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1249 <&rtc_clk>, <&clockgen 4 1>; 1250 status = "disabled"; 1251 }; 1252 1253 pwm2: pwm@2820000 { 1254 compatible = "fsl,vf610-ftm-pwm"; 1255 #pwm-cells = <3>; 1256 reg = <0x0 0x2820000 0x0 0x10000>; 1257 clock-names = "ftm_sys", "ftm_ext", 1258 "ftm_fix", "ftm_cnt_clk_en"; 1259 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1260 <&rtc_clk>, <&clockgen 4 1>; 1261 status = "disabled"; 1262 }; 1263 1264 pwm3: pwm@2830000 { 1265 compatible = "fsl,vf610-ftm-pwm"; 1266 #pwm-cells = <3>; 1267 reg = <0x0 0x2830000 0x0 0x10000>; 1268 clock-names = "ftm_sys", "ftm_ext", 1269 "ftm_fix", "ftm_cnt_clk_en"; 1270 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1271 <&rtc_clk>, <&clockgen 4 1>; 1272 status = "disabled"; 1273 }; 1274 1275 pwm4: pwm@2840000 { 1276 compatible = "fsl,vf610-ftm-pwm"; 1277 #pwm-cells = <3>; 1278 reg = <0x0 0x2840000 0x0 0x10000>; 1279 clock-names = "ftm_sys", "ftm_ext", 1280 "ftm_fix", "ftm_cnt_clk_en"; 1281 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1282 <&rtc_clk>, <&clockgen 4 1>; 1283 status = "disabled"; 1284 }; 1285 1286 pwm5: pwm@2850000 { 1287 compatible = "fsl,vf610-ftm-pwm"; 1288 #pwm-cells = <3>; 1289 reg = <0x0 0x2850000 0x0 0x10000>; 1290 clock-names = "ftm_sys", "ftm_ext", 1291 "ftm_fix", "ftm_cnt_clk_en"; 1292 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1293 <&rtc_clk>, <&clockgen 4 1>; 1294 status = "disabled"; 1295 }; 1296 1297 pwm6: pwm@2860000 { 1298 compatible = "fsl,vf610-ftm-pwm"; 1299 #pwm-cells = <3>; 1300 reg = <0x0 0x2860000 0x0 0x10000>; 1301 clock-names = "ftm_sys", "ftm_ext", 1302 "ftm_fix", "ftm_cnt_clk_en"; 1303 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1304 <&rtc_clk>, <&clockgen 4 1>; 1305 status = "disabled"; 1306 }; 1307 1308 pwm7: pwm@2870000 { 1309 compatible = "fsl,vf610-ftm-pwm"; 1310 #pwm-cells = <3>; 1311 reg = <0x0 0x2870000 0x0 0x10000>; 1312 clock-names = "ftm_sys", "ftm_ext", 1313 "ftm_fix", "ftm_cnt_clk_en"; 1314 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1315 <&rtc_clk>, <&clockgen 4 1>; 1316 status = "disabled"; 1317 }; 1318 1319 rcpm: wakeup-controller@1e34040 { 1320 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1321 reg = <0x0 0x1e34040 0x0 0x1c>; 1322 #fsl,rcpm-wakeup-cells = <7>; 1323 little-endian; 1324 }; 1325 1326 ftm_alarm0: rtc@2800000 { 1327 compatible = "fsl,ls1028a-ftm-alarm"; 1328 reg = <0x0 0x2800000 0x0 0x10000>; 1329 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1330 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1331 status = "disabled"; 1332 }; 1333 1334 ftm_alarm1: rtc@2810000 { 1335 compatible = "fsl,ls1028a-ftm-alarm"; 1336 reg = <0x0 0x2810000 0x0 0x10000>; 1337 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1338 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1339 status = "disabled"; 1340 }; 1341 }; 1342 1343}; 1344