1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for NXP LS1028A QDS Board. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11/dts-v1/; 12 13#include "fsl-ls1028a.dtsi" 14 15/ { 16 model = "LS1028A QDS Board"; 17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; 18 19 aliases { 20 crypto = &crypto; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 serial0 = &duart0; 25 serial1 = &duart1; 26 mmc0 = &esdhc; 27 mmc1 = &esdhc1; 28 }; 29 30 chosen { 31 stdout-path = "serial0:115200n8"; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 reg = <0x0 0x80000000 0x1 0x00000000>; 37 }; 38 39 sys_mclk: clock-mclk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <25000000>; 43 }; 44 45 reg_1p8v: regulator-1p8v { 46 compatible = "regulator-fixed"; 47 regulator-name = "1P8V"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 regulator-always-on; 51 }; 52 53 sb_3v3: regulator-sb3v3 { 54 compatible = "regulator-fixed"; 55 regulator-name = "3v3_vbus"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 regulator-boot-on; 59 regulator-always-on; 60 }; 61 62 sound { 63 compatible = "simple-audio-card"; 64 simple-audio-card,format = "i2s"; 65 simple-audio-card,widgets = 66 "Microphone", "Microphone Jack", 67 "Headphone", "Headphone Jack", 68 "Speaker", "Speaker Ext", 69 "Line", "Line In Jack"; 70 simple-audio-card,routing = 71 "MIC_IN", "Microphone Jack", 72 "Microphone Jack", "Mic Bias", 73 "LINE_IN", "Line In Jack", 74 "Headphone Jack", "HP_OUT", 75 "Speaker Ext", "LINE_OUT"; 76 77 simple-audio-card,cpu { 78 sound-dai = <&sai1>; 79 frame-master; 80 bitclock-master; 81 }; 82 83 simple-audio-card,codec { 84 sound-dai = <&sgtl5000>; 85 frame-master; 86 bitclock-master; 87 system-clock-frequency = <25000000>; 88 }; 89 }; 90 91 mdio-mux { 92 compatible = "mdio-mux-multiplexer"; 93 mux-controls = <&mux 0>; 94 mdio-parent-bus = <&enetc_mdio_pf3>; 95 #address-cells=<1>; 96 #size-cells = <0>; 97 98 /* on-board RGMII PHY */ 99 mdio@0 { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 reg = <0>; 103 104 qds_phy1: ethernet-phy@5 { 105 /* Atheros 8035 */ 106 reg = <5>; 107 }; 108 }; 109 }; 110}; 111 112&dspi0 { 113 bus-num = <0>; 114 status = "okay"; 115 116 flash@0 { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 compatible = "jedec,spi-nor"; 120 spi-cpol; 121 spi-cpha; 122 reg = <0>; 123 spi-max-frequency = <10000000>; 124 }; 125 126 flash@1 { 127 #address-cells = <1>; 128 #size-cells = <1>; 129 compatible = "jedec,spi-nor"; 130 spi-cpol; 131 spi-cpha; 132 reg = <1>; 133 spi-max-frequency = <10000000>; 134 }; 135 136 flash@2 { 137 #address-cells = <1>; 138 #size-cells = <1>; 139 compatible = "jedec,spi-nor"; 140 spi-cpol; 141 spi-cpha; 142 reg = <2>; 143 spi-max-frequency = <10000000>; 144 }; 145}; 146 147&dspi1 { 148 bus-num = <1>; 149 status = "okay"; 150 151 flash@0 { 152 #address-cells = <1>; 153 #size-cells = <1>; 154 compatible = "jedec,spi-nor"; 155 spi-cpol; 156 spi-cpha; 157 reg = <0>; 158 spi-max-frequency = <10000000>; 159 }; 160 161 flash@1 { 162 #address-cells = <1>; 163 #size-cells = <1>; 164 compatible = "jedec,spi-nor"; 165 spi-cpol; 166 spi-cpha; 167 reg = <1>; 168 spi-max-frequency = <10000000>; 169 }; 170 171 flash@2 { 172 #address-cells = <1>; 173 #size-cells = <1>; 174 compatible = "jedec,spi-nor"; 175 spi-cpol; 176 spi-cpha; 177 reg = <2>; 178 spi-max-frequency = <10000000>; 179 }; 180}; 181 182&dspi2 { 183 bus-num = <2>; 184 status = "okay"; 185 186 flash@0 { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 compatible = "jedec,spi-nor"; 190 spi-cpol; 191 spi-cpha; 192 reg = <0>; 193 spi-max-frequency = <10000000>; 194 }; 195}; 196 197&duart0 { 198 status = "okay"; 199}; 200 201&duart1 { 202 status = "okay"; 203}; 204 205&esdhc { 206 status = "okay"; 207}; 208 209&esdhc1 { 210 status = "okay"; 211}; 212 213&fspi { 214 status = "okay"; 215 216 mt35xu02g0: flash@0 { 217 compatible = "jedec,spi-nor"; 218 #address-cells = <1>; 219 #size-cells = <1>; 220 spi-max-frequency = <50000000>; 221 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ 222 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ 223 spi-tx-bus-width = <1>; /* 1 SPI Tx line */ 224 reg = <0>; 225 }; 226}; 227 228&i2c0 { 229 status = "okay"; 230 231 i2c-mux@77 { 232 compatible = "nxp,pca9547"; 233 reg = <0x77>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 237 i2c@2 { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 reg = <0x2>; 241 242 current-monitor@40 { 243 compatible = "ti,ina220"; 244 reg = <0x40>; 245 shunt-resistor = <1000>; 246 }; 247 248 current-monitor@41 { 249 compatible = "ti,ina220"; 250 reg = <0x41>; 251 shunt-resistor = <1000>; 252 }; 253 }; 254 255 i2c@3 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0x3>; 259 260 temperature-sensor@4c { 261 compatible = "nxp,sa56004"; 262 reg = <0x4c>; 263 vcc-supply = <&sb_3v3>; 264 }; 265 266 rtc@51 { 267 compatible = "nxp,pcf2129"; 268 reg = <0x51>; 269 }; 270 271 eeprom@56 { 272 compatible = "atmel,24c512"; 273 reg = <0x56>; 274 }; 275 276 eeprom@57 { 277 compatible = "atmel,24c512"; 278 reg = <0x57>; 279 }; 280 }; 281 282 i2c@5 { 283 #address-cells = <1>; 284 #size-cells = <0>; 285 reg = <0x5>; 286 287 sgtl5000: audio-codec@a { 288 #sound-dai-cells = <0>; 289 compatible = "fsl,sgtl5000"; 290 reg = <0xa>; 291 VDDA-supply = <®_1p8v>; 292 VDDIO-supply = <®_1p8v>; 293 clocks = <&sys_mclk>; 294 }; 295 }; 296 }; 297 298 fpga@66 { 299 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c", 300 "simple-mfd"; 301 reg = <0x66>; 302 303 mux: mux-controller { 304 compatible = "reg-mux"; 305 #mux-control-cells = <1>; 306 mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */ 307 }; 308 }; 309 310}; 311 312&enetc_port1 { 313 phy-handle = <&qds_phy1>; 314 phy-connection-type = "rgmii-id"; 315 status = "okay"; 316}; 317 318&lpuart0 { 319 status = "okay"; 320}; 321 322&sai1 { 323 status = "okay"; 324}; 325 326&sata { 327 status = "okay"; 328}; 329