1/* 2 * Device Tree Include file for Freescale Layerscape-1012A family SoC. 3 * 4 * Copyright 2016, Freescale Semiconductor 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPLv2 or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/thermal/thermal.h> 47 48/ { 49 compatible = "fsl,ls1012a"; 50 interrupt-parent = <&gic>; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 54 aliases { 55 crypto = &crypto; 56 rtic_a = &rtic_a; 57 rtic_b = &rtic_b; 58 rtic_c = &rtic_c; 59 rtic_d = &rtic_d; 60 sec_mon = &sec_mon; 61 }; 62 63 cpus { 64 #address-cells = <1>; 65 #size-cells = <0>; 66 67 cpu0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x0>; 71 clocks = <&clockgen 1 0>; 72 #cooling-cells = <2>; 73 }; 74 }; 75 76 sysclk: sysclk { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <100000000>; 80 clock-output-names = "sysclk"; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 86 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 87 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 88 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 89 }; 90 91 pmu { 92 compatible = "arm,armv8-pmuv3"; 93 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 94 }; 95 96 gic: interrupt-controller@1400000 { 97 compatible = "arm,gic-400"; 98 #interrupt-cells = <3>; 99 interrupt-controller; 100 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 101 <0x0 0x1402000 0 0x2000>, /* GICC */ 102 <0x0 0x1404000 0 0x2000>, /* GICH */ 103 <0x0 0x1406000 0 0x2000>; /* GICV */ 104 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; 105 }; 106 107 reboot { 108 compatible = "syscon-reboot"; 109 regmap = <&dcfg>; 110 offset = <0xb0>; 111 mask = <0x02>; 112 }; 113 114 soc { 115 compatible = "simple-bus"; 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges; 119 120 scfg: scfg@1570000 { 121 compatible = "fsl,ls1012a-scfg", "syscon"; 122 reg = <0x0 0x1570000 0x0 0x10000>; 123 big-endian; 124 }; 125 126 crypto: crypto@1700000 { 127 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 128 "fsl,sec-v4.0"; 129 fsl,sec-era = <8>; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 ranges = <0x0 0x00 0x1700000 0x100000>; 133 reg = <0x00 0x1700000 0x0 0x100000>; 134 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 135 136 sec_jr0: jr@10000 { 137 compatible = "fsl,sec-v5.4-job-ring", 138 "fsl,sec-v5.0-job-ring", 139 "fsl,sec-v4.0-job-ring"; 140 reg = <0x10000 0x10000>; 141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 142 }; 143 144 sec_jr1: jr@20000 { 145 compatible = "fsl,sec-v5.4-job-ring", 146 "fsl,sec-v5.0-job-ring", 147 "fsl,sec-v4.0-job-ring"; 148 reg = <0x20000 0x10000>; 149 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 sec_jr2: jr@30000 { 153 compatible = "fsl,sec-v5.4-job-ring", 154 "fsl,sec-v5.0-job-ring", 155 "fsl,sec-v4.0-job-ring"; 156 reg = <0x30000 0x10000>; 157 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 158 }; 159 160 sec_jr3: jr@40000 { 161 compatible = "fsl,sec-v5.4-job-ring", 162 "fsl,sec-v5.0-job-ring", 163 "fsl,sec-v4.0-job-ring"; 164 reg = <0x40000 0x10000>; 165 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 168 rtic@60000 { 169 compatible = "fsl,sec-v5.4-rtic", 170 "fsl,sec-v5.0-rtic", 171 "fsl,sec-v4.0-rtic"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 reg = <0x60000 0x100 0x60e00 0x18>; 175 ranges = <0x0 0x60100 0x500>; 176 177 rtic_a: rtic-a@0 { 178 compatible = "fsl,sec-v5.4-rtic-memory", 179 "fsl,sec-v5.0-rtic-memory", 180 "fsl,sec-v4.0-rtic-memory"; 181 reg = <0x00 0x20 0x100 0x100>; 182 }; 183 184 rtic_b: rtic-b@20 { 185 compatible = "fsl,sec-v5.4-rtic-memory", 186 "fsl,sec-v5.0-rtic-memory", 187 "fsl,sec-v4.0-rtic-memory"; 188 reg = <0x20 0x20 0x200 0x100>; 189 }; 190 191 rtic_c: rtic-c@40 { 192 compatible = "fsl,sec-v5.4-rtic-memory", 193 "fsl,sec-v5.0-rtic-memory", 194 "fsl,sec-v4.0-rtic-memory"; 195 reg = <0x40 0x20 0x300 0x100>; 196 }; 197 198 rtic_d: rtic-d@60 { 199 compatible = "fsl,sec-v5.4-rtic-memory", 200 "fsl,sec-v5.0-rtic-memory", 201 "fsl,sec-v4.0-rtic-memory"; 202 reg = <0x60 0x20 0x400 0x100>; 203 }; 204 }; 205 }; 206 207 sec_mon: sec_mon@1e90000 { 208 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", 209 "fsl,sec-v4.0-mon"; 210 reg = <0x0 0x1e90000 0x0 0x10000>; 211 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 213 }; 214 215 dcfg: dcfg@1ee0000 { 216 compatible = "fsl,ls1012a-dcfg", 217 "syscon"; 218 reg = <0x0 0x1ee0000 0x0 0x10000>; 219 big-endian; 220 }; 221 222 clockgen: clocking@1ee1000 { 223 compatible = "fsl,ls1012a-clockgen"; 224 reg = <0x0 0x1ee1000 0x0 0x1000>; 225 #clock-cells = <2>; 226 clocks = <&sysclk>; 227 }; 228 229 tmu: tmu@1f00000 { 230 compatible = "fsl,qoriq-tmu"; 231 reg = <0x0 0x1f00000 0x0 0x10000>; 232 interrupts = <0 33 0x4>; 233 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 234 fsl,tmu-calibration = <0x00000000 0x00000026 235 0x00000001 0x0000002d 236 0x00000002 0x00000032 237 0x00000003 0x00000039 238 0x00000004 0x0000003f 239 0x00000005 0x00000046 240 0x00000006 0x0000004d 241 0x00000007 0x00000054 242 0x00000008 0x0000005a 243 0x00000009 0x00000061 244 0x0000000a 0x0000006a 245 0x0000000b 0x00000071 246 247 0x00010000 0x00000025 248 0x00010001 0x0000002c 249 0x00010002 0x00000035 250 0x00010003 0x0000003d 251 0x00010004 0x00000045 252 0x00010005 0x0000004e 253 0x00010006 0x00000057 254 0x00010007 0x00000061 255 0x00010008 0x0000006b 256 0x00010009 0x00000076 257 258 0x00020000 0x00000029 259 0x00020001 0x00000033 260 0x00020002 0x0000003d 261 0x00020003 0x00000049 262 0x00020004 0x00000056 263 0x00020005 0x00000061 264 0x00020006 0x0000006d 265 266 0x00030000 0x00000021 267 0x00030001 0x0000002a 268 0x00030002 0x0000003c 269 0x00030003 0x0000004e>; 270 big-endian; 271 #thermal-sensor-cells = <1>; 272 }; 273 274 thermal-zones { 275 cpu_thermal: cpu-thermal { 276 polling-delay-passive = <1000>; 277 polling-delay = <5000>; 278 thermal-sensors = <&tmu 0>; 279 280 trips { 281 cpu_alert: cpu-alert { 282 temperature = <85000>; 283 hysteresis = <2000>; 284 type = "passive"; 285 }; 286 287 cpu_crit: cpu-crit { 288 temperature = <95000>; 289 hysteresis = <2000>; 290 type = "critical"; 291 }; 292 }; 293 294 cooling-maps { 295 map0 { 296 trip = <&cpu_alert>; 297 cooling-device = 298 <&cpu0 THERMAL_NO_LIMIT 299 THERMAL_NO_LIMIT>; 300 }; 301 }; 302 }; 303 }; 304 305 i2c0: i2c@2180000 { 306 compatible = "fsl,vf610-i2c"; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <0x0 0x2180000 0x0 0x10000>; 310 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&clockgen 4 0>; 312 status = "disabled"; 313 }; 314 315 i2c1: i2c@2190000 { 316 compatible = "fsl,vf610-i2c"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <0x0 0x2190000 0x0 0x10000>; 320 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clockgen 4 0>; 322 status = "disabled"; 323 }; 324 325 duart0: serial@21c0500 { 326 compatible = "fsl,ns16550", "ns16550a"; 327 reg = <0x00 0x21c0500 0x0 0x100>; 328 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&clockgen 4 0>; 330 status = "disabled"; 331 }; 332 333 duart1: serial@21c0600 { 334 compatible = "fsl,ns16550", "ns16550a"; 335 reg = <0x00 0x21c0600 0x0 0x100>; 336 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&clockgen 4 0>; 338 status = "disabled"; 339 }; 340 341 gpio0: gpio@2300000 { 342 compatible = "fsl,qoriq-gpio"; 343 reg = <0x0 0x2300000 0x0 0x10000>; 344 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 }; 350 351 gpio1: gpio@2310000 { 352 compatible = "fsl,qoriq-gpio"; 353 reg = <0x0 0x2310000 0x0 0x10000>; 354 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 355 gpio-controller; 356 #gpio-cells = <2>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 wdog0: wdog@2ad0000 { 362 compatible = "fsl,ls1012a-wdt", 363 "fsl,imx21-wdt"; 364 reg = <0x0 0x2ad0000 0x0 0x10000>; 365 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&clockgen 4 0>; 367 big-endian; 368 }; 369 370 sai1: sai@2b50000 { 371 #sound-dai-cells = <0>; 372 compatible = "fsl,vf610-sai"; 373 reg = <0x0 0x2b50000 0x0 0x10000>; 374 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&clockgen 4 3>, <&clockgen 4 3>, 376 <&clockgen 4 3>, <&clockgen 4 3>; 377 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 378 dma-names = "tx", "rx"; 379 dmas = <&edma0 1 47>, 380 <&edma0 1 46>; 381 status = "disabled"; 382 }; 383 384 sai2: sai@2b60000 { 385 #sound-dai-cells = <0>; 386 compatible = "fsl,vf610-sai"; 387 reg = <0x0 0x2b60000 0x0 0x10000>; 388 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clockgen 4 3>, <&clockgen 4 3>, 390 <&clockgen 4 3>, <&clockgen 4 3>; 391 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 392 dma-names = "tx", "rx"; 393 dmas = <&edma0 1 45>, 394 <&edma0 1 44>; 395 status = "disabled"; 396 }; 397 398 edma0: edma@2c00000 { 399 #dma-cells = <2>; 400 compatible = "fsl,vf610-edma"; 401 reg = <0x0 0x2c00000 0x0 0x10000>, 402 <0x0 0x2c10000 0x0 0x10000>, 403 <0x0 0x2c20000 0x0 0x10000>; 404 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, 405 <0 103 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "edma-tx", "edma-err"; 407 dma-channels = <32>; 408 big-endian; 409 clock-names = "dmamux0", "dmamux1"; 410 clocks = <&clockgen 4 3>, 411 <&clockgen 4 3>; 412 }; 413 414 sata: sata@3200000 { 415 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; 416 reg = <0x0 0x3200000 0x0 0x10000>, 417 <0x0 0x20140520 0x0 0x4>; 418 reg-names = "ahci", "sata-ecc"; 419 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clockgen 4 0>; 421 dma-coherent; 422 status = "disabled"; 423 }; 424 }; 425}; 426