1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GS101 SoC 4 * 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 */ 8 9#include <dt-bindings/clock/google,gs101.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "google,gs101"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_gpio_alive; 23 pinctrl1 = &pinctrl_far_alive; 24 pinctrl2 = &pinctrl_gsacore; 25 pinctrl3 = &pinctrl_gsactrl; 26 pinctrl4 = &pinctrl_peric0; 27 pinctrl5 = &pinctrl_peric1; 28 pinctrl6 = &pinctrl_hsi1; 29 pinctrl7 = &pinctrl_hsi2; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu-map { 37 cluster0 { 38 core0 { 39 cpu = <&cpu0>; 40 }; 41 core1 { 42 cpu = <&cpu1>; 43 }; 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 core3 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu4>; 55 }; 56 core1 { 57 cpu = <&cpu5>; 58 }; 59 }; 60 61 cluster2 { 62 core0 { 63 cpu = <&cpu6>; 64 }; 65 core1 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0000>; 75 enable-method = "psci"; 76 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 77 capacity-dmips-mhz = <250>; 78 dynamic-power-coefficient = <70>; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a55"; 84 reg = <0x0100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 87 capacity-dmips-mhz = <250>; 88 dynamic-power-coefficient = <70>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0200>; 95 enable-method = "psci"; 96 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 97 capacity-dmips-mhz = <250>; 98 dynamic-power-coefficient = <70>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0300>; 105 enable-method = "psci"; 106 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 107 capacity-dmips-mhz = <250>; 108 dynamic-power-coefficient = <70>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a76"; 114 reg = <0x0400>; 115 enable-method = "psci"; 116 cpu-idle-states = <&ENYO_CPU_SLEEP>; 117 capacity-dmips-mhz = <620>; 118 dynamic-power-coefficient = <284>; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a76"; 124 reg = <0x0500>; 125 enable-method = "psci"; 126 cpu-idle-states = <&ENYO_CPU_SLEEP>; 127 capacity-dmips-mhz = <620>; 128 dynamic-power-coefficient = <284>; 129 }; 130 131 cpu6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-x1"; 134 reg = <0x0600>; 135 enable-method = "psci"; 136 cpu-idle-states = <&HERA_CPU_SLEEP>; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <650>; 139 }; 140 141 cpu7: cpu@700 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-x1"; 144 reg = <0x0700>; 145 enable-method = "psci"; 146 cpu-idle-states = <&HERA_CPU_SLEEP>; 147 capacity-dmips-mhz = <1024>; 148 dynamic-power-coefficient = <650>; 149 }; 150 151 idle-states { 152 entry-method = "psci"; 153 154 ANANKE_CPU_SLEEP: cpu-ananke-sleep { 155 idle-state-name = "c2"; 156 compatible = "arm,idle-state"; 157 arm,psci-suspend-param = <0x0010000>; 158 entry-latency-us = <70>; 159 exit-latency-us = <160>; 160 min-residency-us = <2000>; 161 }; 162 163 ENYO_CPU_SLEEP: cpu-enyo-sleep { 164 idle-state-name = "c2"; 165 compatible = "arm,idle-state"; 166 arm,psci-suspend-param = <0x0010000>; 167 entry-latency-us = <150>; 168 exit-latency-us = <190>; 169 min-residency-us = <2500>; 170 }; 171 172 HERA_CPU_SLEEP: cpu-hera-sleep { 173 idle-state-name = "c2"; 174 compatible = "arm,idle-state"; 175 arm,psci-suspend-param = <0x0010000>; 176 entry-latency-us = <235>; 177 exit-latency-us = <220>; 178 min-residency-us = <3500>; 179 }; 180 }; 181 }; 182 183 /* ect node is required to be present by bootloader */ 184 ect { 185 }; 186 187 ext_24_5m: clock-1 { 188 compatible = "fixed-clock"; 189 #clock-cells = <0>; 190 clock-output-names = "oscclk"; 191 }; 192 193 ext_200m: clock-2 { 194 compatible = "fixed-clock"; 195 #clock-cells = <0>; 196 clock-output-names = "ext-200m"; 197 }; 198 199 pmu-0 { 200 compatible = "arm,cortex-a55-pmu"; 201 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 202 }; 203 204 pmu-1 { 205 compatible = "arm,cortex-a76-pmu"; 206 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 207 }; 208 209 pmu-2 { 210 compatible = "arm,cortex-x1-pmu"; 211 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 212 }; 213 214 pmu-3 { 215 compatible = "arm,dsu-pmu"; 216 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; 217 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 218 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 219 }; 220 221 psci { 222 compatible = "arm,psci-1.0"; 223 method = "smc"; 224 }; 225 226 reserved_memory: reserved-memory { 227 #address-cells = <2>; 228 #size-cells = <1>; 229 ranges; 230 231 gsa_reserved_protected: gsa@90200000 { 232 reg = <0x0 0x90200000 0x400000>; 233 no-map; 234 }; 235 236 tpu_fw_reserved: tpu-fw@93000000 { 237 reg = <0x0 0x93000000 0x1000000>; 238 no-map; 239 }; 240 241 aoc_reserve: aoc@94000000 { 242 reg = <0x0 0x94000000 0x03000000>; 243 no-map; 244 }; 245 246 abl_reserved: abl@f8800000 { 247 reg = <0x0 0xf8800000 0x02000000>; 248 no-map; 249 }; 250 251 dss_log_reserved: dss-log-reserved@fd3f0000 { 252 reg = <0x0 0xfd3f0000 0x0000e000>; 253 no-map; 254 }; 255 256 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { 257 reg = <0x0 0xfd3fe000 0x00001000>; 258 no-map; 259 }; 260 261 bldr_log_reserved: bldr-log-reserved@fd800000 { 262 reg = <0x0 0xfd800000 0x00100000>; 263 no-map; 264 }; 265 266 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { 267 reg = <0x0 0xfd900000 0x00002000>; 268 no-map; 269 }; 270 }; 271 272 soc: soc@0 { 273 compatible = "simple-bus"; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 ranges = <0x0 0x0 0x0 0x40000000>; 277 278 cmu_misc: clock-controller@10010000 { 279 compatible = "google,gs101-cmu-misc"; 280 reg = <0x10010000 0x8000>; 281 #clock-cells = <1>; 282 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, 283 <&cmu_top CLK_DOUT_CMU_MISC_SSS>; 284 clock-names = "bus", "sss"; 285 }; 286 287 timer@10050000 { 288 compatible = "google,gs101-mct", 289 "samsung,exynos4210-mct"; 290 reg = <0x10050000 0x800>; 291 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, 292 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, 293 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, 294 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, 295 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, 296 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, 297 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, 298 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, 299 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, 300 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, 301 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, 302 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; 303 clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; 304 clock-names = "fin_pll", "mct"; 305 }; 306 307 watchdog_cl0: watchdog@10060000 { 308 compatible = "google,gs101-wdt"; 309 reg = <0x10060000 0x100>; 310 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; 311 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, 312 <&ext_24_5m>; 313 clock-names = "watchdog", "watchdog_src"; 314 samsung,syscon-phandle = <&pmu_system_controller>; 315 samsung,cluster-index = <0>; 316 status = "disabled"; 317 }; 318 319 watchdog_cl1: watchdog@10070000 { 320 compatible = "google,gs101-wdt"; 321 reg = <0x10070000 0x100>; 322 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; 323 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, 324 <&ext_24_5m>; 325 clock-names = "watchdog", "watchdog_src"; 326 samsung,syscon-phandle = <&pmu_system_controller>; 327 samsung,cluster-index = <1>; 328 status = "disabled"; 329 }; 330 331 gic: interrupt-controller@10400000 { 332 compatible = "arm,gic-v3"; 333 #interrupt-cells = <4>; 334 interrupt-controller; 335 reg = <0x10400000 0x10000>, /* GICD */ 336 <0x10440000 0x100000>;/* GICR * 8 */ 337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 338 339 ppi-partitions { 340 ppi_cluster0: interrupt-partition-0 { 341 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 342 }; 343 344 ppi_cluster1: interrupt-partition-1 { 345 affinity = <&cpu4 &cpu5>; 346 }; 347 348 ppi_cluster2: interrupt-partition-2 { 349 affinity = <&cpu6 &cpu7>; 350 }; 351 }; 352 }; 353 354 cmu_peric0: clock-controller@10800000 { 355 compatible = "google,gs101-cmu-peric0"; 356 reg = <0x10800000 0x4000>; 357 #clock-cells = <1>; 358 clocks = <&ext_24_5m>, 359 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 360 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 361 clock-names = "oscclk", "bus", "ip"; 362 }; 363 364 sysreg_peric0: syscon@10820000 { 365 compatible = "google,gs101-peric0-sysreg", "syscon"; 366 reg = <0x10820000 0x10000>; 367 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 368 }; 369 370 pinctrl_peric0: pinctrl@10840000 { 371 compatible = "google,gs101-pinctrl"; 372 reg = <0x10840000 0x00001000>; 373 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; 374 clock-names = "pclk"; 375 interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; 376 }; 377 378 usi1: usi@109000c0 { 379 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 380 reg = <0x109000c0 0x20>; 381 ranges; 382 #address-cells = <1>; 383 #size-cells = <1>; 384 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 385 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 386 clock-names = "pclk", "ipclk"; 387 samsung,sysreg = <&sysreg_peric0 0x1000>; 388 status = "disabled"; 389 390 hsi2c_1: i2c@10900000 { 391 compatible = "google,gs101-hsi2c", 392 "samsung,exynosautov9-hsi2c"; 393 reg = <0x10900000 0xc0>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, 397 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; 398 clock-names = "hsi2c", "hsi2c_pclk"; 399 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 400 pinctrl-0 = <&hsi2c1_bus>; 401 pinctrl-names = "default"; 402 status = "disabled"; 403 }; 404 405 serial_1: serial@10900000 { 406 compatible = "google,gs101-uart"; 407 reg = <0x10900000 0xc0>; 408 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 409 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 410 clock-names = "uart", "clk_uart_baud0"; 411 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 412 pinctrl-0 = <&uart1_bus_single>; 413 pinctrl-names = "default"; 414 samsung,uart-fifosize = <64>; 415 status = "disabled"; 416 }; 417 418 spi_1: spi@10900000 { 419 compatible = "google,gs101-spi"; 420 reg = <0x10900000 0x30>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 424 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 425 clock-names = "spi", "spi_busclk0"; 426 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 427 pinctrl-0 = <&spi1_bus>; 428 pinctrl-names = "default"; 429 status = "disabled"; 430 }; 431 }; 432 433 usi2: usi@109100c0 { 434 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 435 reg = <0x109100c0 0x20>; 436 ranges; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 440 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 441 clock-names = "pclk", "ipclk"; 442 samsung,sysreg = <&sysreg_peric0 0x1004>; 443 status = "disabled"; 444 445 hsi2c_2: i2c@10910000 { 446 compatible = "google,gs101-hsi2c", 447 "samsung,exynosautov9-hsi2c"; 448 reg = <0x10910000 0xc0>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, 452 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; 453 clock-names = "hsi2c", "hsi2c_pclk"; 454 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 455 pinctrl-0 = <&hsi2c2_bus>; 456 pinctrl-names = "default"; 457 status = "disabled"; 458 }; 459 460 serial_2: serial@10910000 { 461 compatible = "google,gs101-uart"; 462 reg = <0x10910000 0xc0>; 463 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 464 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 465 clock-names = "uart", "clk_uart_baud0"; 466 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 467 pinctrl-0 = <&uart2_bus_single>; 468 pinctrl-names = "default"; 469 samsung,uart-fifosize = <64>; 470 status = "disabled"; 471 }; 472 473 spi_2: spi@10910000 { 474 compatible = "google,gs101-spi"; 475 reg = <0x10910000 0x30>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 479 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 480 clock-names = "spi", "spi_busclk0"; 481 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 482 pinctrl-0 = <&spi2_bus>; 483 pinctrl-names = "default"; 484 status = "disabled"; 485 }; 486 }; 487 488 usi3: usi@109200c0 { 489 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 490 reg = <0x109200c0 0x20>; 491 ranges; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 495 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 496 clock-names = "pclk", "ipclk"; 497 samsung,sysreg = <&sysreg_peric0 0x1008>; 498 status = "disabled"; 499 500 hsi2c_3: i2c@10920000 { 501 compatible = "google,gs101-hsi2c", 502 "samsung,exynosautov9-hsi2c"; 503 reg = <0x10920000 0xc0>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, 507 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; 508 clock-names = "hsi2c", "hsi2c_pclk"; 509 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 510 pinctrl-0 = <&hsi2c3_bus>; 511 pinctrl-names = "default"; 512 status = "disabled"; 513 }; 514 515 serial_3: serial@10920000 { 516 compatible = "google,gs101-uart"; 517 reg = <0x10920000 0xc0>; 518 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 519 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 520 clock-names = "uart", "clk_uart_baud0"; 521 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 522 pinctrl-0 = <&uart3_bus_single>; 523 pinctrl-names = "default"; 524 samsung,uart-fifosize = <64>; 525 status = "disabled"; 526 }; 527 528 spi_3: spi@10920000 { 529 compatible = "google,gs101-spi"; 530 reg = <0x10920000 0x30>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 534 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 535 clock-names = "spi", "spi_busclk0"; 536 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 537 pinctrl-0 = <&spi3_bus>; 538 pinctrl-names = "default"; 539 status = "disabled"; 540 }; 541 }; 542 543 usi4: usi@109300c0 { 544 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 545 reg = <0x109300c0 0x20>; 546 ranges; 547 #address-cells = <1>; 548 #size-cells = <1>; 549 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 550 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 551 clock-names = "pclk", "ipclk"; 552 samsung,sysreg = <&sysreg_peric0 0x100c>; 553 status = "disabled"; 554 555 hsi2c_4: i2c@10930000 { 556 compatible = "google,gs101-hsi2c", 557 "samsung,exynosautov9-hsi2c"; 558 reg = <0x10930000 0xc0>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, 562 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; 563 clock-names = "hsi2c", "hsi2c_pclk"; 564 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 565 pinctrl-0 = <&hsi2c4_bus>; 566 pinctrl-names = "default"; 567 status = "disabled"; 568 }; 569 570 serial_4: serial@10930000 { 571 compatible = "google,gs101-uart"; 572 reg = <0x10930000 0xc0>; 573 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 574 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 575 clock-names = "uart", "clk_uart_baud0"; 576 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 577 pinctrl-0 = <&uart4_bus_single>; 578 pinctrl-names = "default"; 579 samsung,uart-fifosize = <64>; 580 status = "disabled"; 581 }; 582 583 spi_4: spi@10930000 { 584 compatible = "google,gs101-spi"; 585 reg = <0x10930000 0x30>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 589 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 590 clock-names = "spi", "spi_busclk0"; 591 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 592 pinctrl-0 = <&spi4_bus>; 593 pinctrl-names = "default"; 594 status = "disabled"; 595 }; 596 }; 597 598 usi5: usi@109400c0 { 599 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 600 reg = <0x109400c0 0x20>; 601 ranges; 602 #address-cells = <1>; 603 #size-cells = <1>; 604 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 605 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 606 clock-names = "pclk", "ipclk"; 607 samsung,sysreg = <&sysreg_peric0 0x1010>; 608 status = "disabled"; 609 610 hsi2c_5: i2c@10940000 { 611 compatible = "google,gs101-hsi2c", 612 "samsung,exynosautov9-hsi2c"; 613 reg = <0x10940000 0xc0>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, 617 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; 618 clock-names = "hsi2c", "hsi2c_pclk"; 619 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 620 pinctrl-0 = <&hsi2c5_bus>; 621 pinctrl-names = "default"; 622 status = "disabled"; 623 }; 624 625 serial_5: serial@10940000 { 626 compatible = "google,gs101-uart"; 627 reg = <0x10940000 0xc0>; 628 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 629 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 630 clock-names = "uart", "clk_uart_baud0"; 631 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 632 pinctrl-0 = <&uart5_bus_single>; 633 pinctrl-names = "default"; 634 samsung,uart-fifosize = <64>; 635 status = "disabled"; 636 }; 637 638 spi_5: spi@10940000 { 639 compatible = "google,gs101-spi"; 640 reg = <0x10940000 0x30>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 644 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 645 clock-names = "spi", "spi_busclk0"; 646 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 647 pinctrl-0 = <&spi5_bus>; 648 pinctrl-names = "default"; 649 status = "disabled"; 650 }; 651 }; 652 653 usi6: usi@109500c0 { 654 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 655 reg = <0x109500c0 0x20>; 656 ranges; 657 #address-cells = <1>; 658 #size-cells = <1>; 659 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 660 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 661 clock-names = "pclk", "ipclk"; 662 samsung,sysreg = <&sysreg_peric0 0x1014>; 663 status = "disabled"; 664 665 hsi2c_6: i2c@10950000 { 666 compatible = "google,gs101-hsi2c", 667 "samsung,exynosautov9-hsi2c"; 668 reg = <0x10950000 0xc0>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, 672 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; 673 clock-names = "hsi2c", "hsi2c_pclk"; 674 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 675 pinctrl-0 = <&hsi2c6_bus>; 676 pinctrl-names = "default"; 677 status = "disabled"; 678 }; 679 680 serial_6: serial@10950000 { 681 compatible = "google,gs101-uart"; 682 reg = <0x10950000 0xc0>; 683 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 684 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 685 clock-names = "uart", "clk_uart_baud0"; 686 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 687 pinctrl-0 = <&uart6_bus_single>; 688 pinctrl-names = "default"; 689 samsung,uart-fifosize = <64>; 690 status = "disabled"; 691 }; 692 693 spi_6: spi@10950000 { 694 compatible = "google,gs101-spi"; 695 reg = <0x10950000 0x30>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 699 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 700 clock-names = "spi", "spi_busclk0"; 701 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 702 pinctrl-0 = <&spi6_bus>; 703 pinctrl-names = "default"; 704 status = "disabled"; 705 }; 706 }; 707 708 usi7: usi@109600c0 { 709 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 710 reg = <0x109600c0 0x20>; 711 ranges; 712 #address-cells = <1>; 713 #size-cells = <1>; 714 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 715 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 716 clock-names = "pclk", "ipclk"; 717 samsung,sysreg = <&sysreg_peric0 0x1018>; 718 status = "disabled"; 719 720 hsi2c_7: i2c@10960000 { 721 compatible = "google,gs101-hsi2c", 722 "samsung,exynosautov9-hsi2c"; 723 reg = <0x10960000 0xc0>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, 727 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; 728 clock-names = "hsi2c", "hsi2c_pclk"; 729 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 730 pinctrl-0 = <&hsi2c7_bus>; 731 pinctrl-names = "default"; 732 status = "disabled"; 733 }; 734 735 serial_7: serial@10960000 { 736 compatible = "google,gs101-uart"; 737 reg = <0x10960000 0xc0>; 738 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 739 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 740 clock-names = "uart", "clk_uart_baud0"; 741 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 742 pinctrl-0 = <&uart7_bus_single>; 743 pinctrl-names = "default"; 744 samsung,uart-fifosize = <64>; 745 status = "disabled"; 746 }; 747 748 spi_7: spi@10960000 { 749 compatible = "google,gs101-spi"; 750 reg = <0x10960000 0x30>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 754 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 755 clock-names = "spi", "spi_busclk0"; 756 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 757 pinctrl-0 = <&spi7_bus>; 758 pinctrl-names = "default"; 759 status = "disabled"; 760 }; 761 }; 762 763 usi8: usi@109700c0 { 764 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 765 reg = <0x109700c0 0x20>; 766 ranges; 767 #address-cells = <1>; 768 #size-cells = <1>; 769 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 770 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 771 clock-names = "pclk", "ipclk"; 772 samsung,sysreg = <&sysreg_peric0 0x101c>; 773 status = "disabled"; 774 775 hsi2c_8: i2c@10970000 { 776 compatible = "google,gs101-hsi2c", 777 "samsung,exynosautov9-hsi2c"; 778 reg = <0x10970000 0xc0>; 779 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, 783 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; 784 clock-names = "hsi2c", "hsi2c_pclk"; 785 pinctrl-0 = <&hsi2c8_bus>; 786 pinctrl-names = "default"; 787 status = "disabled"; 788 }; 789 790 serial_8: serial@10970000 { 791 compatible = "google,gs101-uart"; 792 reg = <0x10970000 0xc0>; 793 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 794 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 795 clock-names = "uart", "clk_uart_baud0"; 796 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 797 pinctrl-0 = <&uart8_bus_single>; 798 pinctrl-names = "default"; 799 samsung,uart-fifosize = <64>; 800 status = "disabled"; 801 }; 802 803 spi_8: spi@10970000 { 804 compatible = "google,gs101-spi"; 805 reg = <0x10970000 0x30>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 809 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 810 clock-names = "spi", "spi_busclk0"; 811 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 812 pinctrl-0 = <&spi8_bus>; 813 pinctrl-names = "default"; 814 status = "disabled"; 815 }; 816 }; 817 818 usi_uart: usi@10a000c0 { 819 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 820 reg = <0x10a000c0 0x20>; 821 ranges; 822 #address-cells = <1>; 823 #size-cells = <1>; 824 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 825 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 826 clock-names = "pclk", "ipclk"; 827 samsung,sysreg = <&sysreg_peric0 0x1020>; 828 samsung,mode = <USI_V2_UART>; 829 status = "disabled"; 830 831 serial_0: serial@10a00000 { 832 compatible = "google,gs101-uart"; 833 reg = <0x10a00000 0xc0>; 834 interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; 835 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 836 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 837 clock-names = "uart", "clk_uart_baud0"; 838 pinctrl-0 = <&uart0_bus>; 839 pinctrl-names = "default"; 840 samsung,uart-fifosize = <256>; 841 status = "disabled"; 842 }; 843 }; 844 845 usi14: usi@10a200c0 { 846 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 847 reg = <0x10a200c0 0x20>; 848 ranges; 849 #address-cells = <1>; 850 #size-cells = <1>; 851 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 852 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 853 clock-names = "pclk", "ipclk"; 854 samsung,sysreg = <&sysreg_peric0 0x1028>; 855 status = "disabled"; 856 857 hsi2c_14: i2c@10a20000 { 858 compatible = "google,gs101-hsi2c", 859 "samsung,exynosautov9-hsi2c"; 860 reg = <0x10a20000 0xc0>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, 864 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; 865 clock-names = "hsi2c", "hsi2c_pclk"; 866 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 867 pinctrl-0 = <&hsi2c14_bus>; 868 pinctrl-names = "default"; 869 status = "disabled"; 870 }; 871 872 serial_14: serial@10a20000 { 873 compatible = "google,gs101-uart"; 874 reg = <0x10a20000 0xc0>; 875 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 876 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 877 clock-names = "uart", "clk_uart_baud0"; 878 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 879 pinctrl-0 = <&uart14_bus_single>; 880 pinctrl-names = "default"; 881 samsung,uart-fifosize = <64>; 882 status = "disabled"; 883 }; 884 885 spi_14: spi@10a20000 { 886 compatible = "google,gs101-spi"; 887 reg = <0x10a20000 0x30>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 891 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 892 clock-names = "spi", "spi_busclk0"; 893 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 894 pinctrl-0 = <&spi14_bus>; 895 pinctrl-names = "default"; 896 status = "disabled"; 897 }; 898 }; 899 900 cmu_peric1: clock-controller@10c00000 { 901 compatible = "google,gs101-cmu-peric1"; 902 reg = <0x10c00000 0x4000>; 903 #clock-cells = <1>; 904 clocks = <&ext_24_5m>, 905 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 906 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 907 clock-names = "oscclk", "bus", "ip"; 908 }; 909 910 sysreg_peric1: syscon@10c20000 { 911 compatible = "google,gs101-peric1-sysreg", "syscon"; 912 reg = <0x10c20000 0x10000>; 913 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 914 }; 915 916 pinctrl_peric1: pinctrl@10c40000 { 917 compatible = "google,gs101-pinctrl"; 918 reg = <0x10c40000 0x00001000>; 919 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; 920 clock-names = "pclk"; 921 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 922 }; 923 924 usi0: usi@10d100c0 { 925 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 926 reg = <0x10d100c0 0x20>; 927 ranges; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 931 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 932 clock-names = "pclk", "ipclk"; 933 samsung,sysreg = <&sysreg_peric1 0x1000>; 934 status = "disabled"; 935 936 hsi2c_0: i2c@10d10000 { 937 compatible = "google,gs101-hsi2c", 938 "samsung,exynosautov9-hsi2c"; 939 reg = <0x10d10000 0xc0>; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, 943 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; 944 clock-names = "hsi2c", "hsi2c_pclk"; 945 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 946 pinctrl-0 = <&hsi2c0_bus>; 947 pinctrl-names = "default"; 948 status = "disabled"; 949 }; 950 951 serial_usi0: serial@10d10000 { 952 compatible = "google,gs101-uart"; 953 reg = <0x10d10000 0xc0>; 954 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 955 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 956 clock-names = "uart", "clk_uart_baud0"; 957 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 958 pinctrl-0 = <&uart0_bus_single>; 959 pinctrl-names = "default"; 960 samsung,uart-fifosize = <64>; 961 status = "disabled"; 962 }; 963 964 spi_0: spi@10d10000 { 965 compatible = "google,gs101-spi"; 966 reg = <0x10d10000 0x30>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 970 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 971 clock-names = "spi", "spi_busclk0"; 972 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 973 pinctrl-0 = <&spi0_bus>; 974 pinctrl-names = "default"; 975 status = "disabled"; 976 }; 977 }; 978 979 usi9: usi@10d200c0 { 980 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 981 reg = <0x10d200c0 0x20>; 982 ranges; 983 #address-cells = <1>; 984 #size-cells = <1>; 985 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 986 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 987 clock-names = "pclk", "ipclk"; 988 samsung,sysreg = <&sysreg_peric1 0x1004>; 989 status = "disabled"; 990 991 hsi2c_9: i2c@10d20000 { 992 compatible = "google,gs101-hsi2c", 993 "samsung,exynosautov9-hsi2c"; 994 reg = <0x10d20000 0xc0>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, 998 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; 999 clock-names = "hsi2c", "hsi2c_pclk"; 1000 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1001 pinctrl-0 = <&hsi2c9_bus>; 1002 pinctrl-names = "default"; 1003 status = "disabled"; 1004 }; 1005 1006 serial_9: serial@10d20000 { 1007 compatible = "google,gs101-uart"; 1008 reg = <0x10d20000 0xc0>; 1009 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1010 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1011 clock-names = "uart", "clk_uart_baud0"; 1012 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1013 pinctrl-0 = <&uart9_bus_single>; 1014 pinctrl-names = "default"; 1015 samsung,uart-fifosize = <64>; 1016 status = "disabled"; 1017 }; 1018 1019 spi_9: spi@10d20000 { 1020 compatible = "google,gs101-spi"; 1021 reg = <0x10d20000 0x30>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1025 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1026 clock-names = "spi", "spi_busclk0"; 1027 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1028 pinctrl-0 = <&spi9_bus>; 1029 pinctrl-names = "default"; 1030 status = "disabled"; 1031 }; 1032 }; 1033 1034 usi10: usi@10d300c0 { 1035 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1036 reg = <0x10d300c0 0x20>; 1037 ranges; 1038 #address-cells = <1>; 1039 #size-cells = <1>; 1040 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1041 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1042 clock-names = "pclk", "ipclk"; 1043 samsung,sysreg = <&sysreg_peric1 0x1008>; 1044 status = "disabled"; 1045 1046 hsi2c_10: i2c@10d30000 { 1047 compatible = "google,gs101-hsi2c", 1048 "samsung,exynosautov9-hsi2c"; 1049 reg = <0x10d30000 0xc0>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, 1053 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; 1054 clock-names = "hsi2c", "hsi2c_pclk"; 1055 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1056 pinctrl-0 = <&hsi2c10_bus>; 1057 pinctrl-names = "default"; 1058 status = "disabled"; 1059 }; 1060 1061 serial_10: serial@10d30000 { 1062 compatible = "google,gs101-uart"; 1063 reg = <0x10d30000 0xc0>; 1064 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1065 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1066 clock-names = "uart", "clk_uart_baud0"; 1067 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1068 pinctrl-0 = <&uart10_bus_single>; 1069 pinctrl-names = "default"; 1070 samsung,uart-fifosize = <64>; 1071 status = "disabled"; 1072 }; 1073 1074 spi_10: spi@10d30000 { 1075 compatible = "google,gs101-spi"; 1076 reg = <0x10d30000 0x30>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1080 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1081 clock-names = "spi", "spi_busclk0"; 1082 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1083 pinctrl-0 = <&spi10_bus>; 1084 pinctrl-names = "default"; 1085 status = "disabled"; 1086 }; 1087 }; 1088 1089 usi11: usi@10d400c0 { 1090 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1091 reg = <0x10d400c0 0x20>; 1092 ranges; 1093 #address-cells = <1>; 1094 #size-cells = <1>; 1095 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1096 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1097 clock-names = "pclk", "ipclk"; 1098 samsung,sysreg = <&sysreg_peric1 0x100c>; 1099 status = "disabled"; 1100 1101 hsi2c_11: i2c@10d40000 { 1102 compatible = "google,gs101-hsi2c", 1103 "samsung,exynosautov9-hsi2c"; 1104 reg = <0x10d40000 0xc0>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, 1108 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; 1109 clock-names = "hsi2c", "hsi2c_pclk"; 1110 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1111 pinctrl-0 = <&hsi2c11_bus>; 1112 pinctrl-names = "default"; 1113 status = "disabled"; 1114 }; 1115 1116 serial_11: serial@10d40000 { 1117 compatible = "google,gs101-uart"; 1118 reg = <0x10d40000 0xc0>; 1119 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1120 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1121 clock-names = "uart", "clk_uart_baud0"; 1122 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1123 pinctrl-0 = <&uart11_bus_single>; 1124 pinctrl-names = "default"; 1125 samsung,uart-fifosize = <64>; 1126 status = "disabled"; 1127 }; 1128 1129 spi_11: spi@10d40000 { 1130 compatible = "google,gs101-spi"; 1131 reg = <0x10d40000 0x30>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1135 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1136 clock-names = "spi", "spi_busclk0"; 1137 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1138 pinctrl-0 = <&spi11_bus>; 1139 pinctrl-names = "default"; 1140 status = "disabled"; 1141 }; 1142 }; 1143 1144 usi12: usi@10d500c0 { 1145 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1146 reg = <0x10d500c0 0x20>; 1147 ranges; 1148 #address-cells = <1>; 1149 #size-cells = <1>; 1150 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1151 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1152 clock-names = "pclk", "ipclk"; 1153 samsung,sysreg = <&sysreg_peric1 0x1010>; 1154 status = "disabled"; 1155 1156 hsi2c_12: i2c@10d50000 { 1157 compatible = "google,gs101-hsi2c", 1158 "samsung,exynosautov9-hsi2c"; 1159 reg = <0x10d50000 0xc0>; 1160 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, 1164 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; 1165 clock-names = "hsi2c", "hsi2c_pclk"; 1166 pinctrl-0 = <&hsi2c12_bus>; 1167 pinctrl-names = "default"; 1168 status = "disabled"; 1169 }; 1170 1171 serial_12: serial@10d50000 { 1172 compatible = "google,gs101-uart"; 1173 reg = <0x10d50000 0xc0>; 1174 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1175 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1176 clock-names = "uart", "clk_uart_baud0"; 1177 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1178 pinctrl-0 = <&uart12_bus_single>; 1179 pinctrl-names = "default"; 1180 samsung,uart-fifosize = <64>; 1181 status = "disabled"; 1182 }; 1183 1184 spi_12: spi@10d50000 { 1185 compatible = "google,gs101-spi"; 1186 reg = <0x10d50000 0x30>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1190 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1191 clock-names = "spi", "spi_busclk0"; 1192 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1193 pinctrl-0 = <&spi12_bus>; 1194 pinctrl-names = "default"; 1195 status = "disabled"; 1196 }; 1197 }; 1198 1199 usi13: usi@10d600c0 { 1200 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1201 reg = <0x10d600c0 0x20>; 1202 ranges; 1203 #address-cells = <1>; 1204 #size-cells = <1>; 1205 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1206 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1207 clock-names = "pclk", "ipclk"; 1208 samsung,sysreg = <&sysreg_peric1 0x1014>; 1209 status = "disabled"; 1210 1211 hsi2c_13: i2c@10d60000 { 1212 compatible = "google,gs101-hsi2c", 1213 "samsung,exynosautov9-hsi2c"; 1214 reg = <0x10d60000 0xc0>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, 1218 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; 1219 clock-names = "hsi2c", "hsi2c_pclk"; 1220 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1221 pinctrl-0 = <&hsi2c13_bus>; 1222 pinctrl-names = "default"; 1223 status = "disabled"; 1224 }; 1225 1226 serial_13: serial@10d60000 { 1227 compatible = "google,gs101-uart"; 1228 reg = <0x10d60000 0xc0>; 1229 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1230 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1231 clock-names = "uart", "clk_uart_baud0"; 1232 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1233 pinctrl-0 = <&uart13_bus_single>; 1234 pinctrl-names = "default"; 1235 samsung,uart-fifosize = <64>; 1236 status = "disabled"; 1237 }; 1238 1239 spi_13: spi@10d60000 { 1240 compatible = "google,gs101-spi"; 1241 reg = <0x10d60000 0x30>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1245 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1246 clock-names = "spi", "spi_busclk0"; 1247 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1248 pinctrl-0 = <&spi13_bus>; 1249 pinctrl-names = "default"; 1250 status = "disabled"; 1251 }; 1252 }; 1253 1254 cmu_hsi0: clock-controller@11000000 { 1255 compatible = "google,gs101-cmu-hsi0"; 1256 reg = <0x11000000 0x4000>; 1257 #clock-cells = <1>; 1258 1259 clocks = <&ext_24_5m>, 1260 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, 1261 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, 1262 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, 1263 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; 1264 clock-names = "oscclk", "bus", "dpgtc", "usb31drd", 1265 "usbdpdbg"; 1266 }; 1267 1268 usbdrd31_phy: phy@11100000 { 1269 compatible = "google,gs101-usb31drd-phy"; 1270 reg = <0x11100000 0x0100>, 1271 <0x110f0000 0x0800>, 1272 <0x110e0000 0x2800>; 1273 reg-names = "phy", "pcs", "pma"; 1274 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, 1275 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, 1276 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, 1277 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, 1278 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; 1279 clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; 1280 samsung,pmu-syscon = <&pmu_system_controller>; 1281 #phy-cells = <1>; 1282 status = "disabled"; 1283 }; 1284 1285 usbdrd31: usb@11110000 { 1286 compatible = "google,gs101-dwusb3"; 1287 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, 1288 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, 1289 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, 1290 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; 1291 clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; 1292 #address-cells = <1>; 1293 #size-cells = <1>; 1294 ranges = <0x0 0x11110000 0x10000>; 1295 status = "disabled"; 1296 1297 usbdrd31_dwc3: usb@0 { 1298 compatible = "snps,dwc3"; 1299 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; 1300 clock-names = "ref"; 1301 reg = <0x0 0x10000>; 1302 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1303 phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; 1304 phy-names = "usb2-phy", "usb3-phy"; 1305 status = "disabled"; 1306 }; 1307 }; 1308 1309 pinctrl_hsi1: pinctrl@11840000 { 1310 compatible = "google,gs101-pinctrl"; 1311 reg = <0x11840000 0x00001000>; 1312 /* TODO: update once support for this CMU exists */ 1313 clocks = <0>; 1314 clock-names = "pclk"; 1315 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1316 }; 1317 1318 cmu_hsi2: clock-controller@14400000 { 1319 compatible = "google,gs101-cmu-hsi2"; 1320 reg = <0x14400000 0x4000>; 1321 #clock-cells = <1>; 1322 clocks = <&ext_24_5m>, 1323 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, 1324 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, 1325 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, 1326 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; 1327 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; 1328 }; 1329 1330 sysreg_hsi2: syscon@14420000 { 1331 compatible = "google,gs101-hsi2-sysreg", "syscon"; 1332 reg = <0x14420000 0x10000>; 1333 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1334 }; 1335 1336 pinctrl_hsi2: pinctrl@14440000 { 1337 compatible = "google,gs101-pinctrl"; 1338 reg = <0x14440000 0x00001000>; 1339 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; 1340 clock-names = "pclk"; 1341 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 1342 }; 1343 1344 ufs_0: ufs@14700000 { 1345 compatible = "google,gs101-ufs"; 1346 reg = <0x14700000 0x200>, 1347 <0x14701100 0x200>, 1348 <0x14780000 0xa000>, 1349 <0x14600000 0x100>; 1350 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1351 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1352 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, 1353 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, 1354 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, 1355 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, 1356 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, 1357 <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1358 clock-names = "core_clk", "sclk_unipro_main", "fmp", 1359 "aclk", "pclk", "sysreg"; 1360 freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; 1361 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1362 pinctrl-names = "default"; 1363 phys = <&ufs_0_phy>; 1364 phy-names = "ufs-phy"; 1365 samsung,sysreg = <&sysreg_hsi2 0x710>; 1366 status = "disabled"; 1367 }; 1368 1369 ufs_0_phy: phy@14704000 { 1370 compatible = "google,gs101-ufs-phy"; 1371 reg = <0x14704000 0x3000>; 1372 reg-names = "phy-pma"; 1373 samsung,pmu-syscon = <&pmu_system_controller>; 1374 #phy-cells = <0>; 1375 clocks = <&ext_24_5m>; 1376 clock-names = "ref_clk"; 1377 status = "disabled"; 1378 }; 1379 1380 cmu_apm: clock-controller@17400000 { 1381 compatible = "google,gs101-cmu-apm"; 1382 reg = <0x17400000 0x8000>; 1383 #clock-cells = <1>; 1384 1385 clocks = <&ext_24_5m>; 1386 clock-names = "oscclk"; 1387 }; 1388 1389 sysreg_apm: syscon@174204e0 { 1390 compatible = "google,gs101-apm-sysreg", "syscon"; 1391 reg = <0x174204e0 0x1000>; 1392 }; 1393 1394 pmu_system_controller: system-controller@17460000 { 1395 compatible = "google,gs101-pmu", "syscon"; 1396 reg = <0x17460000 0x10000>; 1397 }; 1398 1399 pinctrl_gpio_alive: pinctrl@174d0000 { 1400 compatible = "google,gs101-pinctrl"; 1401 reg = <0x174d0000 0x00001000>; 1402 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; 1403 clock-names = "pclk"; 1404 1405 wakeup-interrupt-controller { 1406 compatible = "google,gs101-wakeup-eint", 1407 "samsung,exynos850-wakeup-eint", 1408 "samsung,exynos7-wakeup-eint"; 1409 }; 1410 }; 1411 1412 pinctrl_far_alive: pinctrl@174e0000 { 1413 compatible = "google,gs101-pinctrl"; 1414 reg = <0x174e0000 0x00001000>; 1415 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; 1416 clock-names = "pclk"; 1417 1418 wakeup-interrupt-controller { 1419 compatible = "google,gs101-wakeup-eint", 1420 "samsung,exynos850-wakeup-eint", 1421 "samsung,exynos7-wakeup-eint"; 1422 }; 1423 }; 1424 1425 pinctrl_gsactrl: pinctrl@17940000 { 1426 compatible = "google,gs101-pinctrl"; 1427 reg = <0x17940000 0x00001000>; 1428 /* TODO: update once support for this CMU exists */ 1429 clocks = <0>; 1430 clock-names = "pclk"; 1431 }; 1432 1433 pinctrl_gsacore: pinctrl@17a80000 { 1434 compatible = "google,gs101-pinctrl"; 1435 reg = <0x17a80000 0x00001000>; 1436 /* TODO: update once support for this CMU exists */ 1437 clocks = <0>; 1438 clock-names = "pclk"; 1439 }; 1440 1441 cmu_top: clock-controller@1e080000 { 1442 compatible = "google,gs101-cmu-top"; 1443 reg = <0x1e080000 0x8000>; 1444 #clock-cells = <1>; 1445 1446 clocks = <&ext_24_5m>; 1447 clock-names = "oscclk"; 1448 }; 1449 }; 1450 1451 timer { 1452 compatible = "arm,armv8-timer"; 1453 interrupts = 1454 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1455 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1456 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1457 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 1458 }; 1459}; 1460 1461#include "gs101-pinctrl.dtsi" 1462