1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GS101 SoC 4 * 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 */ 8 9#include <dt-bindings/clock/google,gs101.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "google,gs101"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_gpio_alive; 23 pinctrl1 = &pinctrl_far_alive; 24 pinctrl2 = &pinctrl_gsacore; 25 pinctrl3 = &pinctrl_gsactrl; 26 pinctrl4 = &pinctrl_peric0; 27 pinctrl5 = &pinctrl_peric1; 28 pinctrl6 = &pinctrl_hsi1; 29 pinctrl7 = &pinctrl_hsi2; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu-map { 37 cluster0 { 38 core0 { 39 cpu = <&cpu0>; 40 }; 41 core1 { 42 cpu = <&cpu1>; 43 }; 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 core3 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu4>; 55 }; 56 core1 { 57 cpu = <&cpu5>; 58 }; 59 }; 60 61 cluster2 { 62 core0 { 63 cpu = <&cpu6>; 64 }; 65 core1 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0000>; 75 enable-method = "psci"; 76 cpu-idle-states = <&ananke_cpu_sleep>; 77 capacity-dmips-mhz = <250>; 78 dynamic-power-coefficient = <70>; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a55"; 84 reg = <0x0100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&ananke_cpu_sleep>; 87 capacity-dmips-mhz = <250>; 88 dynamic-power-coefficient = <70>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0200>; 95 enable-method = "psci"; 96 cpu-idle-states = <&ananke_cpu_sleep>; 97 capacity-dmips-mhz = <250>; 98 dynamic-power-coefficient = <70>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0300>; 105 enable-method = "psci"; 106 cpu-idle-states = <&ananke_cpu_sleep>; 107 capacity-dmips-mhz = <250>; 108 dynamic-power-coefficient = <70>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a76"; 114 reg = <0x0400>; 115 enable-method = "psci"; 116 cpu-idle-states = <&enyo_cpu_sleep>; 117 capacity-dmips-mhz = <620>; 118 dynamic-power-coefficient = <284>; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a76"; 124 reg = <0x0500>; 125 enable-method = "psci"; 126 cpu-idle-states = <&enyo_cpu_sleep>; 127 capacity-dmips-mhz = <620>; 128 dynamic-power-coefficient = <284>; 129 }; 130 131 cpu6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-x1"; 134 reg = <0x0600>; 135 enable-method = "psci"; 136 cpu-idle-states = <&hera_cpu_sleep>; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <650>; 139 }; 140 141 cpu7: cpu@700 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-x1"; 144 reg = <0x0700>; 145 enable-method = "psci"; 146 cpu-idle-states = <&hera_cpu_sleep>; 147 capacity-dmips-mhz = <1024>; 148 dynamic-power-coefficient = <650>; 149 }; 150 151 idle-states { 152 entry-method = "psci"; 153 154 ananke_cpu_sleep: cpu-ananke-sleep { 155 idle-state-name = "c2"; 156 compatible = "arm,idle-state"; 157 arm,psci-suspend-param = <0x0010000>; 158 local-timer-stop; 159 entry-latency-us = <70>; 160 exit-latency-us = <160>; 161 min-residency-us = <2000>; 162 }; 163 164 enyo_cpu_sleep: cpu-enyo-sleep { 165 idle-state-name = "c2"; 166 compatible = "arm,idle-state"; 167 arm,psci-suspend-param = <0x0010000>; 168 local-timer-stop; 169 entry-latency-us = <150>; 170 exit-latency-us = <190>; 171 min-residency-us = <2500>; 172 }; 173 174 hera_cpu_sleep: cpu-hera-sleep { 175 idle-state-name = "c2"; 176 compatible = "arm,idle-state"; 177 arm,psci-suspend-param = <0x0010000>; 178 local-timer-stop; 179 entry-latency-us = <235>; 180 exit-latency-us = <220>; 181 min-residency-us = <3500>; 182 }; 183 }; 184 }; 185 186 /* ect node is required to be present by bootloader */ 187 ect { 188 }; 189 190 ext_24_5m: clock-1 { 191 compatible = "fixed-clock"; 192 #clock-cells = <0>; 193 clock-output-names = "oscclk"; 194 }; 195 196 ext_200m: clock-2 { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-output-names = "ext-200m"; 200 }; 201 202 firmware { 203 acpm_ipc: power-management { 204 compatible = "google,gs101-acpm-ipc"; 205 mboxes = <&ap2apm_mailbox>; 206 shmem = <&apm_sram>; 207 }; 208 }; 209 210 pmu-0 { 211 compatible = "arm,cortex-a55-pmu"; 212 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 213 }; 214 215 pmu-1 { 216 compatible = "arm,cortex-a76-pmu"; 217 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 218 }; 219 220 pmu-2 { 221 compatible = "arm,cortex-x1-pmu"; 222 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 223 }; 224 225 pmu-3 { 226 compatible = "arm,dsu-pmu"; 227 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 228 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 229 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; 230 }; 231 232 psci { 233 compatible = "arm,psci-1.0"; 234 method = "smc"; 235 }; 236 237 reserved_memory: reserved-memory { 238 #address-cells = <2>; 239 #size-cells = <1>; 240 ranges; 241 242 gsa_reserved_protected: gsa@90200000 { 243 reg = <0x0 0x90200000 0x400000>; 244 no-map; 245 }; 246 247 tpu_fw_reserved: tpu-fw@93000000 { 248 reg = <0x0 0x93000000 0x1000000>; 249 no-map; 250 }; 251 252 aoc_reserve: aoc@94000000 { 253 reg = <0x0 0x94000000 0x03000000>; 254 no-map; 255 }; 256 257 abl_reserved: abl@f8800000 { 258 reg = <0x0 0xf8800000 0x02000000>; 259 no-map; 260 }; 261 262 dss_log_reserved: dss-log-reserved@fd3f0000 { 263 reg = <0x0 0xfd3f0000 0x0000e000>; 264 no-map; 265 }; 266 267 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { 268 reg = <0x0 0xfd3fe000 0x00001000>; 269 no-map; 270 }; 271 272 bldr_log_reserved: bldr-log-reserved@fd800000 { 273 reg = <0x0 0xfd800000 0x00100000>; 274 no-map; 275 }; 276 277 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { 278 reg = <0x0 0xfd900000 0x00002000>; 279 no-map; 280 }; 281 }; 282 283 soc: soc@0 { 284 compatible = "simple-bus"; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges = <0x0 0x0 0x0 0x40000000>; 288 289 cmu_misc: clock-controller@10010000 { 290 compatible = "google,gs101-cmu-misc"; 291 reg = <0x10010000 0x8000>; 292 #clock-cells = <1>; 293 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, 294 <&cmu_top CLK_DOUT_CMU_MISC_SSS>; 295 clock-names = "bus", "sss"; 296 }; 297 298 timer@10050000 { 299 compatible = "google,gs101-mct", 300 "samsung,exynos4210-mct"; 301 reg = <0x10050000 0x800>; 302 clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; 303 clock-names = "fin_pll", "mct"; 304 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, 305 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, 306 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, 307 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, 308 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, 309 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, 310 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, 311 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, 312 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, 313 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, 314 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, 315 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; 316 }; 317 318 watchdog_cl0: watchdog@10060000 { 319 compatible = "google,gs101-wdt"; 320 reg = <0x10060000 0x100>; 321 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, 322 <&ext_24_5m>; 323 clock-names = "watchdog", "watchdog_src"; 324 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; 325 samsung,syscon-phandle = <&pmu_system_controller>; 326 samsung,cluster-index = <0>; 327 status = "disabled"; 328 }; 329 330 watchdog_cl1: watchdog@10070000 { 331 compatible = "google,gs101-wdt"; 332 reg = <0x10070000 0x100>; 333 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, 334 <&ext_24_5m>; 335 clock-names = "watchdog", "watchdog_src"; 336 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; 337 samsung,syscon-phandle = <&pmu_system_controller>; 338 samsung,cluster-index = <1>; 339 status = "disabled"; 340 }; 341 342 gic: interrupt-controller@10400000 { 343 compatible = "arm,gic-v3"; 344 #address-cells = <0>; 345 #interrupt-cells = <4>; 346 interrupt-controller; 347 reg = <0x10400000 0x10000>, /* GICD */ 348 <0x10440000 0x100000>;/* GICR * 8 */ 349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 350 351 ppi-partitions { 352 ppi_cluster0: interrupt-partition-0 { 353 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 354 }; 355 356 ppi_cluster1: interrupt-partition-1 { 357 affinity = <&cpu4 &cpu5>; 358 }; 359 360 ppi_cluster2: interrupt-partition-2 { 361 affinity = <&cpu6 &cpu7>; 362 }; 363 }; 364 }; 365 366 cmu_peric0: clock-controller@10800000 { 367 compatible = "google,gs101-cmu-peric0"; 368 reg = <0x10800000 0x4000>; 369 #clock-cells = <1>; 370 clocks = <&ext_24_5m>, 371 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 372 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 373 clock-names = "oscclk", "bus", "ip"; 374 }; 375 376 sysreg_peric0: syscon@10820000 { 377 compatible = "google,gs101-peric0-sysreg", "syscon"; 378 reg = <0x10820000 0x10000>; 379 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 380 }; 381 382 pinctrl_peric0: pinctrl@10840000 { 383 compatible = "google,gs101-pinctrl"; 384 reg = <0x10840000 0x00001000>; 385 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; 386 clock-names = "pclk"; 387 interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; 388 }; 389 390 usi1: usi@109000c0 { 391 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 392 reg = <0x109000c0 0x20>; 393 ranges; 394 #address-cells = <1>; 395 #size-cells = <1>; 396 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 397 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 398 clock-names = "pclk", "ipclk"; 399 samsung,sysreg = <&sysreg_peric0 0x1000>; 400 status = "disabled"; 401 402 hsi2c_1: i2c@10900000 { 403 compatible = "google,gs101-hsi2c", 404 "samsung,exynosautov9-hsi2c"; 405 reg = <0x10900000 0xc0>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, 409 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; 410 clock-names = "hsi2c", "hsi2c_pclk"; 411 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 412 pinctrl-0 = <&hsi2c1_bus>; 413 pinctrl-names = "default"; 414 status = "disabled"; 415 }; 416 417 serial_1: serial@10900000 { 418 compatible = "google,gs101-uart"; 419 reg = <0x10900000 0xc0>; 420 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 421 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 422 clock-names = "uart", "clk_uart_baud0"; 423 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 424 pinctrl-0 = <&uart1_bus_single>; 425 pinctrl-names = "default"; 426 samsung,uart-fifosize = <64>; 427 status = "disabled"; 428 }; 429 430 spi_1: spi@10900000 { 431 compatible = "google,gs101-spi"; 432 reg = <0x10900000 0x30>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 436 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 437 clock-names = "spi", "spi_busclk0"; 438 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 439 pinctrl-0 = <&spi1_bus>; 440 pinctrl-names = "default"; 441 status = "disabled"; 442 }; 443 }; 444 445 usi2: usi@109100c0 { 446 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 447 reg = <0x109100c0 0x20>; 448 ranges; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 452 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 453 clock-names = "pclk", "ipclk"; 454 samsung,sysreg = <&sysreg_peric0 0x1004>; 455 status = "disabled"; 456 457 hsi2c_2: i2c@10910000 { 458 compatible = "google,gs101-hsi2c", 459 "samsung,exynosautov9-hsi2c"; 460 reg = <0x10910000 0xc0>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, 464 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; 465 clock-names = "hsi2c", "hsi2c_pclk"; 466 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 467 pinctrl-0 = <&hsi2c2_bus>; 468 pinctrl-names = "default"; 469 status = "disabled"; 470 }; 471 472 serial_2: serial@10910000 { 473 compatible = "google,gs101-uart"; 474 reg = <0x10910000 0xc0>; 475 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 476 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 477 clock-names = "uart", "clk_uart_baud0"; 478 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 479 pinctrl-0 = <&uart2_bus_single>; 480 pinctrl-names = "default"; 481 samsung,uart-fifosize = <64>; 482 status = "disabled"; 483 }; 484 485 spi_2: spi@10910000 { 486 compatible = "google,gs101-spi"; 487 reg = <0x10910000 0x30>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 491 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 492 clock-names = "spi", "spi_busclk0"; 493 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 494 pinctrl-0 = <&spi2_bus>; 495 pinctrl-names = "default"; 496 status = "disabled"; 497 }; 498 }; 499 500 usi3: usi@109200c0 { 501 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 502 reg = <0x109200c0 0x20>; 503 ranges; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 507 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 508 clock-names = "pclk", "ipclk"; 509 samsung,sysreg = <&sysreg_peric0 0x1008>; 510 status = "disabled"; 511 512 hsi2c_3: i2c@10920000 { 513 compatible = "google,gs101-hsi2c", 514 "samsung,exynosautov9-hsi2c"; 515 reg = <0x10920000 0xc0>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, 519 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; 520 clock-names = "hsi2c", "hsi2c_pclk"; 521 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 522 pinctrl-0 = <&hsi2c3_bus>; 523 pinctrl-names = "default"; 524 status = "disabled"; 525 }; 526 527 serial_3: serial@10920000 { 528 compatible = "google,gs101-uart"; 529 reg = <0x10920000 0xc0>; 530 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 531 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 532 clock-names = "uart", "clk_uart_baud0"; 533 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 534 pinctrl-0 = <&uart3_bus_single>; 535 pinctrl-names = "default"; 536 samsung,uart-fifosize = <64>; 537 status = "disabled"; 538 }; 539 540 spi_3: spi@10920000 { 541 compatible = "google,gs101-spi"; 542 reg = <0x10920000 0x30>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 546 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 547 clock-names = "spi", "spi_busclk0"; 548 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 549 pinctrl-0 = <&spi3_bus>; 550 pinctrl-names = "default"; 551 status = "disabled"; 552 }; 553 }; 554 555 usi4: usi@109300c0 { 556 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 557 reg = <0x109300c0 0x20>; 558 ranges; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 562 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 563 clock-names = "pclk", "ipclk"; 564 samsung,sysreg = <&sysreg_peric0 0x100c>; 565 status = "disabled"; 566 567 hsi2c_4: i2c@10930000 { 568 compatible = "google,gs101-hsi2c", 569 "samsung,exynosautov9-hsi2c"; 570 reg = <0x10930000 0xc0>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, 574 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; 575 clock-names = "hsi2c", "hsi2c_pclk"; 576 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 577 pinctrl-0 = <&hsi2c4_bus>; 578 pinctrl-names = "default"; 579 status = "disabled"; 580 }; 581 582 serial_4: serial@10930000 { 583 compatible = "google,gs101-uart"; 584 reg = <0x10930000 0xc0>; 585 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 586 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 587 clock-names = "uart", "clk_uart_baud0"; 588 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 589 pinctrl-0 = <&uart4_bus_single>; 590 pinctrl-names = "default"; 591 samsung,uart-fifosize = <64>; 592 status = "disabled"; 593 }; 594 595 spi_4: spi@10930000 { 596 compatible = "google,gs101-spi"; 597 reg = <0x10930000 0x30>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 601 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 602 clock-names = "spi", "spi_busclk0"; 603 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 604 pinctrl-0 = <&spi4_bus>; 605 pinctrl-names = "default"; 606 status = "disabled"; 607 }; 608 }; 609 610 usi5: usi@109400c0 { 611 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 612 reg = <0x109400c0 0x20>; 613 ranges; 614 #address-cells = <1>; 615 #size-cells = <1>; 616 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 617 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 618 clock-names = "pclk", "ipclk"; 619 samsung,sysreg = <&sysreg_peric0 0x1010>; 620 status = "disabled"; 621 622 hsi2c_5: i2c@10940000 { 623 compatible = "google,gs101-hsi2c", 624 "samsung,exynosautov9-hsi2c"; 625 reg = <0x10940000 0xc0>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, 629 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; 630 clock-names = "hsi2c", "hsi2c_pclk"; 631 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 632 pinctrl-0 = <&hsi2c5_bus>; 633 pinctrl-names = "default"; 634 status = "disabled"; 635 }; 636 637 serial_5: serial@10940000 { 638 compatible = "google,gs101-uart"; 639 reg = <0x10940000 0xc0>; 640 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 641 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 642 clock-names = "uart", "clk_uart_baud0"; 643 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 644 pinctrl-0 = <&uart5_bus_single>; 645 pinctrl-names = "default"; 646 samsung,uart-fifosize = <64>; 647 status = "disabled"; 648 }; 649 650 spi_5: spi@10940000 { 651 compatible = "google,gs101-spi"; 652 reg = <0x10940000 0x30>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 656 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 657 clock-names = "spi", "spi_busclk0"; 658 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 659 pinctrl-0 = <&spi5_bus>; 660 pinctrl-names = "default"; 661 status = "disabled"; 662 }; 663 }; 664 665 usi6: usi@109500c0 { 666 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 667 reg = <0x109500c0 0x20>; 668 ranges; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 672 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 673 clock-names = "pclk", "ipclk"; 674 samsung,sysreg = <&sysreg_peric0 0x1014>; 675 status = "disabled"; 676 677 hsi2c_6: i2c@10950000 { 678 compatible = "google,gs101-hsi2c", 679 "samsung,exynosautov9-hsi2c"; 680 reg = <0x10950000 0xc0>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, 684 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; 685 clock-names = "hsi2c", "hsi2c_pclk"; 686 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 687 pinctrl-0 = <&hsi2c6_bus>; 688 pinctrl-names = "default"; 689 status = "disabled"; 690 }; 691 692 serial_6: serial@10950000 { 693 compatible = "google,gs101-uart"; 694 reg = <0x10950000 0xc0>; 695 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 696 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 697 clock-names = "uart", "clk_uart_baud0"; 698 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 699 pinctrl-0 = <&uart6_bus_single>; 700 pinctrl-names = "default"; 701 samsung,uart-fifosize = <64>; 702 status = "disabled"; 703 }; 704 705 spi_6: spi@10950000 { 706 compatible = "google,gs101-spi"; 707 reg = <0x10950000 0x30>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 711 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 712 clock-names = "spi", "spi_busclk0"; 713 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 714 pinctrl-0 = <&spi6_bus>; 715 pinctrl-names = "default"; 716 status = "disabled"; 717 }; 718 }; 719 720 usi7: usi@109600c0 { 721 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 722 reg = <0x109600c0 0x20>; 723 ranges; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 727 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 728 clock-names = "pclk", "ipclk"; 729 samsung,sysreg = <&sysreg_peric0 0x1018>; 730 status = "disabled"; 731 732 hsi2c_7: i2c@10960000 { 733 compatible = "google,gs101-hsi2c", 734 "samsung,exynosautov9-hsi2c"; 735 reg = <0x10960000 0xc0>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, 739 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; 740 clock-names = "hsi2c", "hsi2c_pclk"; 741 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 742 pinctrl-0 = <&hsi2c7_bus>; 743 pinctrl-names = "default"; 744 status = "disabled"; 745 }; 746 747 serial_7: serial@10960000 { 748 compatible = "google,gs101-uart"; 749 reg = <0x10960000 0xc0>; 750 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 751 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 752 clock-names = "uart", "clk_uart_baud0"; 753 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 754 pinctrl-0 = <&uart7_bus_single>; 755 pinctrl-names = "default"; 756 samsung,uart-fifosize = <64>; 757 status = "disabled"; 758 }; 759 760 spi_7: spi@10960000 { 761 compatible = "google,gs101-spi"; 762 reg = <0x10960000 0x30>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 766 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 767 clock-names = "spi", "spi_busclk0"; 768 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 769 pinctrl-0 = <&spi7_bus>; 770 pinctrl-names = "default"; 771 status = "disabled"; 772 }; 773 }; 774 775 usi8: usi@109700c0 { 776 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 777 reg = <0x109700c0 0x20>; 778 ranges; 779 #address-cells = <1>; 780 #size-cells = <1>; 781 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 782 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 783 clock-names = "pclk", "ipclk"; 784 samsung,sysreg = <&sysreg_peric0 0x101c>; 785 status = "disabled"; 786 787 hsi2c_8: i2c@10970000 { 788 compatible = "google,gs101-hsi2c", 789 "samsung,exynosautov9-hsi2c"; 790 reg = <0x10970000 0xc0>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, 794 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; 795 clock-names = "hsi2c", "hsi2c_pclk"; 796 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 797 pinctrl-0 = <&hsi2c8_bus>; 798 pinctrl-names = "default"; 799 status = "disabled"; 800 }; 801 802 serial_8: serial@10970000 { 803 compatible = "google,gs101-uart"; 804 reg = <0x10970000 0xc0>; 805 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 806 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 807 clock-names = "uart", "clk_uart_baud0"; 808 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 809 pinctrl-0 = <&uart8_bus_single>; 810 pinctrl-names = "default"; 811 samsung,uart-fifosize = <64>; 812 status = "disabled"; 813 }; 814 815 spi_8: spi@10970000 { 816 compatible = "google,gs101-spi"; 817 reg = <0x10970000 0x30>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 821 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 822 clock-names = "spi", "spi_busclk0"; 823 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 824 pinctrl-0 = <&spi8_bus>; 825 pinctrl-names = "default"; 826 status = "disabled"; 827 }; 828 }; 829 830 usi_uart: usi@10a000c0 { 831 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 832 reg = <0x10a000c0 0x20>; 833 ranges; 834 #address-cells = <1>; 835 #size-cells = <1>; 836 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 837 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 838 clock-names = "pclk", "ipclk"; 839 samsung,sysreg = <&sysreg_peric0 0x1020>; 840 samsung,mode = <USI_MODE_UART>; 841 status = "disabled"; 842 843 serial_0: serial@10a00000 { 844 compatible = "google,gs101-uart"; 845 reg = <0x10a00000 0xc0>; 846 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 847 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 848 clock-names = "uart", "clk_uart_baud0"; 849 interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; 850 pinctrl-0 = <&uart0_bus>; 851 pinctrl-names = "default"; 852 samsung,uart-fifosize = <256>; 853 status = "disabled"; 854 }; 855 }; 856 857 usi14: usi@10a200c0 { 858 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 859 reg = <0x10a200c0 0x20>; 860 ranges; 861 #address-cells = <1>; 862 #size-cells = <1>; 863 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 864 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 865 clock-names = "pclk", "ipclk"; 866 samsung,sysreg = <&sysreg_peric0 0x1028>; 867 status = "disabled"; 868 869 hsi2c_14: i2c@10a20000 { 870 compatible = "google,gs101-hsi2c", 871 "samsung,exynosautov9-hsi2c"; 872 reg = <0x10a20000 0xc0>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, 876 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; 877 clock-names = "hsi2c", "hsi2c_pclk"; 878 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 879 pinctrl-0 = <&hsi2c14_bus>; 880 pinctrl-names = "default"; 881 status = "disabled"; 882 }; 883 884 serial_14: serial@10a20000 { 885 compatible = "google,gs101-uart"; 886 reg = <0x10a20000 0xc0>; 887 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 888 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 889 clock-names = "uart", "clk_uart_baud0"; 890 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 891 pinctrl-0 = <&uart14_bus_single>; 892 pinctrl-names = "default"; 893 samsung,uart-fifosize = <64>; 894 status = "disabled"; 895 }; 896 897 spi_14: spi@10a20000 { 898 compatible = "google,gs101-spi"; 899 reg = <0x10a20000 0x30>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 903 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 904 clock-names = "spi", "spi_busclk0"; 905 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 906 pinctrl-0 = <&spi14_bus>; 907 pinctrl-names = "default"; 908 status = "disabled"; 909 }; 910 }; 911 912 cmu_peric1: clock-controller@10c00000 { 913 compatible = "google,gs101-cmu-peric1"; 914 reg = <0x10c00000 0x4000>; 915 #clock-cells = <1>; 916 clocks = <&ext_24_5m>, 917 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 918 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 919 clock-names = "oscclk", "bus", "ip"; 920 }; 921 922 sysreg_peric1: syscon@10c20000 { 923 compatible = "google,gs101-peric1-sysreg", "syscon"; 924 reg = <0x10c20000 0x10000>; 925 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 926 }; 927 928 pinctrl_peric1: pinctrl@10c40000 { 929 compatible = "google,gs101-pinctrl"; 930 reg = <0x10c40000 0x00001000>; 931 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; 932 clock-names = "pclk"; 933 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 934 }; 935 936 usi0: usi@10d100c0 { 937 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 938 reg = <0x10d100c0 0x20>; 939 ranges; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 943 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 944 clock-names = "pclk", "ipclk"; 945 samsung,sysreg = <&sysreg_peric1 0x1000>; 946 status = "disabled"; 947 948 hsi2c_0: i2c@10d10000 { 949 compatible = "google,gs101-hsi2c", 950 "samsung,exynosautov9-hsi2c"; 951 reg = <0x10d10000 0xc0>; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, 955 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; 956 clock-names = "hsi2c", "hsi2c_pclk"; 957 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 958 pinctrl-0 = <&hsi2c0_bus>; 959 pinctrl-names = "default"; 960 status = "disabled"; 961 }; 962 963 serial_usi0: serial@10d10000 { 964 compatible = "google,gs101-uart"; 965 reg = <0x10d10000 0xc0>; 966 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 967 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 968 clock-names = "uart", "clk_uart_baud0"; 969 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 970 pinctrl-0 = <&uart0_bus_single>; 971 pinctrl-names = "default"; 972 samsung,uart-fifosize = <64>; 973 status = "disabled"; 974 }; 975 976 spi_0: spi@10d10000 { 977 compatible = "google,gs101-spi"; 978 reg = <0x10d10000 0x30>; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 982 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 983 clock-names = "spi", "spi_busclk0"; 984 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 985 pinctrl-0 = <&spi0_bus>; 986 pinctrl-names = "default"; 987 status = "disabled"; 988 }; 989 }; 990 991 usi9: usi@10d200c0 { 992 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 993 reg = <0x10d200c0 0x20>; 994 ranges; 995 #address-cells = <1>; 996 #size-cells = <1>; 997 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 998 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 999 clock-names = "pclk", "ipclk"; 1000 samsung,sysreg = <&sysreg_peric1 0x1004>; 1001 status = "disabled"; 1002 1003 hsi2c_9: i2c@10d20000 { 1004 compatible = "google,gs101-hsi2c", 1005 "samsung,exynosautov9-hsi2c"; 1006 reg = <0x10d20000 0xc0>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, 1010 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; 1011 clock-names = "hsi2c", "hsi2c_pclk"; 1012 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1013 pinctrl-0 = <&hsi2c9_bus>; 1014 pinctrl-names = "default"; 1015 status = "disabled"; 1016 }; 1017 1018 serial_9: serial@10d20000 { 1019 compatible = "google,gs101-uart"; 1020 reg = <0x10d20000 0xc0>; 1021 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1022 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1023 clock-names = "uart", "clk_uart_baud0"; 1024 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1025 pinctrl-0 = <&uart9_bus_single>; 1026 pinctrl-names = "default"; 1027 samsung,uart-fifosize = <64>; 1028 status = "disabled"; 1029 }; 1030 1031 spi_9: spi@10d20000 { 1032 compatible = "google,gs101-spi"; 1033 reg = <0x10d20000 0x30>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1037 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1038 clock-names = "spi", "spi_busclk0"; 1039 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1040 pinctrl-0 = <&spi9_bus>; 1041 pinctrl-names = "default"; 1042 status = "disabled"; 1043 }; 1044 }; 1045 1046 usi10: usi@10d300c0 { 1047 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1048 reg = <0x10d300c0 0x20>; 1049 ranges; 1050 #address-cells = <1>; 1051 #size-cells = <1>; 1052 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1053 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1054 clock-names = "pclk", "ipclk"; 1055 samsung,sysreg = <&sysreg_peric1 0x1008>; 1056 status = "disabled"; 1057 1058 hsi2c_10: i2c@10d30000 { 1059 compatible = "google,gs101-hsi2c", 1060 "samsung,exynosautov9-hsi2c"; 1061 reg = <0x10d30000 0xc0>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, 1065 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; 1066 clock-names = "hsi2c", "hsi2c_pclk"; 1067 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1068 pinctrl-0 = <&hsi2c10_bus>; 1069 pinctrl-names = "default"; 1070 status = "disabled"; 1071 }; 1072 1073 serial_10: serial@10d30000 { 1074 compatible = "google,gs101-uart"; 1075 reg = <0x10d30000 0xc0>; 1076 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1077 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1078 clock-names = "uart", "clk_uart_baud0"; 1079 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1080 pinctrl-0 = <&uart10_bus_single>; 1081 pinctrl-names = "default"; 1082 samsung,uart-fifosize = <64>; 1083 status = "disabled"; 1084 }; 1085 1086 spi_10: spi@10d30000 { 1087 compatible = "google,gs101-spi"; 1088 reg = <0x10d30000 0x30>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1092 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1093 clock-names = "spi", "spi_busclk0"; 1094 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1095 pinctrl-0 = <&spi10_bus>; 1096 pinctrl-names = "default"; 1097 status = "disabled"; 1098 }; 1099 }; 1100 1101 usi11: usi@10d400c0 { 1102 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1103 reg = <0x10d400c0 0x20>; 1104 ranges; 1105 #address-cells = <1>; 1106 #size-cells = <1>; 1107 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1108 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1109 clock-names = "pclk", "ipclk"; 1110 samsung,sysreg = <&sysreg_peric1 0x100c>; 1111 status = "disabled"; 1112 1113 hsi2c_11: i2c@10d40000 { 1114 compatible = "google,gs101-hsi2c", 1115 "samsung,exynosautov9-hsi2c"; 1116 reg = <0x10d40000 0xc0>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, 1120 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; 1121 clock-names = "hsi2c", "hsi2c_pclk"; 1122 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1123 pinctrl-0 = <&hsi2c11_bus>; 1124 pinctrl-names = "default"; 1125 status = "disabled"; 1126 }; 1127 1128 serial_11: serial@10d40000 { 1129 compatible = "google,gs101-uart"; 1130 reg = <0x10d40000 0xc0>; 1131 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1132 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1133 clock-names = "uart", "clk_uart_baud0"; 1134 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1135 pinctrl-0 = <&uart11_bus_single>; 1136 pinctrl-names = "default"; 1137 samsung,uart-fifosize = <64>; 1138 status = "disabled"; 1139 }; 1140 1141 spi_11: spi@10d40000 { 1142 compatible = "google,gs101-spi"; 1143 reg = <0x10d40000 0x30>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1147 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1148 clock-names = "spi", "spi_busclk0"; 1149 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1150 pinctrl-0 = <&spi11_bus>; 1151 pinctrl-names = "default"; 1152 status = "disabled"; 1153 }; 1154 }; 1155 1156 usi12: usi@10d500c0 { 1157 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1158 reg = <0x10d500c0 0x20>; 1159 ranges; 1160 #address-cells = <1>; 1161 #size-cells = <1>; 1162 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1163 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1164 clock-names = "pclk", "ipclk"; 1165 samsung,sysreg = <&sysreg_peric1 0x1010>; 1166 status = "disabled"; 1167 1168 hsi2c_12: i2c@10d50000 { 1169 compatible = "google,gs101-hsi2c", 1170 "samsung,exynosautov9-hsi2c"; 1171 reg = <0x10d50000 0xc0>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, 1175 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; 1176 clock-names = "hsi2c", "hsi2c_pclk"; 1177 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1178 pinctrl-0 = <&hsi2c12_bus>; 1179 pinctrl-names = "default"; 1180 status = "disabled"; 1181 }; 1182 1183 serial_12: serial@10d50000 { 1184 compatible = "google,gs101-uart"; 1185 reg = <0x10d50000 0xc0>; 1186 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1187 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1188 clock-names = "uart", "clk_uart_baud0"; 1189 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1190 pinctrl-0 = <&uart12_bus_single>; 1191 pinctrl-names = "default"; 1192 samsung,uart-fifosize = <64>; 1193 status = "disabled"; 1194 }; 1195 1196 spi_12: spi@10d50000 { 1197 compatible = "google,gs101-spi"; 1198 reg = <0x10d50000 0x30>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1202 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1203 clock-names = "spi", "spi_busclk0"; 1204 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1205 pinctrl-0 = <&spi12_bus>; 1206 pinctrl-names = "default"; 1207 status = "disabled"; 1208 }; 1209 }; 1210 1211 usi13: usi@10d600c0 { 1212 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1213 reg = <0x10d600c0 0x20>; 1214 ranges; 1215 #address-cells = <1>; 1216 #size-cells = <1>; 1217 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1218 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1219 clock-names = "pclk", "ipclk"; 1220 samsung,sysreg = <&sysreg_peric1 0x1014>; 1221 status = "disabled"; 1222 1223 hsi2c_13: i2c@10d60000 { 1224 compatible = "google,gs101-hsi2c", 1225 "samsung,exynosautov9-hsi2c"; 1226 reg = <0x10d60000 0xc0>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, 1230 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; 1231 clock-names = "hsi2c", "hsi2c_pclk"; 1232 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1233 pinctrl-0 = <&hsi2c13_bus>; 1234 pinctrl-names = "default"; 1235 status = "disabled"; 1236 }; 1237 1238 serial_13: serial@10d60000 { 1239 compatible = "google,gs101-uart"; 1240 reg = <0x10d60000 0xc0>; 1241 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1242 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1243 clock-names = "uart", "clk_uart_baud0"; 1244 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1245 pinctrl-0 = <&uart13_bus_single>; 1246 pinctrl-names = "default"; 1247 samsung,uart-fifosize = <64>; 1248 status = "disabled"; 1249 }; 1250 1251 spi_13: spi@10d60000 { 1252 compatible = "google,gs101-spi"; 1253 reg = <0x10d60000 0x30>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1257 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1258 clock-names = "spi", "spi_busclk0"; 1259 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1260 pinctrl-0 = <&spi13_bus>; 1261 pinctrl-names = "default"; 1262 status = "disabled"; 1263 }; 1264 }; 1265 1266 cmu_hsi0: clock-controller@11000000 { 1267 compatible = "google,gs101-cmu-hsi0"; 1268 reg = <0x11000000 0x4000>; 1269 #clock-cells = <1>; 1270 1271 clocks = <&ext_24_5m>, 1272 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, 1273 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, 1274 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, 1275 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; 1276 clock-names = "oscclk", "bus", "dpgtc", "usb31drd", 1277 "usbdpdbg"; 1278 }; 1279 1280 usbdrd31_phy: phy@11100000 { 1281 compatible = "google,gs101-usb31drd-phy"; 1282 reg = <0x11100000 0x0200>, 1283 <0x110f0000 0x0800>, 1284 <0x110e0000 0x2800>; 1285 reg-names = "phy", "pcs", "pma"; 1286 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, 1287 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, 1288 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, 1289 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, 1290 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; 1291 clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; 1292 #phy-cells = <1>; 1293 samsung,pmu-syscon = <&pmu_system_controller>; 1294 status = "disabled"; 1295 }; 1296 1297 usbdrd31: usb@11110000 { 1298 compatible = "google,gs101-dwusb3"; 1299 ranges = <0x0 0x11110000 0x10000>; 1300 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, 1301 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, 1302 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, 1303 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; 1304 clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; 1305 #address-cells = <1>; 1306 #size-cells = <1>; 1307 status = "disabled"; 1308 1309 usbdrd31_dwc3: usb@0 { 1310 compatible = "snps,dwc3"; 1311 reg = <0x0 0x10000>; 1312 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; 1313 clock-names = "ref"; 1314 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1315 phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; 1316 phy-names = "usb2-phy", "usb3-phy"; 1317 snps,has-lpm-erratum; 1318 snps,dis_u2_susphy_quirk; 1319 snps,dis_u3_susphy_quirk; 1320 status = "disabled"; 1321 }; 1322 }; 1323 1324 pinctrl_hsi1: pinctrl@11840000 { 1325 compatible = "google,gs101-pinctrl"; 1326 reg = <0x11840000 0x00001000>; 1327 /* TODO: update once support for this CMU exists */ 1328 clocks = <0>; 1329 clock-names = "pclk"; 1330 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1331 }; 1332 1333 cmu_hsi2: clock-controller@14400000 { 1334 compatible = "google,gs101-cmu-hsi2"; 1335 reg = <0x14400000 0x4000>; 1336 #clock-cells = <1>; 1337 clocks = <&ext_24_5m>, 1338 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, 1339 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, 1340 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, 1341 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; 1342 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; 1343 }; 1344 1345 sysreg_hsi2: syscon@14420000 { 1346 compatible = "google,gs101-hsi2-sysreg", "syscon"; 1347 reg = <0x14420000 0x10000>; 1348 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1349 }; 1350 1351 pinctrl_hsi2: pinctrl@14440000 { 1352 compatible = "google,gs101-pinctrl"; 1353 reg = <0x14440000 0x00001000>; 1354 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; 1355 clock-names = "pclk"; 1356 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 1357 }; 1358 1359 ufs_0: ufs@14700000 { 1360 compatible = "google,gs101-ufs"; 1361 reg = <0x14700000 0x200>, 1362 <0x14701100 0x200>, 1363 <0x14780000 0xa000>, 1364 <0x14600000 0x100>; 1365 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1366 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1367 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, 1368 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, 1369 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, 1370 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, 1371 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, 1372 <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1373 clock-names = "core_clk", "sclk_unipro_main", "fmp", 1374 "aclk", "pclk", "sysreg"; 1375 dma-coherent; 1376 freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; 1377 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1378 pinctrl-names = "default"; 1379 phys = <&ufs_0_phy>; 1380 phy-names = "ufs-phy"; 1381 samsung,sysreg = <&sysreg_hsi2 0x710>; 1382 status = "disabled"; 1383 }; 1384 1385 ufs_0_phy: phy@14704000 { 1386 compatible = "google,gs101-ufs-phy"; 1387 reg = <0x14704000 0x3000>; 1388 reg-names = "phy-pma"; 1389 samsung,pmu-syscon = <&pmu_system_controller>; 1390 #phy-cells = <0>; 1391 clocks = <&ext_24_5m>; 1392 clock-names = "ref_clk"; 1393 status = "disabled"; 1394 }; 1395 1396 cmu_apm: clock-controller@17400000 { 1397 compatible = "google,gs101-cmu-apm"; 1398 reg = <0x17400000 0x8000>; 1399 #clock-cells = <1>; 1400 1401 clocks = <&ext_24_5m>; 1402 clock-names = "oscclk"; 1403 }; 1404 1405 sysreg_apm: syscon@174204e0 { 1406 compatible = "google,gs101-apm-sysreg", "syscon"; 1407 reg = <0x174204e0 0x1000>; 1408 }; 1409 1410 pmu_system_controller: system-controller@17460000 { 1411 compatible = "google,gs101-pmu", "syscon"; 1412 reg = <0x17460000 0x10000>; 1413 google,pmu-intr-gen-syscon = <&pmu_intr_gen>; 1414 1415 poweroff: syscon-poweroff { 1416 compatible = "syscon-poweroff"; 1417 offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ 1418 mask = <0x00000100>; 1419 value = <0x0>; 1420 }; 1421 1422 reboot: syscon-reboot { 1423 compatible = "google,gs101-reboot"; 1424 }; 1425 1426 reboot-mode { 1427 compatible = "syscon-reboot-mode"; 1428 offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */ 1429 mode-bootloader = <0xfc>; 1430 mode-charge = <0x0a>; 1431 mode-dm-verity-device-corrupted = <0x50>; 1432 mode-fastboot = <0xfa>; 1433 mode-reboot-ab-update = <0x52>; 1434 mode-recovery = <0xff>; 1435 mode-rescue = <0xf9>; 1436 mode-shutdown-thermal = <0x51>; 1437 mode-shutdown-thermal-battery = <0x51>; 1438 }; 1439 }; 1440 1441 pmu_intr_gen: syscon@17470000 { 1442 compatible = "google,gs101-pmu-intr-gen", "syscon"; 1443 reg = <0x17470000 0x10000>; 1444 }; 1445 1446 pinctrl_gpio_alive: pinctrl@174d0000 { 1447 compatible = "google,gs101-pinctrl"; 1448 reg = <0x174d0000 0x00001000>; 1449 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; 1450 clock-names = "pclk"; 1451 1452 wakeup-interrupt-controller { 1453 compatible = "google,gs101-wakeup-eint", 1454 "samsung,exynos850-wakeup-eint", 1455 "samsung,exynos7-wakeup-eint"; 1456 }; 1457 }; 1458 1459 pinctrl_far_alive: pinctrl@174e0000 { 1460 compatible = "google,gs101-pinctrl"; 1461 reg = <0x174e0000 0x00001000>; 1462 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; 1463 clock-names = "pclk"; 1464 1465 wakeup-interrupt-controller { 1466 compatible = "google,gs101-wakeup-eint", 1467 "samsung,exynos850-wakeup-eint", 1468 "samsung,exynos7-wakeup-eint"; 1469 }; 1470 }; 1471 1472 ap2apm_mailbox: mailbox@17610000 { 1473 compatible = "google,gs101-mbox"; 1474 reg = <0x17610000 0x1000>; 1475 clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; 1476 clock-names = "pclk"; 1477 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>; 1478 #mbox-cells = <0>; 1479 }; 1480 1481 pinctrl_gsactrl: pinctrl@17940000 { 1482 compatible = "google,gs101-pinctrl"; 1483 reg = <0x17940000 0x00001000>; 1484 /* TODO: update once support for this CMU exists */ 1485 clocks = <0>; 1486 clock-names = "pclk"; 1487 }; 1488 1489 pinctrl_gsacore: pinctrl@17a80000 { 1490 compatible = "google,gs101-pinctrl"; 1491 reg = <0x17a80000 0x00001000>; 1492 /* TODO: update once support for this CMU exists */ 1493 clocks = <0>; 1494 clock-names = "pclk"; 1495 status = "disabled"; 1496 }; 1497 1498 cmu_top: clock-controller@1e080000 { 1499 compatible = "google,gs101-cmu-top"; 1500 reg = <0x1e080000 0x8000>; 1501 #clock-cells = <1>; 1502 1503 clocks = <&ext_24_5m>; 1504 clock-names = "oscclk"; 1505 }; 1506 }; 1507 1508 apm_sram: sram@2039000 { 1509 compatible = "mmio-sram"; 1510 reg = <0x0 0x2039000 0x40000>; 1511 #address-cells = <1>; 1512 #size-cells = <1>; 1513 ranges = <0x0 0x0 0x2039000 0x40000>; 1514 }; 1515 1516 timer { 1517 compatible = "arm,armv8-timer"; 1518 interrupts = 1519 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1520 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1521 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1522 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 1523 }; 1524}; 1525 1526#include "gs101-pinctrl.dtsi" 1527