1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GS101 SoC 4 * 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 */ 8 9#include <dt-bindings/clock/google,gs101.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "google,gs101"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_gpio_alive; 23 pinctrl1 = &pinctrl_far_alive; 24 pinctrl2 = &pinctrl_gsacore; 25 pinctrl3 = &pinctrl_gsactrl; 26 pinctrl4 = &pinctrl_peric0; 27 pinctrl5 = &pinctrl_peric1; 28 pinctrl6 = &pinctrl_hsi1; 29 pinctrl7 = &pinctrl_hsi2; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu-map { 37 cluster0 { 38 core0 { 39 cpu = <&cpu0>; 40 }; 41 core1 { 42 cpu = <&cpu1>; 43 }; 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 core3 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu4>; 55 }; 56 core1 { 57 cpu = <&cpu5>; 58 }; 59 }; 60 61 cluster2 { 62 core0 { 63 cpu = <&cpu6>; 64 }; 65 core1 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0000>; 75 enable-method = "psci"; 76 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 77 capacity-dmips-mhz = <250>; 78 dynamic-power-coefficient = <70>; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a55"; 84 reg = <0x0100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 87 capacity-dmips-mhz = <250>; 88 dynamic-power-coefficient = <70>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0200>; 95 enable-method = "psci"; 96 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 97 capacity-dmips-mhz = <250>; 98 dynamic-power-coefficient = <70>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0300>; 105 enable-method = "psci"; 106 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 107 capacity-dmips-mhz = <250>; 108 dynamic-power-coefficient = <70>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a76"; 114 reg = <0x0400>; 115 enable-method = "psci"; 116 cpu-idle-states = <&ENYO_CPU_SLEEP>; 117 capacity-dmips-mhz = <620>; 118 dynamic-power-coefficient = <284>; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a76"; 124 reg = <0x0500>; 125 enable-method = "psci"; 126 cpu-idle-states = <&ENYO_CPU_SLEEP>; 127 capacity-dmips-mhz = <620>; 128 dynamic-power-coefficient = <284>; 129 }; 130 131 cpu6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-x1"; 134 reg = <0x0600>; 135 enable-method = "psci"; 136 cpu-idle-states = <&HERA_CPU_SLEEP>; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <650>; 139 }; 140 141 cpu7: cpu@700 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-x1"; 144 reg = <0x0700>; 145 enable-method = "psci"; 146 cpu-idle-states = <&HERA_CPU_SLEEP>; 147 capacity-dmips-mhz = <1024>; 148 dynamic-power-coefficient = <650>; 149 }; 150 151 idle-states { 152 entry-method = "psci"; 153 154 ANANKE_CPU_SLEEP: cpu-ananke-sleep { 155 idle-state-name = "c2"; 156 compatible = "arm,idle-state"; 157 arm,psci-suspend-param = <0x0010000>; 158 entry-latency-us = <70>; 159 exit-latency-us = <160>; 160 min-residency-us = <2000>; 161 }; 162 163 ENYO_CPU_SLEEP: cpu-enyo-sleep { 164 idle-state-name = "c2"; 165 compatible = "arm,idle-state"; 166 arm,psci-suspend-param = <0x0010000>; 167 entry-latency-us = <150>; 168 exit-latency-us = <190>; 169 min-residency-us = <2500>; 170 }; 171 172 HERA_CPU_SLEEP: cpu-hera-sleep { 173 idle-state-name = "c2"; 174 compatible = "arm,idle-state"; 175 arm,psci-suspend-param = <0x0010000>; 176 entry-latency-us = <235>; 177 exit-latency-us = <220>; 178 min-residency-us = <3500>; 179 }; 180 }; 181 }; 182 183 /* ect node is required to be present by bootloader */ 184 ect { 185 }; 186 187 ext_24_5m: clock-1 { 188 compatible = "fixed-clock"; 189 #clock-cells = <0>; 190 clock-output-names = "oscclk"; 191 }; 192 193 ext_200m: clock-2 { 194 compatible = "fixed-clock"; 195 #clock-cells = <0>; 196 clock-output-names = "ext-200m"; 197 }; 198 199 pmu-0 { 200 compatible = "arm,cortex-a55-pmu"; 201 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 202 }; 203 204 pmu-1 { 205 compatible = "arm,cortex-a76-pmu"; 206 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 207 }; 208 209 pmu-2 { 210 compatible = "arm,cortex-x1-pmu"; 211 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 212 }; 213 214 pmu-3 { 215 compatible = "arm,dsu-pmu"; 216 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; 217 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 218 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 219 }; 220 221 psci { 222 compatible = "arm,psci-1.0"; 223 method = "smc"; 224 }; 225 226 reserved_memory: reserved-memory { 227 #address-cells = <2>; 228 #size-cells = <1>; 229 ranges; 230 231 gsa_reserved_protected: gsa@90200000 { 232 reg = <0x0 0x90200000 0x400000>; 233 no-map; 234 }; 235 236 tpu_fw_reserved: tpu-fw@93000000 { 237 reg = <0x0 0x93000000 0x1000000>; 238 no-map; 239 }; 240 241 aoc_reserve: aoc@94000000 { 242 reg = <0x0 0x94000000 0x03000000>; 243 no-map; 244 }; 245 246 abl_reserved: abl@f8800000 { 247 reg = <0x0 0xf8800000 0x02000000>; 248 no-map; 249 }; 250 251 dss_log_reserved: dss-log-reserved@fd3f0000 { 252 reg = <0x0 0xfd3f0000 0x0000e000>; 253 no-map; 254 }; 255 256 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { 257 reg = <0x0 0xfd3fe000 0x00001000>; 258 no-map; 259 }; 260 261 bldr_log_reserved: bldr-log-reserved@fd800000 { 262 reg = <0x0 0xfd800000 0x00100000>; 263 no-map; 264 }; 265 266 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { 267 reg = <0x0 0xfd900000 0x00002000>; 268 no-map; 269 }; 270 }; 271 272 soc: soc@0 { 273 compatible = "simple-bus"; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 ranges = <0x0 0x0 0x0 0x40000000>; 277 278 cmu_misc: clock-controller@10010000 { 279 compatible = "google,gs101-cmu-misc"; 280 reg = <0x10010000 0x8000>; 281 #clock-cells = <1>; 282 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, 283 <&cmu_top CLK_DOUT_CMU_MISC_SSS>; 284 clock-names = "bus", "sss"; 285 }; 286 287 timer@10050000 { 288 compatible = "google,gs101-mct", 289 "samsung,exynos4210-mct"; 290 reg = <0x10050000 0x800>; 291 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, 292 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, 293 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, 294 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, 295 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, 296 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, 297 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, 298 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, 299 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, 300 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, 301 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, 302 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; 303 clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; 304 clock-names = "fin_pll", "mct"; 305 }; 306 307 watchdog_cl0: watchdog@10060000 { 308 compatible = "google,gs101-wdt"; 309 reg = <0x10060000 0x100>; 310 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; 311 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, 312 <&ext_24_5m>; 313 clock-names = "watchdog", "watchdog_src"; 314 samsung,syscon-phandle = <&pmu_system_controller>; 315 samsung,cluster-index = <0>; 316 status = "disabled"; 317 }; 318 319 watchdog_cl1: watchdog@10070000 { 320 compatible = "google,gs101-wdt"; 321 reg = <0x10070000 0x100>; 322 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; 323 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, 324 <&ext_24_5m>; 325 clock-names = "watchdog", "watchdog_src"; 326 samsung,syscon-phandle = <&pmu_system_controller>; 327 samsung,cluster-index = <1>; 328 status = "disabled"; 329 }; 330 331 gic: interrupt-controller@10400000 { 332 compatible = "arm,gic-v3"; 333 #interrupt-cells = <4>; 334 interrupt-controller; 335 reg = <0x10400000 0x10000>, /* GICD */ 336 <0x10440000 0x100000>;/* GICR * 8 */ 337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 338 339 ppi-partitions { 340 ppi_cluster0: interrupt-partition-0 { 341 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 342 }; 343 344 ppi_cluster1: interrupt-partition-1 { 345 affinity = <&cpu4 &cpu5>; 346 }; 347 348 ppi_cluster2: interrupt-partition-2 { 349 affinity = <&cpu6 &cpu7>; 350 }; 351 }; 352 }; 353 354 cmu_peric0: clock-controller@10800000 { 355 compatible = "google,gs101-cmu-peric0"; 356 reg = <0x10800000 0x4000>; 357 #clock-cells = <1>; 358 clocks = <&ext_24_5m>, 359 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 360 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 361 clock-names = "oscclk", "bus", "ip"; 362 }; 363 364 sysreg_peric0: syscon@10820000 { 365 compatible = "google,gs101-peric0-sysreg", "syscon"; 366 reg = <0x10820000 0x10000>; 367 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 368 }; 369 370 pinctrl_peric0: pinctrl@10840000 { 371 compatible = "google,gs101-pinctrl"; 372 reg = <0x10840000 0x00001000>; 373 interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; 374 }; 375 376 usi8: usi@109700c0 { 377 compatible = "google,gs101-usi", 378 "samsung,exynos850-usi"; 379 reg = <0x109700c0 0x20>; 380 ranges; 381 #address-cells = <1>; 382 #size-cells = <1>; 383 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 384 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 385 clock-names = "pclk", "ipclk"; 386 samsung,sysreg = <&sysreg_peric0 0x101c>; 387 status = "disabled"; 388 389 hsi2c_8: i2c@10970000 { 390 compatible = "google,gs101-hsi2c", 391 "samsung,exynosautov9-hsi2c"; 392 reg = <0x10970000 0xc0>; 393 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&hsi2c8_bus>; 398 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, 399 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; 400 clock-names = "hsi2c", "hsi2c_pclk"; 401 status = "disabled"; 402 }; 403 }; 404 405 usi_uart: usi@10a000c0 { 406 compatible = "google,gs101-usi", 407 "samsung,exynos850-usi"; 408 reg = <0x10a000c0 0x20>; 409 ranges; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 413 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 414 clock-names = "pclk", "ipclk"; 415 samsung,sysreg = <&sysreg_peric0 0x1020>; 416 samsung,mode = <USI_V2_UART>; 417 status = "disabled"; 418 419 serial_0: serial@10a00000 { 420 compatible = "google,gs101-uart"; 421 reg = <0x10a00000 0xc0>; 422 interrupts = <GIC_SPI 634 423 IRQ_TYPE_LEVEL_HIGH 0>; 424 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 425 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 426 clock-names = "uart", "clk_uart_baud0"; 427 samsung,uart-fifosize = <256>; 428 status = "disabled"; 429 }; 430 }; 431 432 cmu_peric1: clock-controller@10c00000 { 433 compatible = "google,gs101-cmu-peric1"; 434 reg = <0x10c00000 0x4000>; 435 #clock-cells = <1>; 436 clocks = <&ext_24_5m>, 437 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 438 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 439 clock-names = "oscclk", "bus", "ip"; 440 }; 441 442 sysreg_peric1: syscon@10c20000 { 443 compatible = "google,gs101-peric1-sysreg", "syscon"; 444 reg = <0x10c20000 0x10000>; 445 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 446 }; 447 448 pinctrl_peric1: pinctrl@10c40000 { 449 compatible = "google,gs101-pinctrl"; 450 reg = <0x10c40000 0x00001000>; 451 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 452 }; 453 454 usi12: usi@10d500c0 { 455 compatible = "google,gs101-usi", 456 "samsung,exynos850-usi"; 457 reg = <0x10d500c0 0x20>; 458 ranges; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 462 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 463 clock-names = "pclk", "ipclk"; 464 samsung,sysreg = <&sysreg_peric1 0x1010>; 465 status = "disabled"; 466 467 hsi2c_12: i2c@10d50000 { 468 compatible = "google,gs101-hsi2c", 469 "samsung,exynosautov9-hsi2c"; 470 reg = <0x10d50000 0xc0>; 471 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 pinctrl-0 = <&hsi2c12_bus>; 475 pinctrl-names = "default"; 476 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, 477 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; 478 clock-names = "hsi2c", "hsi2c_pclk"; 479 status = "disabled"; 480 }; 481 }; 482 483 pinctrl_hsi1: pinctrl@11840000 { 484 compatible = "google,gs101-pinctrl"; 485 reg = <0x11840000 0x00001000>; 486 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 487 }; 488 489 pinctrl_hsi2: pinctrl@14440000 { 490 compatible = "google,gs101-pinctrl"; 491 reg = <0x14440000 0x00001000>; 492 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 493 }; 494 495 cmu_apm: clock-controller@17400000 { 496 compatible = "google,gs101-cmu-apm"; 497 reg = <0x17400000 0x8000>; 498 #clock-cells = <1>; 499 500 clocks = <&ext_24_5m>; 501 clock-names = "oscclk"; 502 }; 503 504 sysreg_apm: syscon@174204e0 { 505 compatible = "google,gs101-apm-sysreg", "syscon"; 506 reg = <0x174204e0 0x1000>; 507 }; 508 509 pmu_system_controller: system-controller@17460000 { 510 compatible = "google,gs101-pmu", "syscon"; 511 reg = <0x17460000 0x10000>; 512 }; 513 514 pinctrl_gpio_alive: pinctrl@174d0000 { 515 compatible = "google,gs101-pinctrl"; 516 reg = <0x174d0000 0x00001000>; 517 518 wakeup-interrupt-controller { 519 compatible = "google,gs101-wakeup-eint", 520 "samsung,exynos850-wakeup-eint", 521 "samsung,exynos7-wakeup-eint"; 522 }; 523 }; 524 525 pinctrl_far_alive: pinctrl@174e0000 { 526 compatible = "google,gs101-pinctrl"; 527 reg = <0x174e0000 0x00001000>; 528 529 wakeup-interrupt-controller { 530 compatible = "google,gs101-wakeup-eint", 531 "samsung,exynos850-wakeup-eint", 532 "samsung,exynos7-wakeup-eint"; 533 }; 534 }; 535 536 pinctrl_gsactrl: pinctrl@17940000 { 537 compatible = "google,gs101-pinctrl"; 538 reg = <0x17940000 0x00001000>; 539 }; 540 541 pinctrl_gsacore: pinctrl@17a80000 { 542 compatible = "google,gs101-pinctrl"; 543 reg = <0x17a80000 0x00001000>; 544 }; 545 546 cmu_top: clock-controller@1e080000 { 547 compatible = "google,gs101-cmu-top"; 548 reg = <0x1e080000 0x8000>; 549 #clock-cells = <1>; 550 551 clocks = <&ext_24_5m>; 552 clock-names = "oscclk"; 553 }; 554 }; 555 556 timer { 557 compatible = "arm,armv8-timer"; 558 interrupts = 559 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 560 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 561 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 562 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 563 }; 564}; 565 566#include "gs101-pinctrl.dtsi" 567