1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GS101 SoC 4 * 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 */ 8 9#include <dt-bindings/clock/google,gs101.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "google,gs101"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_gpio_alive; 23 pinctrl1 = &pinctrl_far_alive; 24 pinctrl2 = &pinctrl_gsacore; 25 pinctrl3 = &pinctrl_gsactrl; 26 pinctrl4 = &pinctrl_peric0; 27 pinctrl5 = &pinctrl_peric1; 28 pinctrl6 = &pinctrl_hsi1; 29 pinctrl7 = &pinctrl_hsi2; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu-map { 37 cluster0 { 38 core0 { 39 cpu = <&cpu0>; 40 }; 41 core1 { 42 cpu = <&cpu1>; 43 }; 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 core3 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu4>; 55 }; 56 core1 { 57 cpu = <&cpu5>; 58 }; 59 }; 60 61 cluster2 { 62 core0 { 63 cpu = <&cpu6>; 64 }; 65 core1 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0000>; 75 enable-method = "psci"; 76 cpu-idle-states = <&ananke_cpu_sleep>; 77 capacity-dmips-mhz = <250>; 78 dynamic-power-coefficient = <70>; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a55"; 84 reg = <0x0100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&ananke_cpu_sleep>; 87 capacity-dmips-mhz = <250>; 88 dynamic-power-coefficient = <70>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0200>; 95 enable-method = "psci"; 96 cpu-idle-states = <&ananke_cpu_sleep>; 97 capacity-dmips-mhz = <250>; 98 dynamic-power-coefficient = <70>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0300>; 105 enable-method = "psci"; 106 cpu-idle-states = <&ananke_cpu_sleep>; 107 capacity-dmips-mhz = <250>; 108 dynamic-power-coefficient = <70>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a76"; 114 reg = <0x0400>; 115 enable-method = "psci"; 116 cpu-idle-states = <&enyo_cpu_sleep>; 117 capacity-dmips-mhz = <620>; 118 dynamic-power-coefficient = <284>; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a76"; 124 reg = <0x0500>; 125 enable-method = "psci"; 126 cpu-idle-states = <&enyo_cpu_sleep>; 127 capacity-dmips-mhz = <620>; 128 dynamic-power-coefficient = <284>; 129 }; 130 131 cpu6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-x1"; 134 reg = <0x0600>; 135 enable-method = "psci"; 136 cpu-idle-states = <&hera_cpu_sleep>; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <650>; 139 }; 140 141 cpu7: cpu@700 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-x1"; 144 reg = <0x0700>; 145 enable-method = "psci"; 146 cpu-idle-states = <&hera_cpu_sleep>; 147 capacity-dmips-mhz = <1024>; 148 dynamic-power-coefficient = <650>; 149 }; 150 151 idle-states { 152 entry-method = "psci"; 153 154 ananke_cpu_sleep: cpu-ananke-sleep { 155 idle-state-name = "c2"; 156 compatible = "arm,idle-state"; 157 arm,psci-suspend-param = <0x0010000>; 158 local-timer-stop; 159 entry-latency-us = <70>; 160 exit-latency-us = <160>; 161 min-residency-us = <2000>; 162 }; 163 164 enyo_cpu_sleep: cpu-enyo-sleep { 165 idle-state-name = "c2"; 166 compatible = "arm,idle-state"; 167 arm,psci-suspend-param = <0x0010000>; 168 local-timer-stop; 169 entry-latency-us = <150>; 170 exit-latency-us = <190>; 171 min-residency-us = <2500>; 172 }; 173 174 hera_cpu_sleep: cpu-hera-sleep { 175 idle-state-name = "c2"; 176 compatible = "arm,idle-state"; 177 arm,psci-suspend-param = <0x0010000>; 178 local-timer-stop; 179 entry-latency-us = <235>; 180 exit-latency-us = <220>; 181 min-residency-us = <3500>; 182 }; 183 }; 184 }; 185 186 /* ect node is required to be present by bootloader */ 187 ect { 188 }; 189 190 ext_24_5m: clock-1 { 191 compatible = "fixed-clock"; 192 #clock-cells = <0>; 193 clock-output-names = "oscclk"; 194 }; 195 196 ext_200m: clock-2 { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-output-names = "ext-200m"; 200 }; 201 202 firmware { 203 acpm_ipc: power-management { 204 compatible = "google,gs101-acpm-ipc"; 205 mboxes = <&ap2apm_mailbox>; 206 shmem = <&apm_sram>; 207 }; 208 }; 209 210 pmu-0 { 211 compatible = "arm,cortex-a55-pmu"; 212 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 213 }; 214 215 pmu-1 { 216 compatible = "arm,cortex-a76-pmu"; 217 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 218 }; 219 220 pmu-2 { 221 compatible = "arm,cortex-x1-pmu"; 222 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 223 }; 224 225 pmu-3 { 226 compatible = "arm,dsu-pmu"; 227 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 228 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 229 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; 230 }; 231 232 psci { 233 compatible = "arm,psci-1.0"; 234 method = "smc"; 235 }; 236 237 reserved_memory: reserved-memory { 238 #address-cells = <2>; 239 #size-cells = <1>; 240 ranges; 241 242 gsa_reserved_protected: gsa@90200000 { 243 reg = <0x0 0x90200000 0x400000>; 244 no-map; 245 }; 246 247 tpu_fw_reserved: tpu-fw@93000000 { 248 reg = <0x0 0x93000000 0x1000000>; 249 no-map; 250 }; 251 252 aoc_reserve: aoc@94000000 { 253 reg = <0x0 0x94000000 0x03000000>; 254 no-map; 255 }; 256 257 abl_reserved: abl@f8800000 { 258 reg = <0x0 0xf8800000 0x02000000>; 259 no-map; 260 }; 261 262 dss_log_reserved: dss-log-reserved@fd3f0000 { 263 reg = <0x0 0xfd3f0000 0x0000e000>; 264 no-map; 265 }; 266 267 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { 268 reg = <0x0 0xfd3fe000 0x00001000>; 269 no-map; 270 }; 271 272 bldr_log_reserved: bldr-log-reserved@fd800000 { 273 reg = <0x0 0xfd800000 0x00100000>; 274 no-map; 275 }; 276 277 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { 278 reg = <0x0 0xfd900000 0x00002000>; 279 no-map; 280 }; 281 }; 282 283 soc: soc@0 { 284 compatible = "simple-bus"; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges = <0x0 0x0 0x0 0x40000000>; 288 289 cmu_misc: clock-controller@10010000 { 290 compatible = "google,gs101-cmu-misc"; 291 reg = <0x10010000 0x8000>; 292 #clock-cells = <1>; 293 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, 294 <&cmu_top CLK_DOUT_CMU_MISC_SSS>; 295 clock-names = "bus", "sss"; 296 }; 297 298 timer@10050000 { 299 compatible = "google,gs101-mct", 300 "samsung,exynos4210-mct"; 301 reg = <0x10050000 0x800>; 302 clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; 303 clock-names = "fin_pll", "mct"; 304 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, 305 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, 306 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, 307 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, 308 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, 309 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, 310 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, 311 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, 312 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, 313 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, 314 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, 315 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; 316 }; 317 318 watchdog_cl0: watchdog@10060000 { 319 compatible = "google,gs101-wdt"; 320 reg = <0x10060000 0x100>; 321 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, 322 <&ext_24_5m>; 323 clock-names = "watchdog", "watchdog_src"; 324 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; 325 samsung,syscon-phandle = <&pmu_system_controller>; 326 samsung,cluster-index = <0>; 327 status = "disabled"; 328 }; 329 330 watchdog_cl1: watchdog@10070000 { 331 compatible = "google,gs101-wdt"; 332 reg = <0x10070000 0x100>; 333 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, 334 <&ext_24_5m>; 335 clock-names = "watchdog", "watchdog_src"; 336 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; 337 samsung,syscon-phandle = <&pmu_system_controller>; 338 samsung,cluster-index = <1>; 339 status = "disabled"; 340 }; 341 342 gic: interrupt-controller@10400000 { 343 compatible = "arm,gic-v3"; 344 #interrupt-cells = <4>; 345 interrupt-controller; 346 reg = <0x10400000 0x10000>, /* GICD */ 347 <0x10440000 0x100000>;/* GICR * 8 */ 348 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 349 350 ppi-partitions { 351 ppi_cluster0: interrupt-partition-0 { 352 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 353 }; 354 355 ppi_cluster1: interrupt-partition-1 { 356 affinity = <&cpu4 &cpu5>; 357 }; 358 359 ppi_cluster2: interrupt-partition-2 { 360 affinity = <&cpu6 &cpu7>; 361 }; 362 }; 363 }; 364 365 cmu_peric0: clock-controller@10800000 { 366 compatible = "google,gs101-cmu-peric0"; 367 reg = <0x10800000 0x4000>; 368 #clock-cells = <1>; 369 clocks = <&ext_24_5m>, 370 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 371 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 372 clock-names = "oscclk", "bus", "ip"; 373 }; 374 375 sysreg_peric0: syscon@10820000 { 376 compatible = "google,gs101-peric0-sysreg", "syscon"; 377 reg = <0x10820000 0x10000>; 378 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 379 }; 380 381 pinctrl_peric0: pinctrl@10840000 { 382 compatible = "google,gs101-pinctrl"; 383 reg = <0x10840000 0x00001000>; 384 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; 385 clock-names = "pclk"; 386 interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; 387 }; 388 389 usi1: usi@109000c0 { 390 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 391 reg = <0x109000c0 0x20>; 392 ranges; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 396 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 397 clock-names = "pclk", "ipclk"; 398 samsung,sysreg = <&sysreg_peric0 0x1000>; 399 status = "disabled"; 400 401 hsi2c_1: i2c@10900000 { 402 compatible = "google,gs101-hsi2c", 403 "samsung,exynosautov9-hsi2c"; 404 reg = <0x10900000 0xc0>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, 408 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; 409 clock-names = "hsi2c", "hsi2c_pclk"; 410 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 411 pinctrl-0 = <&hsi2c1_bus>; 412 pinctrl-names = "default"; 413 status = "disabled"; 414 }; 415 416 serial_1: serial@10900000 { 417 compatible = "google,gs101-uart"; 418 reg = <0x10900000 0xc0>; 419 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 420 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 421 clock-names = "uart", "clk_uart_baud0"; 422 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 423 pinctrl-0 = <&uart1_bus_single>; 424 pinctrl-names = "default"; 425 samsung,uart-fifosize = <64>; 426 status = "disabled"; 427 }; 428 429 spi_1: spi@10900000 { 430 compatible = "google,gs101-spi"; 431 reg = <0x10900000 0x30>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 435 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 436 clock-names = "spi", "spi_busclk0"; 437 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 438 pinctrl-0 = <&spi1_bus>; 439 pinctrl-names = "default"; 440 status = "disabled"; 441 }; 442 }; 443 444 usi2: usi@109100c0 { 445 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 446 reg = <0x109100c0 0x20>; 447 ranges; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 451 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 452 clock-names = "pclk", "ipclk"; 453 samsung,sysreg = <&sysreg_peric0 0x1004>; 454 status = "disabled"; 455 456 hsi2c_2: i2c@10910000 { 457 compatible = "google,gs101-hsi2c", 458 "samsung,exynosautov9-hsi2c"; 459 reg = <0x10910000 0xc0>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, 463 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; 464 clock-names = "hsi2c", "hsi2c_pclk"; 465 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 466 pinctrl-0 = <&hsi2c2_bus>; 467 pinctrl-names = "default"; 468 status = "disabled"; 469 }; 470 471 serial_2: serial@10910000 { 472 compatible = "google,gs101-uart"; 473 reg = <0x10910000 0xc0>; 474 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 475 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 476 clock-names = "uart", "clk_uart_baud0"; 477 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 478 pinctrl-0 = <&uart2_bus_single>; 479 pinctrl-names = "default"; 480 samsung,uart-fifosize = <64>; 481 status = "disabled"; 482 }; 483 484 spi_2: spi@10910000 { 485 compatible = "google,gs101-spi"; 486 reg = <0x10910000 0x30>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 490 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 491 clock-names = "spi", "spi_busclk0"; 492 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 493 pinctrl-0 = <&spi2_bus>; 494 pinctrl-names = "default"; 495 status = "disabled"; 496 }; 497 }; 498 499 usi3: usi@109200c0 { 500 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 501 reg = <0x109200c0 0x20>; 502 ranges; 503 #address-cells = <1>; 504 #size-cells = <1>; 505 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 506 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 507 clock-names = "pclk", "ipclk"; 508 samsung,sysreg = <&sysreg_peric0 0x1008>; 509 status = "disabled"; 510 511 hsi2c_3: i2c@10920000 { 512 compatible = "google,gs101-hsi2c", 513 "samsung,exynosautov9-hsi2c"; 514 reg = <0x10920000 0xc0>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, 518 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; 519 clock-names = "hsi2c", "hsi2c_pclk"; 520 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 521 pinctrl-0 = <&hsi2c3_bus>; 522 pinctrl-names = "default"; 523 status = "disabled"; 524 }; 525 526 serial_3: serial@10920000 { 527 compatible = "google,gs101-uart"; 528 reg = <0x10920000 0xc0>; 529 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 530 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 531 clock-names = "uart", "clk_uart_baud0"; 532 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 533 pinctrl-0 = <&uart3_bus_single>; 534 pinctrl-names = "default"; 535 samsung,uart-fifosize = <64>; 536 status = "disabled"; 537 }; 538 539 spi_3: spi@10920000 { 540 compatible = "google,gs101-spi"; 541 reg = <0x10920000 0x30>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 545 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 546 clock-names = "spi", "spi_busclk0"; 547 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 548 pinctrl-0 = <&spi3_bus>; 549 pinctrl-names = "default"; 550 status = "disabled"; 551 }; 552 }; 553 554 usi4: usi@109300c0 { 555 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 556 reg = <0x109300c0 0x20>; 557 ranges; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 561 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 562 clock-names = "pclk", "ipclk"; 563 samsung,sysreg = <&sysreg_peric0 0x100c>; 564 status = "disabled"; 565 566 hsi2c_4: i2c@10930000 { 567 compatible = "google,gs101-hsi2c", 568 "samsung,exynosautov9-hsi2c"; 569 reg = <0x10930000 0xc0>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, 573 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; 574 clock-names = "hsi2c", "hsi2c_pclk"; 575 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 576 pinctrl-0 = <&hsi2c4_bus>; 577 pinctrl-names = "default"; 578 status = "disabled"; 579 }; 580 581 serial_4: serial@10930000 { 582 compatible = "google,gs101-uart"; 583 reg = <0x10930000 0xc0>; 584 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 585 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 586 clock-names = "uart", "clk_uart_baud0"; 587 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 588 pinctrl-0 = <&uart4_bus_single>; 589 pinctrl-names = "default"; 590 samsung,uart-fifosize = <64>; 591 status = "disabled"; 592 }; 593 594 spi_4: spi@10930000 { 595 compatible = "google,gs101-spi"; 596 reg = <0x10930000 0x30>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 600 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 601 clock-names = "spi", "spi_busclk0"; 602 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 603 pinctrl-0 = <&spi4_bus>; 604 pinctrl-names = "default"; 605 status = "disabled"; 606 }; 607 }; 608 609 usi5: usi@109400c0 { 610 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 611 reg = <0x109400c0 0x20>; 612 ranges; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 616 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 617 clock-names = "pclk", "ipclk"; 618 samsung,sysreg = <&sysreg_peric0 0x1010>; 619 status = "disabled"; 620 621 hsi2c_5: i2c@10940000 { 622 compatible = "google,gs101-hsi2c", 623 "samsung,exynosautov9-hsi2c"; 624 reg = <0x10940000 0xc0>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, 628 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; 629 clock-names = "hsi2c", "hsi2c_pclk"; 630 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 631 pinctrl-0 = <&hsi2c5_bus>; 632 pinctrl-names = "default"; 633 status = "disabled"; 634 }; 635 636 serial_5: serial@10940000 { 637 compatible = "google,gs101-uart"; 638 reg = <0x10940000 0xc0>; 639 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 640 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 641 clock-names = "uart", "clk_uart_baud0"; 642 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 643 pinctrl-0 = <&uart5_bus_single>; 644 pinctrl-names = "default"; 645 samsung,uart-fifosize = <64>; 646 status = "disabled"; 647 }; 648 649 spi_5: spi@10940000 { 650 compatible = "google,gs101-spi"; 651 reg = <0x10940000 0x30>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 655 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 656 clock-names = "spi", "spi_busclk0"; 657 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 658 pinctrl-0 = <&spi5_bus>; 659 pinctrl-names = "default"; 660 status = "disabled"; 661 }; 662 }; 663 664 usi6: usi@109500c0 { 665 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 666 reg = <0x109500c0 0x20>; 667 ranges; 668 #address-cells = <1>; 669 #size-cells = <1>; 670 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 671 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 672 clock-names = "pclk", "ipclk"; 673 samsung,sysreg = <&sysreg_peric0 0x1014>; 674 status = "disabled"; 675 676 hsi2c_6: i2c@10950000 { 677 compatible = "google,gs101-hsi2c", 678 "samsung,exynosautov9-hsi2c"; 679 reg = <0x10950000 0xc0>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, 683 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; 684 clock-names = "hsi2c", "hsi2c_pclk"; 685 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 686 pinctrl-0 = <&hsi2c6_bus>; 687 pinctrl-names = "default"; 688 status = "disabled"; 689 }; 690 691 serial_6: serial@10950000 { 692 compatible = "google,gs101-uart"; 693 reg = <0x10950000 0xc0>; 694 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 695 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 696 clock-names = "uart", "clk_uart_baud0"; 697 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 698 pinctrl-0 = <&uart6_bus_single>; 699 pinctrl-names = "default"; 700 samsung,uart-fifosize = <64>; 701 status = "disabled"; 702 }; 703 704 spi_6: spi@10950000 { 705 compatible = "google,gs101-spi"; 706 reg = <0x10950000 0x30>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 710 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 711 clock-names = "spi", "spi_busclk0"; 712 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 713 pinctrl-0 = <&spi6_bus>; 714 pinctrl-names = "default"; 715 status = "disabled"; 716 }; 717 }; 718 719 usi7: usi@109600c0 { 720 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 721 reg = <0x109600c0 0x20>; 722 ranges; 723 #address-cells = <1>; 724 #size-cells = <1>; 725 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 726 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 727 clock-names = "pclk", "ipclk"; 728 samsung,sysreg = <&sysreg_peric0 0x1018>; 729 status = "disabled"; 730 731 hsi2c_7: i2c@10960000 { 732 compatible = "google,gs101-hsi2c", 733 "samsung,exynosautov9-hsi2c"; 734 reg = <0x10960000 0xc0>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, 738 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; 739 clock-names = "hsi2c", "hsi2c_pclk"; 740 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 741 pinctrl-0 = <&hsi2c7_bus>; 742 pinctrl-names = "default"; 743 status = "disabled"; 744 }; 745 746 serial_7: serial@10960000 { 747 compatible = "google,gs101-uart"; 748 reg = <0x10960000 0xc0>; 749 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 750 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 751 clock-names = "uart", "clk_uart_baud0"; 752 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 753 pinctrl-0 = <&uart7_bus_single>; 754 pinctrl-names = "default"; 755 samsung,uart-fifosize = <64>; 756 status = "disabled"; 757 }; 758 759 spi_7: spi@10960000 { 760 compatible = "google,gs101-spi"; 761 reg = <0x10960000 0x30>; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 765 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 766 clock-names = "spi", "spi_busclk0"; 767 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 768 pinctrl-0 = <&spi7_bus>; 769 pinctrl-names = "default"; 770 status = "disabled"; 771 }; 772 }; 773 774 usi8: usi@109700c0 { 775 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 776 reg = <0x109700c0 0x20>; 777 ranges; 778 #address-cells = <1>; 779 #size-cells = <1>; 780 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 781 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 782 clock-names = "pclk", "ipclk"; 783 samsung,sysreg = <&sysreg_peric0 0x101c>; 784 status = "disabled"; 785 786 hsi2c_8: i2c@10970000 { 787 compatible = "google,gs101-hsi2c", 788 "samsung,exynosautov9-hsi2c"; 789 reg = <0x10970000 0xc0>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, 793 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; 794 clock-names = "hsi2c", "hsi2c_pclk"; 795 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 796 pinctrl-0 = <&hsi2c8_bus>; 797 pinctrl-names = "default"; 798 status = "disabled"; 799 }; 800 801 serial_8: serial@10970000 { 802 compatible = "google,gs101-uart"; 803 reg = <0x10970000 0xc0>; 804 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 805 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 806 clock-names = "uart", "clk_uart_baud0"; 807 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 808 pinctrl-0 = <&uart8_bus_single>; 809 pinctrl-names = "default"; 810 samsung,uart-fifosize = <64>; 811 status = "disabled"; 812 }; 813 814 spi_8: spi@10970000 { 815 compatible = "google,gs101-spi"; 816 reg = <0x10970000 0x30>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 820 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 821 clock-names = "spi", "spi_busclk0"; 822 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 823 pinctrl-0 = <&spi8_bus>; 824 pinctrl-names = "default"; 825 status = "disabled"; 826 }; 827 }; 828 829 usi_uart: usi@10a000c0 { 830 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 831 reg = <0x10a000c0 0x20>; 832 ranges; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 836 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 837 clock-names = "pclk", "ipclk"; 838 samsung,sysreg = <&sysreg_peric0 0x1020>; 839 samsung,mode = <USI_MODE_UART>; 840 status = "disabled"; 841 842 serial_0: serial@10a00000 { 843 compatible = "google,gs101-uart"; 844 reg = <0x10a00000 0xc0>; 845 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 846 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 847 clock-names = "uart", "clk_uart_baud0"; 848 interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; 849 pinctrl-0 = <&uart0_bus>; 850 pinctrl-names = "default"; 851 samsung,uart-fifosize = <256>; 852 status = "disabled"; 853 }; 854 }; 855 856 usi14: usi@10a200c0 { 857 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 858 reg = <0x10a200c0 0x20>; 859 ranges; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 863 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 864 clock-names = "pclk", "ipclk"; 865 samsung,sysreg = <&sysreg_peric0 0x1028>; 866 status = "disabled"; 867 868 hsi2c_14: i2c@10a20000 { 869 compatible = "google,gs101-hsi2c", 870 "samsung,exynosautov9-hsi2c"; 871 reg = <0x10a20000 0xc0>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, 875 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; 876 clock-names = "hsi2c", "hsi2c_pclk"; 877 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 878 pinctrl-0 = <&hsi2c14_bus>; 879 pinctrl-names = "default"; 880 status = "disabled"; 881 }; 882 883 serial_14: serial@10a20000 { 884 compatible = "google,gs101-uart"; 885 reg = <0x10a20000 0xc0>; 886 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 887 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 888 clock-names = "uart", "clk_uart_baud0"; 889 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 890 pinctrl-0 = <&uart14_bus_single>; 891 pinctrl-names = "default"; 892 samsung,uart-fifosize = <64>; 893 status = "disabled"; 894 }; 895 896 spi_14: spi@10a20000 { 897 compatible = "google,gs101-spi"; 898 reg = <0x10a20000 0x30>; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 902 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 903 clock-names = "spi", "spi_busclk0"; 904 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 905 pinctrl-0 = <&spi14_bus>; 906 pinctrl-names = "default"; 907 status = "disabled"; 908 }; 909 }; 910 911 cmu_peric1: clock-controller@10c00000 { 912 compatible = "google,gs101-cmu-peric1"; 913 reg = <0x10c00000 0x4000>; 914 #clock-cells = <1>; 915 clocks = <&ext_24_5m>, 916 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 917 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 918 clock-names = "oscclk", "bus", "ip"; 919 }; 920 921 sysreg_peric1: syscon@10c20000 { 922 compatible = "google,gs101-peric1-sysreg", "syscon"; 923 reg = <0x10c20000 0x10000>; 924 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 925 }; 926 927 pinctrl_peric1: pinctrl@10c40000 { 928 compatible = "google,gs101-pinctrl"; 929 reg = <0x10c40000 0x00001000>; 930 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; 931 clock-names = "pclk"; 932 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 933 }; 934 935 usi0: usi@10d100c0 { 936 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 937 reg = <0x10d100c0 0x20>; 938 ranges; 939 #address-cells = <1>; 940 #size-cells = <1>; 941 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 942 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 943 clock-names = "pclk", "ipclk"; 944 samsung,sysreg = <&sysreg_peric1 0x1000>; 945 status = "disabled"; 946 947 hsi2c_0: i2c@10d10000 { 948 compatible = "google,gs101-hsi2c", 949 "samsung,exynosautov9-hsi2c"; 950 reg = <0x10d10000 0xc0>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, 954 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; 955 clock-names = "hsi2c", "hsi2c_pclk"; 956 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 957 pinctrl-0 = <&hsi2c0_bus>; 958 pinctrl-names = "default"; 959 status = "disabled"; 960 }; 961 962 serial_usi0: serial@10d10000 { 963 compatible = "google,gs101-uart"; 964 reg = <0x10d10000 0xc0>; 965 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 966 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 967 clock-names = "uart", "clk_uart_baud0"; 968 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 969 pinctrl-0 = <&uart0_bus_single>; 970 pinctrl-names = "default"; 971 samsung,uart-fifosize = <64>; 972 status = "disabled"; 973 }; 974 975 spi_0: spi@10d10000 { 976 compatible = "google,gs101-spi"; 977 reg = <0x10d10000 0x30>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 981 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 982 clock-names = "spi", "spi_busclk0"; 983 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 984 pinctrl-0 = <&spi0_bus>; 985 pinctrl-names = "default"; 986 status = "disabled"; 987 }; 988 }; 989 990 usi9: usi@10d200c0 { 991 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 992 reg = <0x10d200c0 0x20>; 993 ranges; 994 #address-cells = <1>; 995 #size-cells = <1>; 996 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 997 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 998 clock-names = "pclk", "ipclk"; 999 samsung,sysreg = <&sysreg_peric1 0x1004>; 1000 status = "disabled"; 1001 1002 hsi2c_9: i2c@10d20000 { 1003 compatible = "google,gs101-hsi2c", 1004 "samsung,exynosautov9-hsi2c"; 1005 reg = <0x10d20000 0xc0>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, 1009 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; 1010 clock-names = "hsi2c", "hsi2c_pclk"; 1011 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1012 pinctrl-0 = <&hsi2c9_bus>; 1013 pinctrl-names = "default"; 1014 status = "disabled"; 1015 }; 1016 1017 serial_9: serial@10d20000 { 1018 compatible = "google,gs101-uart"; 1019 reg = <0x10d20000 0xc0>; 1020 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1021 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1022 clock-names = "uart", "clk_uart_baud0"; 1023 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1024 pinctrl-0 = <&uart9_bus_single>; 1025 pinctrl-names = "default"; 1026 samsung,uart-fifosize = <64>; 1027 status = "disabled"; 1028 }; 1029 1030 spi_9: spi@10d20000 { 1031 compatible = "google,gs101-spi"; 1032 reg = <0x10d20000 0x30>; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1036 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1037 clock-names = "spi", "spi_busclk0"; 1038 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1039 pinctrl-0 = <&spi9_bus>; 1040 pinctrl-names = "default"; 1041 status = "disabled"; 1042 }; 1043 }; 1044 1045 usi10: usi@10d300c0 { 1046 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1047 reg = <0x10d300c0 0x20>; 1048 ranges; 1049 #address-cells = <1>; 1050 #size-cells = <1>; 1051 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1052 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1053 clock-names = "pclk", "ipclk"; 1054 samsung,sysreg = <&sysreg_peric1 0x1008>; 1055 status = "disabled"; 1056 1057 hsi2c_10: i2c@10d30000 { 1058 compatible = "google,gs101-hsi2c", 1059 "samsung,exynosautov9-hsi2c"; 1060 reg = <0x10d30000 0xc0>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, 1064 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; 1065 clock-names = "hsi2c", "hsi2c_pclk"; 1066 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1067 pinctrl-0 = <&hsi2c10_bus>; 1068 pinctrl-names = "default"; 1069 status = "disabled"; 1070 }; 1071 1072 serial_10: serial@10d30000 { 1073 compatible = "google,gs101-uart"; 1074 reg = <0x10d30000 0xc0>; 1075 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1076 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1077 clock-names = "uart", "clk_uart_baud0"; 1078 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1079 pinctrl-0 = <&uart10_bus_single>; 1080 pinctrl-names = "default"; 1081 samsung,uart-fifosize = <64>; 1082 status = "disabled"; 1083 }; 1084 1085 spi_10: spi@10d30000 { 1086 compatible = "google,gs101-spi"; 1087 reg = <0x10d30000 0x30>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1091 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1092 clock-names = "spi", "spi_busclk0"; 1093 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1094 pinctrl-0 = <&spi10_bus>; 1095 pinctrl-names = "default"; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 usi11: usi@10d400c0 { 1101 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1102 reg = <0x10d400c0 0x20>; 1103 ranges; 1104 #address-cells = <1>; 1105 #size-cells = <1>; 1106 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1107 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1108 clock-names = "pclk", "ipclk"; 1109 samsung,sysreg = <&sysreg_peric1 0x100c>; 1110 status = "disabled"; 1111 1112 hsi2c_11: i2c@10d40000 { 1113 compatible = "google,gs101-hsi2c", 1114 "samsung,exynosautov9-hsi2c"; 1115 reg = <0x10d40000 0xc0>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, 1119 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; 1120 clock-names = "hsi2c", "hsi2c_pclk"; 1121 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1122 pinctrl-0 = <&hsi2c11_bus>; 1123 pinctrl-names = "default"; 1124 status = "disabled"; 1125 }; 1126 1127 serial_11: serial@10d40000 { 1128 compatible = "google,gs101-uart"; 1129 reg = <0x10d40000 0xc0>; 1130 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1131 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1132 clock-names = "uart", "clk_uart_baud0"; 1133 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1134 pinctrl-0 = <&uart11_bus_single>; 1135 pinctrl-names = "default"; 1136 samsung,uart-fifosize = <64>; 1137 status = "disabled"; 1138 }; 1139 1140 spi_11: spi@10d40000 { 1141 compatible = "google,gs101-spi"; 1142 reg = <0x10d40000 0x30>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1146 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1147 clock-names = "spi", "spi_busclk0"; 1148 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1149 pinctrl-0 = <&spi11_bus>; 1150 pinctrl-names = "default"; 1151 status = "disabled"; 1152 }; 1153 }; 1154 1155 usi12: usi@10d500c0 { 1156 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1157 reg = <0x10d500c0 0x20>; 1158 ranges; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1162 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1163 clock-names = "pclk", "ipclk"; 1164 samsung,sysreg = <&sysreg_peric1 0x1010>; 1165 status = "disabled"; 1166 1167 hsi2c_12: i2c@10d50000 { 1168 compatible = "google,gs101-hsi2c", 1169 "samsung,exynosautov9-hsi2c"; 1170 reg = <0x10d50000 0xc0>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, 1174 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; 1175 clock-names = "hsi2c", "hsi2c_pclk"; 1176 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1177 pinctrl-0 = <&hsi2c12_bus>; 1178 pinctrl-names = "default"; 1179 status = "disabled"; 1180 }; 1181 1182 serial_12: serial@10d50000 { 1183 compatible = "google,gs101-uart"; 1184 reg = <0x10d50000 0xc0>; 1185 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1186 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1187 clock-names = "uart", "clk_uart_baud0"; 1188 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1189 pinctrl-0 = <&uart12_bus_single>; 1190 pinctrl-names = "default"; 1191 samsung,uart-fifosize = <64>; 1192 status = "disabled"; 1193 }; 1194 1195 spi_12: spi@10d50000 { 1196 compatible = "google,gs101-spi"; 1197 reg = <0x10d50000 0x30>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1201 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1202 clock-names = "spi", "spi_busclk0"; 1203 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1204 pinctrl-0 = <&spi12_bus>; 1205 pinctrl-names = "default"; 1206 status = "disabled"; 1207 }; 1208 }; 1209 1210 usi13: usi@10d600c0 { 1211 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1212 reg = <0x10d600c0 0x20>; 1213 ranges; 1214 #address-cells = <1>; 1215 #size-cells = <1>; 1216 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1217 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1218 clock-names = "pclk", "ipclk"; 1219 samsung,sysreg = <&sysreg_peric1 0x1014>; 1220 status = "disabled"; 1221 1222 hsi2c_13: i2c@10d60000 { 1223 compatible = "google,gs101-hsi2c", 1224 "samsung,exynosautov9-hsi2c"; 1225 reg = <0x10d60000 0xc0>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, 1229 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; 1230 clock-names = "hsi2c", "hsi2c_pclk"; 1231 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1232 pinctrl-0 = <&hsi2c13_bus>; 1233 pinctrl-names = "default"; 1234 status = "disabled"; 1235 }; 1236 1237 serial_13: serial@10d60000 { 1238 compatible = "google,gs101-uart"; 1239 reg = <0x10d60000 0xc0>; 1240 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1241 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1242 clock-names = "uart", "clk_uart_baud0"; 1243 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1244 pinctrl-0 = <&uart13_bus_single>; 1245 pinctrl-names = "default"; 1246 samsung,uart-fifosize = <64>; 1247 status = "disabled"; 1248 }; 1249 1250 spi_13: spi@10d60000 { 1251 compatible = "google,gs101-spi"; 1252 reg = <0x10d60000 0x30>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1256 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1257 clock-names = "spi", "spi_busclk0"; 1258 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1259 pinctrl-0 = <&spi13_bus>; 1260 pinctrl-names = "default"; 1261 status = "disabled"; 1262 }; 1263 }; 1264 1265 cmu_hsi0: clock-controller@11000000 { 1266 compatible = "google,gs101-cmu-hsi0"; 1267 reg = <0x11000000 0x4000>; 1268 #clock-cells = <1>; 1269 1270 clocks = <&ext_24_5m>, 1271 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, 1272 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, 1273 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, 1274 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; 1275 clock-names = "oscclk", "bus", "dpgtc", "usb31drd", 1276 "usbdpdbg"; 1277 }; 1278 1279 usbdrd31_phy: phy@11100000 { 1280 compatible = "google,gs101-usb31drd-phy"; 1281 reg = <0x11100000 0x0200>, 1282 <0x110f0000 0x0800>, 1283 <0x110e0000 0x2800>; 1284 reg-names = "phy", "pcs", "pma"; 1285 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, 1286 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, 1287 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, 1288 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, 1289 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; 1290 clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; 1291 #phy-cells = <1>; 1292 samsung,pmu-syscon = <&pmu_system_controller>; 1293 status = "disabled"; 1294 }; 1295 1296 usbdrd31: usb@11110000 { 1297 compatible = "google,gs101-dwusb3"; 1298 ranges = <0x0 0x11110000 0x10000>; 1299 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, 1300 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, 1301 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, 1302 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; 1303 clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; 1304 #address-cells = <1>; 1305 #size-cells = <1>; 1306 status = "disabled"; 1307 1308 usbdrd31_dwc3: usb@0 { 1309 compatible = "snps,dwc3"; 1310 reg = <0x0 0x10000>; 1311 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; 1312 clock-names = "ref"; 1313 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1314 phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; 1315 phy-names = "usb2-phy", "usb3-phy"; 1316 snps,has-lpm-erratum; 1317 snps,dis_u2_susphy_quirk; 1318 snps,dis_u3_susphy_quirk; 1319 status = "disabled"; 1320 }; 1321 }; 1322 1323 pinctrl_hsi1: pinctrl@11840000 { 1324 compatible = "google,gs101-pinctrl"; 1325 reg = <0x11840000 0x00001000>; 1326 /* TODO: update once support for this CMU exists */ 1327 clocks = <0>; 1328 clock-names = "pclk"; 1329 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1330 }; 1331 1332 cmu_hsi2: clock-controller@14400000 { 1333 compatible = "google,gs101-cmu-hsi2"; 1334 reg = <0x14400000 0x4000>; 1335 #clock-cells = <1>; 1336 clocks = <&ext_24_5m>, 1337 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, 1338 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, 1339 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, 1340 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; 1341 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; 1342 }; 1343 1344 sysreg_hsi2: syscon@14420000 { 1345 compatible = "google,gs101-hsi2-sysreg", "syscon"; 1346 reg = <0x14420000 0x10000>; 1347 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1348 }; 1349 1350 pinctrl_hsi2: pinctrl@14440000 { 1351 compatible = "google,gs101-pinctrl"; 1352 reg = <0x14440000 0x00001000>; 1353 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; 1354 clock-names = "pclk"; 1355 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 1356 }; 1357 1358 ufs_0: ufs@14700000 { 1359 compatible = "google,gs101-ufs"; 1360 reg = <0x14700000 0x200>, 1361 <0x14701100 0x200>, 1362 <0x14780000 0xa000>, 1363 <0x14600000 0x100>; 1364 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1365 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1366 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, 1367 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, 1368 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, 1369 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, 1370 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, 1371 <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1372 clock-names = "core_clk", "sclk_unipro_main", "fmp", 1373 "aclk", "pclk", "sysreg"; 1374 dma-coherent; 1375 freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; 1376 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1377 pinctrl-names = "default"; 1378 phys = <&ufs_0_phy>; 1379 phy-names = "ufs-phy"; 1380 samsung,sysreg = <&sysreg_hsi2 0x710>; 1381 status = "disabled"; 1382 }; 1383 1384 ufs_0_phy: phy@14704000 { 1385 compatible = "google,gs101-ufs-phy"; 1386 reg = <0x14704000 0x3000>; 1387 reg-names = "phy-pma"; 1388 samsung,pmu-syscon = <&pmu_system_controller>; 1389 #phy-cells = <0>; 1390 clocks = <&ext_24_5m>; 1391 clock-names = "ref_clk"; 1392 status = "disabled"; 1393 }; 1394 1395 cmu_apm: clock-controller@17400000 { 1396 compatible = "google,gs101-cmu-apm"; 1397 reg = <0x17400000 0x8000>; 1398 #clock-cells = <1>; 1399 1400 clocks = <&ext_24_5m>; 1401 clock-names = "oscclk"; 1402 }; 1403 1404 sysreg_apm: syscon@174204e0 { 1405 compatible = "google,gs101-apm-sysreg", "syscon"; 1406 reg = <0x174204e0 0x1000>; 1407 }; 1408 1409 pmu_system_controller: system-controller@17460000 { 1410 compatible = "google,gs101-pmu", "syscon"; 1411 reg = <0x17460000 0x10000>; 1412 google,pmu-intr-gen-syscon = <&pmu_intr_gen>; 1413 1414 poweroff: syscon-poweroff { 1415 compatible = "syscon-poweroff"; 1416 offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ 1417 mask = <0x00000100>; 1418 value = <0x0>; 1419 }; 1420 1421 reboot: syscon-reboot { 1422 compatible = "google,gs101-reboot"; 1423 }; 1424 1425 reboot-mode { 1426 compatible = "syscon-reboot-mode"; 1427 offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */ 1428 mode-bootloader = <0xfc>; 1429 mode-charge = <0x0a>; 1430 mode-dm-verity-device-corrupted = <0x50>; 1431 mode-fastboot = <0xfa>; 1432 mode-reboot-ab-update = <0x52>; 1433 mode-recovery = <0xff>; 1434 mode-rescue = <0xf9>; 1435 mode-shutdown-thermal = <0x51>; 1436 mode-shutdown-thermal-battery = <0x51>; 1437 }; 1438 }; 1439 1440 pmu_intr_gen: syscon@17470000 { 1441 compatible = "google,gs101-pmu-intr-gen", "syscon"; 1442 reg = <0x17470000 0x10000>; 1443 }; 1444 1445 pinctrl_gpio_alive: pinctrl@174d0000 { 1446 compatible = "google,gs101-pinctrl"; 1447 reg = <0x174d0000 0x00001000>; 1448 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; 1449 clock-names = "pclk"; 1450 1451 wakeup-interrupt-controller { 1452 compatible = "google,gs101-wakeup-eint", 1453 "samsung,exynos850-wakeup-eint", 1454 "samsung,exynos7-wakeup-eint"; 1455 }; 1456 }; 1457 1458 pinctrl_far_alive: pinctrl@174e0000 { 1459 compatible = "google,gs101-pinctrl"; 1460 reg = <0x174e0000 0x00001000>; 1461 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; 1462 clock-names = "pclk"; 1463 1464 wakeup-interrupt-controller { 1465 compatible = "google,gs101-wakeup-eint", 1466 "samsung,exynos850-wakeup-eint", 1467 "samsung,exynos7-wakeup-eint"; 1468 }; 1469 }; 1470 1471 ap2apm_mailbox: mailbox@17610000 { 1472 compatible = "google,gs101-mbox"; 1473 reg = <0x17610000 0x1000>; 1474 clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; 1475 clock-names = "pclk"; 1476 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>; 1477 #mbox-cells = <0>; 1478 }; 1479 1480 pinctrl_gsactrl: pinctrl@17940000 { 1481 compatible = "google,gs101-pinctrl"; 1482 reg = <0x17940000 0x00001000>; 1483 /* TODO: update once support for this CMU exists */ 1484 clocks = <0>; 1485 clock-names = "pclk"; 1486 }; 1487 1488 pinctrl_gsacore: pinctrl@17a80000 { 1489 compatible = "google,gs101-pinctrl"; 1490 reg = <0x17a80000 0x00001000>; 1491 /* TODO: update once support for this CMU exists */ 1492 clocks = <0>; 1493 clock-names = "pclk"; 1494 status = "disabled"; 1495 }; 1496 1497 cmu_top: clock-controller@1e080000 { 1498 compatible = "google,gs101-cmu-top"; 1499 reg = <0x1e080000 0x8000>; 1500 #clock-cells = <1>; 1501 1502 clocks = <&ext_24_5m>; 1503 clock-names = "oscclk"; 1504 }; 1505 }; 1506 1507 apm_sram: sram@2039000 { 1508 compatible = "mmio-sram"; 1509 reg = <0x0 0x2039000 0x40000>; 1510 #address-cells = <1>; 1511 #size-cells = <1>; 1512 ranges = <0x0 0x0 0x2039000 0x40000>; 1513 }; 1514 1515 timer { 1516 compatible = "arm,armv8-timer"; 1517 interrupts = 1518 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1519 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1520 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1521 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 1522 }; 1523}; 1524 1525#include "gs101-pinctrl.dtsi" 1526