1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAuto v9 SoC device tree source 4 * 5 * Copyright (c) 2021 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov9.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,exynos-usi.h> 12 13/ { 14 compatible = "samsung,exynosautov9"; 15 #address-cells = <2>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 pinctrl0 = &pinctrl_alive; 22 pinctrl1 = &pinctrl_aud; 23 pinctrl2 = &pinctrl_fsys0; 24 pinctrl3 = &pinctrl_fsys1; 25 pinctrl4 = &pinctrl_fsys2; 26 pinctrl5 = &pinctrl_peric0; 27 pinctrl6 = &pinctrl_peric1; 28 }; 29 30 arm-pmu { 31 compatible = "arm,cortex-a76-pmu"; 32 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 40 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 41 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu-map { 49 cluster0 { 50 core0 { 51 cpu = <&cpu0>; 52 }; 53 core1 { 54 cpu = <&cpu1>; 55 }; 56 core2 { 57 cpu = <&cpu2>; 58 }; 59 core3 { 60 cpu = <&cpu3>; 61 }; 62 }; 63 64 cluster1 { 65 core0 { 66 cpu = <&cpu4>; 67 }; 68 core1 { 69 cpu = <&cpu5>; 70 }; 71 core2 { 72 cpu = <&cpu6>; 73 }; 74 core3 { 75 cpu = <&cpu7>; 76 }; 77 }; 78 }; 79 80 cpu0: cpu@0 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a76"; 83 reg = <0x0>; 84 enable-method = "psci"; 85 }; 86 87 cpu1: cpu@100 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a76"; 90 reg = <0x100>; 91 enable-method = "psci"; 92 }; 93 94 cpu2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a76"; 97 reg = <0x200>; 98 enable-method = "psci"; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a76"; 104 reg = <0x300>; 105 enable-method = "psci"; 106 }; 107 108 cpu4: cpu@10000 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a76"; 111 reg = <0x10000>; 112 enable-method = "psci"; 113 }; 114 115 cpu5: cpu@10100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a76"; 118 reg = <0x10100>; 119 enable-method = "psci"; 120 }; 121 122 cpu6: cpu@10200 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a76"; 125 reg = <0x10200>; 126 enable-method = "psci"; 127 }; 128 129 cpu7: cpu@10300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a76"; 132 reg = <0x10300>; 133 enable-method = "psci"; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0"; 139 method = "smc"; 140 cpu_suspend = <0xc4000001>; 141 cpu_off = <0x84000002>; 142 cpu_on = <0xc4000003>; 143 }; 144 145 timer { 146 compatible = "arm,armv8-timer"; 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 151 }; 152 153 fixed-rate-clocks { 154 xtcxo: clock { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-output-names = "oscclk"; 158 }; 159 }; 160 161 soc: soc@0 { 162 compatible = "simple-bus"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0x0 0x0 0x0 0x20000000>; 166 167 chipid@10000000 { 168 compatible = "samsung,exynos850-chipid"; 169 reg = <0x10000000 0x24>; 170 }; 171 172 cmu_peris: clock-controller@10020000 { 173 compatible = "samsung,exynosautov9-cmu-peris"; 174 reg = <0x10020000 0x8000>; 175 #clock-cells = <1>; 176 177 clocks = <&xtcxo>, 178 <&cmu_top DOUT_CLKCMU_PERIS_BUS>; 179 clock-names = "oscclk", 180 "dout_clkcmu_peris_bus"; 181 }; 182 183 cmu_peric0: clock-controller@10200000 { 184 compatible = "samsung,exynosautov9-cmu-peric0"; 185 reg = <0x10200000 0x8000>; 186 #clock-cells = <1>; 187 188 clocks = <&xtcxo>, 189 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, 190 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 191 clock-names = "oscclk", 192 "dout_clkcmu_peric0_bus", 193 "dout_clkcmu_peric0_ip"; 194 }; 195 196 cmu_peric1: clock-controller@10800000 { 197 compatible = "samsung,exynosautov9-cmu-peric1"; 198 reg = <0x10800000 0x8000>; 199 #clock-cells = <1>; 200 201 clocks = <&xtcxo>, 202 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, 203 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 204 clock-names = "oscclk", 205 "dout_clkcmu_peric1_bus", 206 "dout_clkcmu_peric1_ip"; 207 }; 208 209 cmu_fsys2: clock-controller@17c00000 { 210 compatible = "samsung,exynosautov9-cmu-fsys2"; 211 reg = <0x17c00000 0x8000>; 212 #clock-cells = <1>; 213 214 clocks = <&xtcxo>, 215 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, 216 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, 217 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; 218 clock-names = "oscclk", 219 "dout_clkcmu_fsys2_bus", 220 "dout_fsys2_clkcmu_ufs_embd", 221 "dout_fsys2_clkcmu_ethernet"; 222 }; 223 224 cmu_core: clock-controller@1b030000 { 225 compatible = "samsung,exynosautov9-cmu-core"; 226 reg = <0x1b030000 0x8000>; 227 #clock-cells = <1>; 228 229 clocks = <&xtcxo>, 230 <&cmu_top DOUT_CLKCMU_CORE_BUS>; 231 clock-names = "oscclk", 232 "dout_clkcmu_core_bus"; 233 }; 234 235 cmu_busmc: clock-controller@1b200000 { 236 compatible = "samsung,exynosautov9-cmu-busmc"; 237 reg = <0x1b200000 0x8000>; 238 #clock-cells = <1>; 239 240 clocks = <&xtcxo>, 241 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; 242 clock-names = "oscclk", 243 "dout_clkcmu_busmc_bus"; 244 }; 245 246 cmu_top: clock-controller@1b240000 { 247 compatible = "samsung,exynosautov9-cmu-top"; 248 reg = <0x1b240000 0x8000>; 249 #clock-cells = <1>; 250 251 clocks = <&xtcxo>; 252 clock-names = "oscclk"; 253 }; 254 255 gic: interrupt-controller@10101000 { 256 compatible = "arm,gic-400"; 257 #interrupt-cells = <3>; 258 #address-cells = <0>; 259 interrupt-controller; 260 reg = <0x10101000 0x1000>, 261 <0x10102000 0x2000>, 262 <0x10104000 0x2000>, 263 <0x10106000 0x2000>; 264 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 265 IRQ_TYPE_LEVEL_HIGH)>; 266 }; 267 268 pinctrl_alive: pinctrl@10450000 { 269 compatible = "samsung,exynosautov9-pinctrl"; 270 reg = <0x10450000 0x1000>; 271 272 wakeup-interrupt-controller { 273 compatible = "samsung,exynosautov9-wakeup-eint"; 274 }; 275 }; 276 277 pinctrl_aud: pinctrl@19c60000{ 278 compatible = "samsung,exynosautov9-pinctrl"; 279 reg = <0x19c60000 0x1000>; 280 }; 281 282 pinctrl_fsys0: pinctrl@17740000 { 283 compatible = "samsung,exynosautov9-pinctrl"; 284 reg = <0x17740000 0x1000>; 285 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 286 }; 287 288 pinctrl_fsys1: pinctrl@17060000 { 289 compatible = "samsung,exynosautov9-pinctrl"; 290 reg = <0x17060000 0x1000>; 291 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 292 }; 293 294 pinctrl_fsys2: pinctrl@17c30000 { 295 compatible = "samsung,exynosautov9-pinctrl"; 296 reg = <0x17c30000 0x1000>; 297 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 298 }; 299 300 pinctrl_peric0: pinctrl@10230000 { 301 compatible = "samsung,exynosautov9-pinctrl"; 302 reg = <0x10230000 0x1000>; 303 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 304 }; 305 306 pinctrl_peric1: pinctrl@10830000 { 307 compatible = "samsung,exynosautov9-pinctrl"; 308 reg = <0x10830000 0x1000>; 309 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 310 }; 311 312 pmu_system_controller: system-controller@10460000 { 313 compatible = "samsung,exynos7-pmu", "syscon"; 314 reg = <0x10460000 0x10000>; 315 }; 316 317 syscon_fsys2: syscon@17c20000 { 318 compatible = "samsung,exynosautov9-sysreg", "syscon"; 319 reg = <0x17c20000 0x1000>; 320 }; 321 322 syscon_peric0: syscon@10220000 { 323 compatible = "samsung,exynosautov9-sysreg", "syscon"; 324 reg = <0x10220000 0x2000>; 325 }; 326 327 usi_0: usi@103000c0 { 328 compatible = "samsung,exynos850-usi"; 329 reg = <0x103000c0 0x20>; 330 samsung,sysreg = <&syscon_peric0 0x1000>; 331 samsung,mode = <USI_V2_UART>; 332 samsung,clkreq-on; /* needed for UART mode */ 333 #address-cells = <1>; 334 #size-cells = <1>; 335 ranges; 336 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 337 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 338 clock-names = "pclk", "ipclk"; 339 status = "disabled"; 340 341 /* USI: UART */ 342 serial_0: serial@10300000 { 343 compatible = "samsung,exynos850-uart"; 344 reg = <0x10300000 0xc0>; 345 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&uart0_bus_dual>; 348 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 349 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 350 clock-names = "uart", "clk_uart_baud0"; 351 status = "disabled"; 352 }; 353 }; 354 355 ufs_0_phy: ufs0-phy@17e04000 { 356 compatible = "samsung,exynosautov9-ufs-phy"; 357 reg = <0x17e04000 0xc00>; 358 reg-names = "phy-pma"; 359 samsung,pmu-syscon = <&pmu_system_controller>; 360 #phy-cells = <0>; 361 clocks = <&xtcxo>; 362 clock-names = "ref_clk"; 363 status = "disabled"; 364 }; 365 366 ufs_0: ufs0@17e00000 { 367 compatible ="samsung,exynosautov9-ufs"; 368 369 reg = <0x17e00000 0x100>, /* 0: HCI standard */ 370 <0x17e01100 0x410>, /* 1: Vendor-specific */ 371 <0x17e80000 0x8000>, /* 2: UNIPRO */ 372 <0x17dc0000 0x2200>; /* 3: UFS protector */ 373 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 374 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, 376 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; 377 clock-names = "core_clk", "sclk_unipro_main"; 378 freq-table-hz = <0 0>, <0 0>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 381 phys = <&ufs_0_phy>; 382 phy-names = "ufs-phy"; 383 samsung,sysreg = <&syscon_fsys2 0x710>; 384 status = "disabled"; 385 }; 386 }; 387}; 388 389#include "exynosautov9-pinctrl.dtsi" 390