1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Samsung Exynos 990 SoC device tree source 4 * 5 * Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org> 6 */ 7 8#include <dt-bindings/clock/samsung,exynos990.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "samsung,exynos990"; 13 #address-cells = <2>; 14 #size-cells = <1>; 15 16 interrupt-parent = <&gic>; 17 18 aliases { 19 pinctrl0 = &pinctrl_alive; 20 pinctrl1 = &pinctrl_cmgp; 21 pinctrl2 = &pinctrl_hsi1; 22 pinctrl3 = &pinctrl_hsi2; 23 pinctrl4 = &pinctrl_peric0; 24 pinctrl5 = &pinctrl_peric1; 25 pinctrl6 = &pinctrl_vts; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu-map { 33 cluster0 { 34 core0 { 35 cpu = <&cpu0>; 36 }; 37 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 42 core2 { 43 cpu = <&cpu2>; 44 }; 45 46 core3 { 47 cpu = <&cpu3>; 48 }; 49 }; 50 51 cluster1 { 52 core0 { 53 cpu = <&cpu4>; 54 }; 55 56 core1 { 57 cpu = <&cpu5>; 58 }; 59 }; 60 61 cluster2 { 62 core0 { 63 cpu = <&cpu6>; 64 }; 65 66 core1 { 67 cpu = <&cpu7>; 68 }; 69 }; 70 }; 71 72 cpu0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x0>; 76 enable-method = "psci"; 77 }; 78 79 cpu1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a55"; 82 reg = <0x1>; 83 enable-method = "psci"; 84 }; 85 86 cpu2: cpu@2 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 reg = <0x2>; 90 enable-method = "psci"; 91 }; 92 93 cpu3: cpu@3 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x3>; 97 enable-method = "psci"; 98 }; 99 100 cpu4: cpu@100 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a76"; 103 reg = <0x4>; 104 enable-method = "psci"; 105 }; 106 107 cpu5: cpu@101 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a76"; 110 reg = <0x5>; 111 enable-method = "psci"; 112 }; 113 114 cpu6: cpu@200 { 115 device_type = "cpu"; 116 compatible = "samsung,mongoose-m5"; 117 reg = <0x6>; 118 enable-method = "psci"; 119 }; 120 121 cpu7: cpu@201 { 122 device_type = "cpu"; 123 compatible = "samsung,mongoose-m5"; 124 reg = <0x7>; 125 enable-method = "psci"; 126 }; 127 }; 128 129 oscclk: clock-osc { 130 compatible = "fixed-clock"; 131 #clock-cells = <0>; 132 clock-output-names = "oscclk"; 133 }; 134 135 pmu-a55 { 136 compatible = "arm,cortex-a55-pmu"; 137 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 141 142 interrupt-affinity = <&cpu0>, 143 <&cpu1>, 144 <&cpu2>, 145 <&cpu3>; 146 }; 147 148 pmu-a76 { 149 compatible = "arm,cortex-a76-pmu"; 150 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 152 153 interrupt-affinity = <&cpu4>, 154 <&cpu5>; 155 }; 156 157 pmu-mongoose-m5 { 158 compatible = "samsung,mongoose-pmu"; 159 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 161 162 interrupt-affinity = <&cpu6>, 163 <&cpu7>; 164 }; 165 166 psci { 167 compatible = "arm,psci-0.2"; 168 method = "hvc"; 169 }; 170 171 soc: soc@0 { 172 compatible = "simple-bus"; 173 ranges = <0x0 0x0 0x0 0x20000000>; 174 175 #address-cells = <1>; 176 #size-cells = <1>; 177 178 chipid@10000000 { 179 compatible = "samsung,exynos990-chipid", 180 "samsung,exynos850-chipid"; 181 reg = <0x10000000 0x100>; 182 }; 183 184 cmu_peris: clock-controller@10020000 { 185 compatible = "samsung,exynos990-cmu-peris"; 186 reg = <0x10020000 0x8000>; 187 #clock-cells = <1>; 188 189 clocks = <&oscclk>, 190 <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; 191 clock-names = "oscclk", "bus"; 192 }; 193 194 timer@10040000 { 195 compatible = "samsung,exynos990-mct", 196 "samsung,exynos4210-mct"; 197 reg = <0x10040000 0x800>; 198 clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; 199 clock-names = "fin_pll", "mct"; 200 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 212 }; 213 214 watchdog_cl0: watchdog@10050000 { 215 compatible = "samsung,exynos990-wdt"; 216 reg = <0x10050000 0x100>; 217 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK>, 219 <&oscclk>; 220 clock-names = "watchdog", 221 "watchdog_src"; 222 samsung,syscon-phandle = <&pmu_system_controller>; 223 samsung,cluster-index = <0>; 224 }; 225 226 watchdog_cl2: watchdog@10060000 { 227 compatible = "samsung,exynos990-wdt"; 228 reg = <0x10060000 0x100>; 229 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK>, 231 <&oscclk>; 232 clock-names = "watchdog", 233 "watchdog_src"; 234 samsung,syscon-phandle = <&pmu_system_controller>; 235 samsung,cluster-index = <2>; 236 }; 237 238 gic: interrupt-controller@10101000 { 239 compatible = "arm,gic-400"; 240 reg = <0x10101000 0x1000>, 241 <0x10102000 0x1000>, 242 <0x10104000 0x2000>, 243 <0x10106000 0x2000>; 244 #interrupt-cells = <3>; 245 interrupt-controller; 246 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 247 IRQ_TYPE_LEVEL_HIGH)>; 248 #address-cells = <0>; 249 #size-cells = <1>; 250 }; 251 252 cmu_peric0: clock-controller@10400000 { 253 compatible = "samsung,exynos990-cmu-peric0"; 254 reg = <0x10400000 0x8000>; 255 #clock-cells = <1>; 256 257 clocks = <&oscclk>, 258 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 259 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 260 clock-names = "oscclk", "bus", "ip"; 261 }; 262 263 pinctrl_peric0: pinctrl@10430000 { 264 compatible = "samsung,exynos990-pinctrl"; 265 reg = <0x10430000 0x1000>; 266 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 267 }; 268 269 cmu_peric1: clock-controller@10700000 { 270 compatible = "samsung,exynos990-cmu-peric1"; 271 reg = <0x10700000 0x8000>; 272 #clock-cells = <1>; 273 274 clocks = <&oscclk>, 275 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 276 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 277 clock-names = "oscclk", "bus", "ip"; 278 }; 279 280 pinctrl_peric1: pinctrl@10730000 { 281 compatible = "samsung,exynos990-pinctrl"; 282 reg = <0x10730000 0x1000>; 283 interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 284 }; 285 286 cmu_hsi0: clock-controller@10a00000 { 287 compatible = "samsung,exynos990-cmu-hsi0"; 288 reg = <0x10a00000 0x8000>; 289 #clock-cells = <1>; 290 291 clocks = <&oscclk>, 292 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, 293 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, 294 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>, 295 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>; 296 clock-names = "oscclk", 297 "bus", 298 "usb31drd", 299 "usbdp_debug", 300 "dpgtc"; 301 }; 302 303 usbdrd_phy: phy@10c00000 { 304 compatible = "samsung,exynos990-usbdrd-phy"; 305 reg = <0x10c00000 0x100>; 306 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, 307 <&oscclk>; 308 clock-names = "phy", "ref"; 309 samsung,pmu-syscon = <&pmu_system_controller>; 310 #phy-cells = <1>; 311 status = "disabled"; 312 }; 313 314 usbdrd: usb@10e00000 { 315 compatible = "samsung,exynos990-dwusb3", 316 "samsung,exynos850-dwusb3"; 317 ranges = <0x0 0x10e00000 0x10000>; 318 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, 319 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40>; 320 clock-names = "bus_early", "ref"; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 status = "disabled"; 324 325 usbdrd_dwc3: usb@0 { 326 compatible = "snps,dwc3"; 327 reg = <0x0 0x10000>; 328 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 329 phys = <&usbdrd_phy 0>; 330 phy-names = "usb2-phy"; 331 }; 332 }; 333 334 pinctrl_hsi1: pinctrl@13040000 { 335 compatible = "samsung,exynos990-pinctrl"; 336 reg = <0x13040000 0x1000>; 337 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 338 }; 339 340 pinctrl_hsi2: pinctrl@13c30000 { 341 compatible = "samsung,exynos990-pinctrl"; 342 reg = <0x13c30000 0x1000>; 343 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 344 }; 345 346 pinctrl_vts: pinctrl@15580000 { 347 compatible = "samsung,exynos990-pinctrl"; 348 reg = <0x15580000 0x1000>; 349 }; 350 351 pinctrl_alive: pinctrl@15850000 { 352 compatible = "samsung,exynos990-pinctrl"; 353 reg = <0x15850000 0x1000>; 354 355 wakeup-interrupt-controller { 356 compatible = "samsung,exynos990-wakeup-eint", 357 "samsung,exynos850-wakeup-eint", 358 "samsung,exynos7-wakeup-eint"; 359 }; 360 }; 361 362 pmu_system_controller: system-controller@15860000 { 363 compatible = "samsung,exynos990-pmu", 364 "samsung,exynos7-pmu", "syscon"; 365 reg = <0x15860000 0x10000>; 366 367 reboot: syscon-reboot { 368 compatible = "syscon-reboot"; 369 regmap = <&pmu_system_controller>; 370 offset = <0x3a00>; /* SWRESET */ 371 mask = <0x2>; /* SWRESET_TRIGGER */ 372 value = <0x2>; 373 }; 374 }; 375 376 pinctrl_cmgp: pinctrl@15c30000 { 377 compatible = "samsung,exynos990-pinctrl"; 378 reg = <0x15c30000 0x1000>; 379 }; 380 381 cmu_top: clock-controller@1a330000 { 382 compatible = "samsung,exynos990-cmu-top"; 383 reg = <0x1a330000 0x8000>; 384 #clock-cells = <1>; 385 386 clocks = <&oscclk>; 387 clock-names = "oscclk"; 388 }; 389 }; 390 391 timer { 392 compatible = "arm,armv8-timer"; 393 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 394 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 395 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 396 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 397 398 /* 399 * Non-updatable, broken stock Samsung bootloader does not 400 * configure CNTFRQ_EL0 401 */ 402 clock-frequency = <26000000>; 403 }; 404}; 405 406#include "exynos990-pinctrl.dtsi" 407