1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Samsung Exynos 990 SoC device tree source 4 * 5 * Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org> 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "samsung,exynos990"; 12 #address-cells = <2>; 13 #size-cells = <1>; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 pinctrl0 = &pinctrl_alive; 19 pinctrl1 = &pinctrl_cmgp; 20 pinctrl2 = &pinctrl_hsi1; 21 pinctrl3 = &pinctrl_hsi2; 22 pinctrl4 = &pinctrl_peric0; 23 pinctrl5 = &pinctrl_peric1; 24 pinctrl6 = &pinctrl_vts; 25 }; 26 27 arm-a55-pmu { 28 compatible = "arm,cortex-a55-pmu"; 29 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 33 34 interrupt-affinity = <&cpu0>, 35 <&cpu1>, 36 <&cpu2>, 37 <&cpu3>; 38 }; 39 40 arm-a76-pmu { 41 compatible = "arm,cortex-a76-pmu"; 42 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 44 45 interrupt-affinity = <&cpu4>, 46 <&cpu5>; 47 }; 48 49 /* There's no PMU model for cluster2, which are the Mongoose cores. */ 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 cpu-map { 56 cluster0 { 57 core0 { 58 cpu = <&cpu0>; 59 }; 60 61 core1 { 62 cpu = <&cpu1>; 63 }; 64 65 core2 { 66 cpu = <&cpu2>; 67 }; 68 69 core3 { 70 cpu = <&cpu3>; 71 }; 72 }; 73 74 cluster1 { 75 core0 { 76 cpu = <&cpu4>; 77 }; 78 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 }; 83 84 cluster2 { 85 core0 { 86 cpu = <&cpu6>; 87 }; 88 89 core1 { 90 cpu = <&cpu7>; 91 }; 92 }; 93 }; 94 95 cpu0: cpu@0 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a55"; 98 reg = <0x0>; 99 enable-method = "psci"; 100 }; 101 102 cpu1: cpu@1 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a55"; 105 reg = <0x1>; 106 enable-method = "psci"; 107 }; 108 109 cpu2: cpu@2 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x2>; 113 enable-method = "psci"; 114 }; 115 116 cpu3: cpu@3 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x3>; 120 enable-method = "psci"; 121 }; 122 123 cpu4: cpu@100 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a76"; 126 reg = <0x4>; 127 enable-method = "psci"; 128 }; 129 130 cpu5: cpu@101 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a76"; 133 reg = <0x5>; 134 enable-method = "psci"; 135 }; 136 137 cpu6: cpu@200 { 138 device_type = "cpu"; 139 compatible = "samsung,mongoose-m5"; 140 reg = <0x6>; 141 enable-method = "psci"; 142 }; 143 144 cpu7: cpu@201 { 145 device_type = "cpu"; 146 compatible = "samsung,mongoose-m5"; 147 reg = <0x7>; 148 enable-method = "psci"; 149 }; 150 }; 151 152 oscclk: clock-osc { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-output-names = "oscclk"; 156 }; 157 158 psci { 159 compatible = "arm,psci-0.2"; 160 method = "hvc"; 161 }; 162 163 soc: soc@0 { 164 compatible = "simple-bus"; 165 ranges = <0x0 0x0 0x0 0x20000000>; 166 167 #address-cells = <1>; 168 #size-cells = <1>; 169 170 chipid@10000000 { 171 compatible = "samsung,exynos990-chipid", 172 "samsung,exynos850-chipid"; 173 reg = <0x10000000 0x100>; 174 }; 175 176 gic: interrupt-controller@10101000 { 177 compatible = "arm,gic-400"; 178 reg = <0x10101000 0x1000>, 179 <0x10102000 0x1000>, 180 <0x10104000 0x2000>, 181 <0x10106000 0x2000>; 182 #interrupt-cells = <3>; 183 interrupt-controller; 184 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 185 IRQ_TYPE_LEVEL_HIGH)>; 186 #address-cells = <0>; 187 #size-cells = <1>; 188 }; 189 190 pinctrl_peric0: pinctrl@10430000 { 191 compatible = "samsung,exynos990-pinctrl"; 192 reg = <0x10430000 0x1000>; 193 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 194 }; 195 196 pinctrl_peric1: pinctrl@10730000 { 197 compatible = "samsung,exynos990-pinctrl"; 198 reg = <0x10730000 0x1000>; 199 interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 200 }; 201 202 pinctrl_hsi1: pinctrl@13040000 { 203 compatible = "samsung,exynos990-pinctrl"; 204 reg = <0x13040000 0x1000>; 205 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 206 }; 207 208 pinctrl_hsi2: pinctrl@13c30000 { 209 compatible = "samsung,exynos990-pinctrl"; 210 reg = <0x13c30000 0x1000>; 211 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 212 }; 213 214 pinctrl_vts: pinctrl@15580000 { 215 compatible = "samsung,exynos990-pinctrl"; 216 reg = <0x15580000 0x1000>; 217 }; 218 219 pinctrl_alive: pinctrl@15850000 { 220 compatible = "samsung,exynos990-pinctrl"; 221 reg = <0x15850000 0x1000>; 222 223 wakeup-interrupt-controller { 224 compatible = "samsung,exynos990-wakeup-eint", 225 "samsung,exynos850-wakeup-eint", 226 "samsung,exynos7-wakeup-eint"; 227 }; 228 }; 229 230 pinctrl_cmgp: pinctrl@15c30000 { 231 compatible = "samsung,exynos990-pinctrl"; 232 reg = <0x15c30000 0x1000>; 233 }; 234 }; 235 236 timer { 237 compatible = "arm,armv8-timer"; 238 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 239 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 242 243 /* 244 * Non-updatable, broken stock Samsung bootloader does not 245 * configure CNTFRQ_EL0 246 */ 247 clock-frequency = <26000000>; 248 }; 249}; 250 251#include "exynos990-pinctrl.dtsi" 252