1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Samsung's Exynos 8895 SoC device tree source 4 * 5 * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "samsung,exynos8895"; 12 #address-cells = <2>; 13 #size-cells = <1>; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 pinctrl0 = &pinctrl_alive; 19 pinctrl1 = &pinctrl_abox; 20 pinctrl2 = &pinctrl_vts; 21 pinctrl3 = &pinctrl_fsys0; 22 pinctrl4 = &pinctrl_fsys1; 23 pinctrl5 = &pinctrl_busc; 24 pinctrl6 = &pinctrl_peric0; 25 pinctrl7 = &pinctrl_peric1; 26 }; 27 28 arm-a53-pmu { 29 compatible = "arm,cortex-a53-pmu"; 30 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 34 interrupt-affinity = <&cpu0>, 35 <&cpu1>, 36 <&cpu2>, 37 <&cpu3>; 38 }; 39 40 /* There's no PMU model for the Mongoose cores */ 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu0>; 50 }; 51 core1 { 52 cpu = <&cpu1>; 53 }; 54 core2 { 55 cpu = <&cpu2>; 56 }; 57 core3 { 58 cpu = <&cpu3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu4>; 65 }; 66 core1 { 67 cpu = <&cpu5>; 68 }; 69 core2 { 70 cpu = <&cpu6>; 71 }; 72 core3 { 73 cpu = <&cpu7>; 74 }; 75 }; 76 }; 77 78 cpu4: cpu@0 { 79 device_type = "cpu"; 80 compatible = "samsung,mongoose-m2"; 81 reg = <0x0>; 82 enable-method = "psci"; 83 }; 84 85 cpu5: cpu@1 { 86 device_type = "cpu"; 87 compatible = "samsung,mongoose-m2"; 88 reg = <0x1>; 89 enable-method = "psci"; 90 }; 91 92 cpu6: cpu@2 { 93 device_type = "cpu"; 94 compatible = "samsung,mongoose-m2"; 95 reg = <0x2>; 96 enable-method = "psci"; 97 }; 98 99 cpu7: cpu@3 { 100 device_type = "cpu"; 101 compatible = "samsung,mongoose-m2"; 102 reg = <0x3>; 103 enable-method = "psci"; 104 }; 105 106 cpu0: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x100>; 110 enable-method = "psci"; 111 }; 112 113 cpu1: cpu@101 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a53"; 116 reg = <0x101>; 117 enable-method = "psci"; 118 }; 119 120 cpu2: cpu@102 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x102>; 124 enable-method = "psci"; 125 }; 126 127 cpu3: cpu@103 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a53"; 130 reg = <0x103>; 131 enable-method = "psci"; 132 }; 133 }; 134 135 oscclk: osc-clock { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-output-names = "oscclk"; 139 }; 140 141 psci { 142 compatible = "arm,psci"; 143 method = "smc"; 144 cpu_off = <0x84000002>; 145 cpu_on = <0xc4000003>; 146 cpu_suspend = <0xc4000001>; 147 }; 148 149 soc: soc@0 { 150 compatible = "simple-bus"; 151 ranges = <0x0 0x0 0x0 0x20000000>; 152 153 #address-cells = <1>; 154 #size-cells = <1>; 155 156 chipid@10000000 { 157 compatible = "samsung,exynos8895-chipid", 158 "samsung,exynos850-chipid"; 159 reg = <0x10000000 0x24>; 160 }; 161 162 gic: interrupt-controller@10201000 { 163 compatible = "arm,gic-400"; 164 reg = <0x10201000 0x1000>, 165 <0x10202000 0x1000>, 166 <0x10204000 0x2000>, 167 <0x10206000 0x2000>; 168 #interrupt-cells = <3>; 169 interrupt-controller; 170 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 171 IRQ_TYPE_LEVEL_HIGH)>; 172 #address-cells = <0>; 173 #size-cells = <1>; 174 }; 175 176 pinctrl_peric0: pinctrl@104d0000 { 177 compatible = "samsung,exynos8895-pinctrl"; 178 reg = <0x104d0000 0x1000>; 179 interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>; 180 }; 181 182 pinctrl_peric1: pinctrl@10980000 { 183 compatible = "samsung,exynos8895-pinctrl"; 184 reg = <0x10980000 0x1000>; 185 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 186 }; 187 188 pinctrl_fsys0: pinctrl@11050000 { 189 compatible = "samsung,exynos8895-pinctrl"; 190 reg = <0x11050000 0x1000>; 191 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 192 }; 193 194 pinctrl_fsys1: pinctrl@11430000 { 195 compatible = "samsung,exynos8895-pinctrl"; 196 reg = <0x11430000 0x1000>; 197 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 198 }; 199 200 pinctrl_abox: pinctrl@13e60000 { 201 compatible = "samsung,exynos8895-pinctrl"; 202 reg = <0x13e60000 0x1000>; 203 }; 204 205 pinctrl_vts: pinctrl@14080000 { 206 compatible = "samsung,exynos8895-pinctrl"; 207 reg = <0x14080000 0x1000>; 208 }; 209 210 pinctrl_busc: pinctrl@15a30000 { 211 compatible = "samsung,exynos8895-pinctrl"; 212 reg = <0x15a30000 0x1000>; 213 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 214 }; 215 216 pmu_system_controller: system-controller@16480000 { 217 compatible = "samsung,exynos8895-pmu", 218 "samsung,exynos7-pmu", "syscon"; 219 reg = <0x16480000 0x10000>; 220 }; 221 222 pinctrl_alive: pinctrl@164b0000 { 223 compatible = "samsung,exynos8895-pinctrl"; 224 reg = <0x164b0000 0x1000>; 225 226 wakeup-interrupt-controller { 227 compatible = "samsung,exynos8895-wakeup-eint", 228 "samsung,exynos7-wakeup-eint"; 229 interrupt-parent = <&gic>; 230 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 231 }; 232 }; 233 }; 234 235 timer { 236 compatible = "arm,armv8-timer"; 237 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 238 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 239 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 242 /* 243 * Non-updatable, broken stock Samsung bootloader does not 244 * configure CNTFRQ_EL0 245 */ 246 clock-frequency = <26000000>; 247 }; 248}; 249 250#include "exynos8895-pinctrl.dtsi" 251#include "arm/samsung/exynos-syscon-restart.dtsi" 252