xref: /linux/arch/arm64/boot/dts/exynos/exynos8895.dtsi (revision 9ad6c3bd1bcbb73e2a5723e13b9d06e2296b07e4) 
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Samsung's Exynos 8895 SoC device tree source
4 *
5 * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
6 */
7
8#include <dt-bindings/clock/samsung,exynos8895.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "samsung,exynos8895";
13	#address-cells = <2>;
14	#size-cells = <1>;
15
16	interrupt-parent = <&gic>;
17
18	aliases {
19		pinctrl0 = &pinctrl_alive;
20		pinctrl1 = &pinctrl_abox;
21		pinctrl2 = &pinctrl_vts;
22		pinctrl3 = &pinctrl_fsys0;
23		pinctrl4 = &pinctrl_fsys1;
24		pinctrl5 = &pinctrl_busc;
25		pinctrl6 = &pinctrl_peric0;
26		pinctrl7 = &pinctrl_peric1;
27	};
28
29	arm-a53-pmu {
30		compatible = "arm,cortex-a53-pmu";
31		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
35		interrupt-affinity = <&cpu0>,
36				     <&cpu1>,
37				     <&cpu2>,
38				     <&cpu3>;
39	};
40
41	/* There's no PMU model for the Mongoose cores */
42
43	cpus {
44		#address-cells = <1>;
45		#size-cells = <0>;
46
47		cpu-map {
48			cluster0 {
49				core0 {
50					cpu = <&cpu0>;
51				};
52				core1 {
53					cpu = <&cpu1>;
54				};
55				core2 {
56					cpu = <&cpu2>;
57				};
58				core3 {
59					cpu = <&cpu3>;
60				};
61			};
62
63			cluster1 {
64				core0 {
65					cpu = <&cpu4>;
66				};
67				core1 {
68					cpu = <&cpu5>;
69				};
70				core2 {
71					cpu = <&cpu6>;
72				};
73				core3 {
74					cpu = <&cpu7>;
75				};
76			};
77		};
78
79		cpu4: cpu@0 {
80			device_type = "cpu";
81			compatible = "samsung,mongoose-m2";
82			reg = <0x0>;
83			enable-method = "psci";
84		};
85
86		cpu5: cpu@1 {
87			device_type = "cpu";
88			compatible = "samsung,mongoose-m2";
89			reg = <0x1>;
90			enable-method = "psci";
91		};
92
93		cpu6: cpu@2 {
94			device_type = "cpu";
95			compatible = "samsung,mongoose-m2";
96			reg = <0x2>;
97			enable-method = "psci";
98		};
99
100		cpu7: cpu@3 {
101			device_type = "cpu";
102			compatible = "samsung,mongoose-m2";
103			reg = <0x3>;
104			enable-method = "psci";
105		};
106
107		cpu0: cpu@100 {
108			device_type = "cpu";
109			compatible = "arm,cortex-a53";
110			reg = <0x100>;
111			enable-method = "psci";
112		};
113
114		cpu1: cpu@101 {
115			device_type = "cpu";
116			compatible = "arm,cortex-a53";
117			reg = <0x101>;
118			enable-method = "psci";
119		};
120
121		cpu2: cpu@102 {
122			device_type = "cpu";
123			compatible = "arm,cortex-a53";
124			reg = <0x102>;
125			enable-method = "psci";
126		};
127
128		cpu3: cpu@103 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a53";
131			reg = <0x103>;
132			enable-method = "psci";
133		};
134	};
135
136	oscclk: osc-clock {
137		compatible = "fixed-clock";
138		#clock-cells = <0>;
139		clock-output-names = "oscclk";
140	};
141
142	psci {
143		compatible = "arm,psci";
144		method = "smc";
145		cpu_off = <0x84000002>;
146		cpu_on = <0xc4000003>;
147		cpu_suspend = <0xc4000001>;
148	};
149
150	soc: soc@0 {
151		compatible = "simple-bus";
152		ranges = <0x0 0x0 0x0 0x20000000>;
153
154		#address-cells = <1>;
155		#size-cells = <1>;
156
157		chipid@10000000 {
158			compatible = "samsung,exynos8895-chipid",
159				     "samsung,exynos850-chipid";
160			reg = <0x10000000 0x24>;
161		};
162
163		cmu_peris: clock-controller@10010000 {
164			compatible = "samsung,exynos8895-cmu-peris";
165			reg = <0x10010000 0x8000>;
166			#clock-cells = <1>;
167			clocks = <&oscclk>,
168				 <&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
169			clock-names = "oscclk", "bus";
170		};
171
172		timer@10040000 {
173			compatible = "samsung,exynos8895-mct",
174				     "samsung,exynos4210-mct";
175			reg = <0x10040000 0x800>;
176			clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
177			clock-names = "fin_pll", "mct";
178			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
179				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
180				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
181				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
182				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
183				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
184				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
185				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
186				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
187				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
188				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
189				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
190		};
191
192		gic: interrupt-controller@10201000 {
193			compatible = "arm,gic-400";
194			reg = <0x10201000 0x1000>,
195			      <0x10202000 0x1000>,
196			      <0x10204000 0x2000>,
197			      <0x10206000 0x2000>;
198			#interrupt-cells = <3>;
199			interrupt-controller;
200			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
201						 IRQ_TYPE_LEVEL_HIGH)>;
202			#address-cells = <0>;
203			#size-cells = <1>;
204		};
205
206		cmu_peric0: clock-controller@10400000 {
207			compatible = "samsung,exynos8895-cmu-peric0";
208			reg = <0x10400000 0x8000>;
209			#clock-cells = <1>;
210			clocks = <&oscclk>,
211				 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
212				 <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>,
213				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>,
214				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>,
215				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>,
216				 <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>;
217			clock-names = "oscclk", "bus", "uart", "usi0",
218				      "usi1", "usi2", "usi3";
219		};
220
221		pinctrl_peric0: pinctrl@104d0000 {
222			compatible = "samsung,exynos8895-pinctrl";
223			reg = <0x104d0000 0x1000>;
224			interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
225		};
226
227		cmu_peric1: clock-controller@10800000 {
228			compatible = "samsung,exynos8895-cmu-peric1";
229			reg = <0x10800000 0x8000>;
230			#clock-cells = <1>;
231			clocks = <&oscclk>,
232				 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
233				 <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>,
234				 <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>,
235				 <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>,
236				 <&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>,
237				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI04>,
238				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI05>,
239				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI06>,
240				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI07>,
241				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI08>,
242				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI09>,
243				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI10>,
244				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI11>,
245				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI12>,
246				 <&cmu_top CLK_DOUT_CMU_PERIC1_USI13>;
247			clock-names = "oscclk", "bus", "speedy", "cam0",
248				      "cam1", "uart", "usi4", "usi5",
249				      "usi6", "usi7", "usi8", "usi9",
250				      "usi10", "usi11", "usi12", "usi13";
251		};
252
253		pinctrl_peric1: pinctrl@10980000 {
254			compatible = "samsung,exynos8895-pinctrl";
255			reg = <0x10980000 0x1000>;
256			interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
257		};
258
259		cmu_fsys0: clock-controller@11000000 {
260			compatible = "samsung,exynos8895-cmu-fsys0";
261			reg = <0x11000000 0x8000>;
262			#clock-cells = <1>;
263			clocks = <&oscclk>,
264				 <&cmu_top CLK_DOUT_CMU_FSYS0_BUS>,
265				 <&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>,
266				 <&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>,
267				 <&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>,
268				 <&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>;
269			clock-names = "oscclk", "bus", "dpgtc", "mmc",
270				      "ufs", "usbdrd30";
271		};
272
273		pinctrl_fsys0: pinctrl@11050000 {
274			compatible = "samsung,exynos8895-pinctrl";
275			reg = <0x11050000 0x1000>;
276			interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
277		};
278
279		cmu_fsys1: clock-controller@11400000 {
280			compatible = "samsung,exynos8895-cmu-fsys1";
281			reg = <0x11400000 0x8000>;
282			#clock-cells = <1>;
283			clocks = <&oscclk>,
284				 <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
285				 <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
286				 <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
287				 <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
288			clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
289		};
290
291		pinctrl_fsys1: pinctrl@11430000 {
292			compatible = "samsung,exynos8895-pinctrl";
293			reg = <0x11430000 0x1000>;
294			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
295		};
296
297		pinctrl_abox: pinctrl@13e60000 {
298			compatible = "samsung,exynos8895-pinctrl";
299			reg = <0x13e60000 0x1000>;
300		};
301
302		pinctrl_vts: pinctrl@14080000 {
303			compatible = "samsung,exynos8895-pinctrl";
304			reg = <0x14080000 0x1000>;
305		};
306
307		pinctrl_busc: pinctrl@15a30000 {
308			compatible = "samsung,exynos8895-pinctrl";
309			reg = <0x15a30000 0x1000>;
310			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
311		};
312
313		cmu_top: clock-controller@15a80000 {
314			compatible = "samsung,exynos8895-cmu-top";
315			reg = <0x15a80000 0x8000>;
316			#clock-cells = <1>;
317			clocks = <&oscclk>;
318			clock-names = "oscclk";
319		};
320
321		pmu_system_controller: system-controller@16480000 {
322			compatible = "samsung,exynos8895-pmu",
323				     "samsung,exynos7-pmu", "syscon";
324			reg = <0x16480000 0x10000>;
325		};
326
327		pinctrl_alive: pinctrl@164b0000 {
328			compatible = "samsung,exynos8895-pinctrl";
329			reg = <0x164b0000 0x1000>;
330
331			wakeup-interrupt-controller {
332				compatible = "samsung,exynos8895-wakeup-eint",
333					     "samsung,exynos7-wakeup-eint";
334				interrupt-parent = <&gic>;
335				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
336			};
337		};
338	};
339
340	timer {
341		compatible = "arm,armv8-timer";
342		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
343		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
344			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
345			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
346			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
347		/*
348		 * Non-updatable, broken stock Samsung bootloader does not
349		 * configure CNTFRQ_EL0
350		 */
351		clock-frequency = <26000000>;
352	};
353};
354
355#include "exynos8895-pinctrl.dtsi"
356#include "arm/samsung/exynos-syscon-restart.dtsi"
357