1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a55-pmu"; 36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 46 }; 47 48 /* Main system clock (XTCXO); external, must be 26 MHz */ 49 oscclk: clock-oscclk { 50 compatible = "fixed-clock"; 51 clock-output-names = "oscclk"; 52 #clock-cells = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 75 cluster1 { 76 core0 { 77 cpu = <&cpu4>; 78 }; 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 core2 { 83 cpu = <&cpu6>; 84 }; 85 core3 { 86 cpu = <&cpu7>; 87 }; 88 }; 89 }; 90 91 cpu0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 }; 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x1>; 101 enable-method = "psci"; 102 }; 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a55"; 106 reg = <0x2>; 107 enable-method = "psci"; 108 }; 109 cpu3: cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x3>; 113 enable-method = "psci"; 114 }; 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 }; 121 cpu5: cpu@101 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x101>; 125 enable-method = "psci"; 126 }; 127 cpu6: cpu@102 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a55"; 130 reg = <0x102>; 131 enable-method = "psci"; 132 }; 133 cpu7: cpu@103 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a55"; 136 reg = <0x103>; 137 enable-method = "psci"; 138 }; 139 }; 140 141 psci { 142 compatible = "arm,psci-1.0"; 143 method = "smc"; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 149 interrupts = 150 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 154 }; 155 156 soc: soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 ranges = <0x0 0x0 0x0 0x20000000>; 161 162 chipid@10000000 { 163 compatible = "samsung,exynos850-chipid"; 164 reg = <0x10000000 0x100>; 165 }; 166 167 timer@10040000 { 168 compatible = "samsung,exynos850-mct", 169 "samsung,exynos4210-mct"; 170 reg = <0x10040000 0x800>; 171 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 184 clock-names = "fin_pll", "mct"; 185 }; 186 187 gic: interrupt-controller@12a01000 { 188 compatible = "arm,gic-400"; 189 #interrupt-cells = <3>; 190 #address-cells = <0>; 191 reg = <0x12a01000 0x1000>, 192 <0x12a02000 0x2000>, 193 <0x12a04000 0x2000>, 194 <0x12a06000 0x2000>; 195 interrupt-controller; 196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 197 IRQ_TYPE_LEVEL_HIGH)>; 198 }; 199 200 pmu_system_controller: system-controller@11860000 { 201 compatible = "samsung,exynos850-pmu", "syscon"; 202 reg = <0x11860000 0x10000>; 203 clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; 204 205 reboot: syscon-reboot { 206 compatible = "syscon-reboot"; 207 regmap = <&pmu_system_controller>; 208 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 209 mask = <0x2>; /* SWRESET_SYSTEM */ 210 value = <0x2>; /* reset value */ 211 }; 212 }; 213 214 watchdog_cl0: watchdog@10050000 { 215 compatible = "samsung,exynos850-wdt"; 216 reg = <0x10050000 0x100>; 217 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 219 clock-names = "watchdog", "watchdog_src"; 220 samsung,syscon-phandle = <&pmu_system_controller>; 221 samsung,cluster-index = <0>; 222 status = "disabled"; 223 }; 224 225 watchdog_cl1: watchdog@10060000 { 226 compatible = "samsung,exynos850-wdt"; 227 reg = <0x10060000 0x100>; 228 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 230 clock-names = "watchdog", "watchdog_src"; 231 samsung,syscon-phandle = <&pmu_system_controller>; 232 samsung,cluster-index = <1>; 233 status = "disabled"; 234 }; 235 236 cmu_peri: clock-controller@10030000 { 237 compatible = "samsung,exynos850-cmu-peri"; 238 reg = <0x10030000 0x8000>; 239 #clock-cells = <1>; 240 241 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 242 <&cmu_top CLK_DOUT_PERI_UART>, 243 <&cmu_top CLK_DOUT_PERI_IP>; 244 clock-names = "oscclk", "dout_peri_bus", 245 "dout_peri_uart", "dout_peri_ip"; 246 }; 247 248 cmu_apm: clock-controller@11800000 { 249 compatible = "samsung,exynos850-cmu-apm"; 250 reg = <0x11800000 0x8000>; 251 #clock-cells = <1>; 252 253 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 254 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 255 }; 256 257 cmu_cmgp: clock-controller@11c00000 { 258 compatible = "samsung,exynos850-cmu-cmgp"; 259 reg = <0x11c00000 0x8000>; 260 #clock-cells = <1>; 261 262 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 263 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 264 }; 265 266 cmu_core: clock-controller@12000000 { 267 compatible = "samsung,exynos850-cmu-core"; 268 reg = <0x12000000 0x8000>; 269 #clock-cells = <1>; 270 271 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 272 <&cmu_top CLK_DOUT_CORE_CCI>, 273 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 274 <&cmu_top CLK_DOUT_CORE_SSS>; 275 clock-names = "oscclk", "dout_core_bus", 276 "dout_core_cci", "dout_core_mmc_embd", 277 "dout_core_sss"; 278 }; 279 280 cmu_top: clock-controller@120e0000 { 281 compatible = "samsung,exynos850-cmu-top"; 282 reg = <0x120e0000 0x8000>; 283 #clock-cells = <1>; 284 285 clocks = <&oscclk>; 286 clock-names = "oscclk"; 287 }; 288 289 cmu_mfcmscl: clock-controller@12c00000 { 290 compatible = "samsung,exynos850-cmu-mfcmscl"; 291 reg = <0x12c00000 0x8000>; 292 #clock-cells = <1>; 293 294 clocks = <&oscclk>, 295 <&cmu_top CLK_DOUT_MFCMSCL_MFC>, 296 <&cmu_top CLK_DOUT_MFCMSCL_M2M>, 297 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, 298 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; 299 clock-names = "oscclk", "dout_mfcmscl_mfc", 300 "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", 301 "dout_mfcmscl_jpeg"; 302 }; 303 304 cmu_dpu: clock-controller@13000000 { 305 compatible = "samsung,exynos850-cmu-dpu"; 306 reg = <0x13000000 0x8000>; 307 #clock-cells = <1>; 308 309 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 310 clock-names = "oscclk", "dout_dpu"; 311 }; 312 313 cmu_hsi: clock-controller@13400000 { 314 compatible = "samsung,exynos850-cmu-hsi"; 315 reg = <0x13400000 0x8000>; 316 #clock-cells = <1>; 317 318 clocks = <&oscclk>, 319 <&cmu_top CLK_DOUT_HSI_BUS>, 320 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 321 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 322 clock-names = "oscclk", "dout_hsi_bus", 323 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 324 }; 325 326 cmu_is: clock-controller@14500000 { 327 compatible = "samsung,exynos850-cmu-is"; 328 reg = <0x14500000 0x8000>; 329 #clock-cells = <1>; 330 331 clocks = <&oscclk>, 332 <&cmu_top CLK_DOUT_IS_BUS>, 333 <&cmu_top CLK_DOUT_IS_ITP>, 334 <&cmu_top CLK_DOUT_IS_VRA>, 335 <&cmu_top CLK_DOUT_IS_GDC>; 336 clock-names = "oscclk", "dout_is_bus", "dout_is_itp", 337 "dout_is_vra", "dout_is_gdc"; 338 }; 339 340 cmu_aud: clock-controller@14a00000 { 341 compatible = "samsung,exynos850-cmu-aud"; 342 reg = <0x14a00000 0x8000>; 343 #clock-cells = <1>; 344 345 clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; 346 clock-names = "oscclk", "dout_aud"; 347 }; 348 349 pinctrl_alive: pinctrl@11850000 { 350 compatible = "samsung,exynos850-pinctrl"; 351 reg = <0x11850000 0x1000>; 352 353 wakeup-interrupt-controller { 354 compatible = "samsung,exynos850-wakeup-eint"; 355 }; 356 }; 357 358 pinctrl_cmgp: pinctrl@11c30000 { 359 compatible = "samsung,exynos850-pinctrl"; 360 reg = <0x11c30000 0x1000>; 361 362 wakeup-interrupt-controller { 363 compatible = "samsung,exynos850-wakeup-eint"; 364 }; 365 }; 366 367 pinctrl_core: pinctrl@12070000 { 368 compatible = "samsung,exynos850-pinctrl"; 369 reg = <0x12070000 0x1000>; 370 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 371 }; 372 373 pinctrl_hsi: pinctrl@13430000 { 374 compatible = "samsung,exynos850-pinctrl"; 375 reg = <0x13430000 0x1000>; 376 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 377 }; 378 379 pinctrl_peri: pinctrl@139b0000 { 380 compatible = "samsung,exynos850-pinctrl"; 381 reg = <0x139b0000 0x1000>; 382 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 383 }; 384 385 pinctrl_aud: pinctrl@14a60000 { 386 compatible = "samsung,exynos850-pinctrl"; 387 reg = <0x14a60000 0x1000>; 388 }; 389 390 rtc: rtc@11a30000 { 391 compatible = "samsung,s3c6410-rtc"; 392 reg = <0x11a30000 0x100>; 393 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 396 clock-names = "rtc"; 397 status = "disabled"; 398 }; 399 400 mmc_0: mmc@12100000 { 401 compatible = "samsung,exynos7-dw-mshc-smu"; 402 reg = <0x12100000 0x2000>; 403 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 407 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 408 clock-names = "biu", "ciu"; 409 fifo-depth = <0x40>; 410 status = "disabled"; 411 }; 412 413 i2c_0: i2c@13830000 { 414 compatible = "samsung,s3c2440-i2c"; 415 reg = <0x13830000 0x100>; 416 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2c0_pins>; 421 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 422 clock-names = "i2c"; 423 status = "disabled"; 424 }; 425 426 i2c_1: i2c@13840000 { 427 compatible = "samsung,s3c2440-i2c"; 428 reg = <0x13840000 0x100>; 429 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&i2c1_pins>; 434 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 435 clock-names = "i2c"; 436 status = "disabled"; 437 }; 438 439 i2c_2: i2c@13850000 { 440 compatible = "samsung,s3c2440-i2c"; 441 reg = <0x13850000 0x100>; 442 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&i2c2_pins>; 447 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 448 clock-names = "i2c"; 449 status = "disabled"; 450 }; 451 452 i2c_3: i2c@13860000 { 453 compatible = "samsung,s3c2440-i2c"; 454 reg = <0x13860000 0x100>; 455 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&i2c3_pins>; 460 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 461 clock-names = "i2c"; 462 status = "disabled"; 463 }; 464 465 i2c_4: i2c@13870000 { 466 compatible = "samsung,s3c2440-i2c"; 467 reg = <0x13870000 0x100>; 468 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&i2c4_pins>; 473 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 474 clock-names = "i2c"; 475 status = "disabled"; 476 }; 477 478 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 479 i2c_5: i2c@13880000 { 480 compatible = "samsung,s3c2440-i2c"; 481 reg = <0x13880000 0x100>; 482 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&i2c5_pins>; 487 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 488 clock-names = "i2c"; 489 status = "disabled"; 490 }; 491 492 /* I2C_6 (also called MOTOR_I2C in TRM) */ 493 i2c_6: i2c@13890000 { 494 compatible = "samsung,s3c2440-i2c"; 495 reg = <0x13890000 0x100>; 496 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&i2c6_pins>; 501 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 502 clock-names = "i2c"; 503 status = "disabled"; 504 }; 505 506 sysmmu_mfcmscl: sysmmu@12c50000 { 507 compatible = "samsung,exynos-sysmmu"; 508 reg = <0x12c50000 0x9000>; 509 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 510 clock-names = "sysmmu"; 511 clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; 512 #iommu-cells = <0>; 513 }; 514 515 sysmmu_dpu: sysmmu@130c0000 { 516 compatible = "samsung,exynos-sysmmu"; 517 reg = <0x130c0000 0x9000>; 518 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 519 clock-names = "sysmmu"; 520 clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; 521 #iommu-cells = <0>; 522 }; 523 524 sysmmu_is0: sysmmu@14550000 { 525 compatible = "samsung,exynos-sysmmu"; 526 reg = <0x14550000 0x9000>; 527 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 528 clock-names = "sysmmu"; 529 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; 530 #iommu-cells = <0>; 531 }; 532 533 sysmmu_is1: sysmmu@14570000 { 534 compatible = "samsung,exynos-sysmmu"; 535 reg = <0x14570000 0x9000>; 536 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 537 clock-names = "sysmmu"; 538 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; 539 #iommu-cells = <0>; 540 }; 541 542 sysmmu_aud: sysmmu@14850000 { 543 compatible = "samsung,exynos-sysmmu"; 544 reg = <0x14850000 0x9000>; 545 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 546 clock-names = "sysmmu"; 547 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; 548 #iommu-cells = <0>; 549 }; 550 551 sysreg_peri: syscon@10020000 { 552 compatible = "samsung,exynos850-peri-sysreg", 553 "samsung,exynos850-sysreg", "syscon"; 554 reg = <0x10020000 0x10000>; 555 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 556 }; 557 558 sysreg_cmgp: syscon@11c20000 { 559 compatible = "samsung,exynos850-cmgp-sysreg", 560 "samsung,exynos850-sysreg", "syscon"; 561 reg = <0x11c20000 0x10000>; 562 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 563 }; 564 565 usi_uart: usi@138200c0 { 566 compatible = "samsung,exynos850-usi"; 567 reg = <0x138200c0 0x20>; 568 samsung,sysreg = <&sysreg_peri 0x1010>; 569 samsung,mode = <USI_V2_UART>; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 ranges; 573 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 574 <&cmu_peri CLK_GOUT_UART_IPCLK>; 575 clock-names = "pclk", "ipclk"; 576 status = "disabled"; 577 578 serial_0: serial@13820000 { 579 compatible = "samsung,exynos850-uart"; 580 reg = <0x13820000 0xc0>; 581 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&uart0_pins>; 584 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 585 <&cmu_peri CLK_GOUT_UART_IPCLK>; 586 clock-names = "uart", "clk_uart_baud0"; 587 status = "disabled"; 588 }; 589 }; 590 591 usi_hsi2c_0: usi@138a00c0 { 592 compatible = "samsung,exynos850-usi"; 593 reg = <0x138a00c0 0x20>; 594 samsung,sysreg = <&sysreg_peri 0x1020>; 595 samsung,mode = <USI_V2_I2C>; 596 #address-cells = <1>; 597 #size-cells = <1>; 598 ranges; 599 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 600 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 601 clock-names = "pclk", "ipclk"; 602 status = "disabled"; 603 604 hsi2c_0: i2c@138a0000 { 605 compatible = "samsung,exynosautov9-hsi2c"; 606 reg = <0x138a0000 0xc0>; 607 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&hsi2c0_pins>; 612 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 613 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 614 clock-names = "hsi2c", "hsi2c_pclk"; 615 status = "disabled"; 616 }; 617 }; 618 619 usi_hsi2c_1: usi@138b00c0 { 620 compatible = "samsung,exynos850-usi"; 621 reg = <0x138b00c0 0x20>; 622 samsung,sysreg = <&sysreg_peri 0x1030>; 623 samsung,mode = <USI_V2_I2C>; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 ranges; 627 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 628 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 629 clock-names = "pclk", "ipclk"; 630 status = "disabled"; 631 632 hsi2c_1: i2c@138b0000 { 633 compatible = "samsung,exynosautov9-hsi2c"; 634 reg = <0x138b0000 0xc0>; 635 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&hsi2c1_pins>; 640 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 641 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 642 clock-names = "hsi2c", "hsi2c_pclk"; 643 status = "disabled"; 644 }; 645 }; 646 647 usi_hsi2c_2: usi@138c00c0 { 648 compatible = "samsung,exynos850-usi"; 649 reg = <0x138c00c0 0x20>; 650 samsung,sysreg = <&sysreg_peri 0x1040>; 651 samsung,mode = <USI_V2_I2C>; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 ranges; 655 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 656 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 657 clock-names = "pclk", "ipclk"; 658 status = "disabled"; 659 660 hsi2c_2: i2c@138c0000 { 661 compatible = "samsung,exynosautov9-hsi2c"; 662 reg = <0x138c0000 0xc0>; 663 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&hsi2c2_pins>; 668 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 669 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 670 clock-names = "hsi2c", "hsi2c_pclk"; 671 status = "disabled"; 672 }; 673 }; 674 675 usi_spi_0: usi@139400c0 { 676 compatible = "samsung,exynos850-usi"; 677 reg = <0x139400c0 0x20>; 678 samsung,sysreg = <&sysreg_peri 0x1050>; 679 samsung,mode = <USI_V2_SPI>; 680 #address-cells = <1>; 681 #size-cells = <1>; 682 ranges; 683 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 684 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 685 clock-names = "pclk", "ipclk"; 686 status = "disabled"; 687 }; 688 689 usi_cmgp0: usi@11d000c0 { 690 compatible = "samsung,exynos850-usi"; 691 reg = <0x11d000c0 0x20>; 692 samsung,sysreg = <&sysreg_cmgp 0x2000>; 693 samsung,mode = <USI_V2_I2C>; 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges; 697 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 698 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 699 clock-names = "pclk", "ipclk"; 700 status = "disabled"; 701 702 hsi2c_3: i2c@11d00000 { 703 compatible = "samsung,exynosautov9-hsi2c"; 704 reg = <0x11d00000 0xc0>; 705 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&hsi2c3_pins>; 710 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 711 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 712 clock-names = "hsi2c", "hsi2c_pclk"; 713 status = "disabled"; 714 }; 715 716 serial_1: serial@11d00000 { 717 compatible = "samsung,exynos850-uart"; 718 reg = <0x11d00000 0xc0>; 719 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&uart1_single_pins>; 722 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 723 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 724 clock-names = "uart", "clk_uart_baud0"; 725 status = "disabled"; 726 }; 727 }; 728 729 usi_cmgp1: usi@11d200c0 { 730 compatible = "samsung,exynos850-usi"; 731 reg = <0x11d200c0 0x20>; 732 samsung,sysreg = <&sysreg_cmgp 0x2010>; 733 samsung,mode = <USI_V2_I2C>; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 ranges; 737 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 738 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 739 clock-names = "pclk", "ipclk"; 740 status = "disabled"; 741 742 hsi2c_4: i2c@11d20000 { 743 compatible = "samsung,exynosautov9-hsi2c"; 744 reg = <0x11d20000 0xc0>; 745 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&hsi2c4_pins>; 750 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 751 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 752 clock-names = "hsi2c", "hsi2c_pclk"; 753 status = "disabled"; 754 }; 755 756 serial_2: serial@11d20000 { 757 compatible = "samsung,exynos850-uart"; 758 reg = <0x11d20000 0xc0>; 759 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&uart2_single_pins>; 762 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 763 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 764 clock-names = "uart", "clk_uart_baud0"; 765 status = "disabled"; 766 }; 767 }; 768 }; 769}; 770 771#include "exynos850-pinctrl.dtsi" 772