1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a55-pmu"; 36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 46 }; 47 48 /* Main system clock (XTCXO); external, must be 26 MHz */ 49 oscclk: clock-oscclk { 50 compatible = "fixed-clock"; 51 clock-output-names = "oscclk"; 52 #clock-cells = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 75 cluster1 { 76 core0 { 77 cpu = <&cpu4>; 78 }; 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 core2 { 83 cpu = <&cpu6>; 84 }; 85 core3 { 86 cpu = <&cpu7>; 87 }; 88 }; 89 }; 90 91 cpu0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; 97 clock-names = "cluster0_clk"; 98 }; 99 cpu1: cpu@1 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x1>; 103 enable-method = "psci"; 104 }; 105 cpu2: cpu@2 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a55"; 108 reg = <0x2>; 109 enable-method = "psci"; 110 }; 111 cpu3: cpu@3 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x3>; 115 enable-method = "psci"; 116 }; 117 cpu4: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a55"; 120 reg = <0x100>; 121 enable-method = "psci"; 122 clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; 123 clock-names = "cluster1_clk"; 124 }; 125 cpu5: cpu@101 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a55"; 128 reg = <0x101>; 129 enable-method = "psci"; 130 }; 131 cpu6: cpu@102 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x102>; 135 enable-method = "psci"; 136 }; 137 cpu7: cpu@103 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a55"; 140 reg = <0x103>; 141 enable-method = "psci"; 142 }; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 153 interrupts = 154 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 158 }; 159 160 soc: soc@0 { 161 compatible = "simple-bus"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0x0 0x0 0x0 0x20000000>; 165 166 chipid@10000000 { 167 compatible = "samsung,exynos850-chipid"; 168 reg = <0x10000000 0x100>; 169 }; 170 171 timer@10040000 { 172 compatible = "samsung,exynos850-mct", 173 "samsung,exynos4210-mct"; 174 reg = <0x10040000 0x800>; 175 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 188 clock-names = "fin_pll", "mct"; 189 }; 190 191 pdma0: dma-controller@120c0000 { 192 compatible = "arm,pl330", "arm,primecell"; 193 reg = <0x120c0000 0x1000>; 194 clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>; 195 clock-names = "apb_pclk"; 196 #dma-cells = <1>; 197 interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; 198 arm,pl330-broken-no-flushp; 199 }; 200 201 gic: interrupt-controller@12a01000 { 202 compatible = "arm,gic-400"; 203 #interrupt-cells = <3>; 204 #address-cells = <0>; 205 reg = <0x12a01000 0x1000>, 206 <0x12a02000 0x2000>, 207 <0x12a04000 0x2000>, 208 <0x12a06000 0x2000>; 209 interrupt-controller; 210 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 211 IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 pmu_system_controller: system-controller@11860000 { 215 compatible = "samsung,exynos850-pmu", "syscon"; 216 reg = <0x11860000 0x10000>; 217 218 reboot: syscon-reboot { 219 compatible = "syscon-reboot"; 220 regmap = <&pmu_system_controller>; 221 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 222 mask = <0x2>; /* SWRESET_SYSTEM */ 223 value = <0x2>; /* reset value */ 224 }; 225 }; 226 227 watchdog_cl0: watchdog@10050000 { 228 compatible = "samsung,exynos850-wdt"; 229 reg = <0x10050000 0x100>; 230 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 232 clock-names = "watchdog", "watchdog_src"; 233 samsung,syscon-phandle = <&pmu_system_controller>; 234 samsung,cluster-index = <0>; 235 status = "disabled"; 236 }; 237 238 watchdog_cl1: watchdog@10060000 { 239 compatible = "samsung,exynos850-wdt"; 240 reg = <0x10060000 0x100>; 241 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 243 clock-names = "watchdog", "watchdog_src"; 244 samsung,syscon-phandle = <&pmu_system_controller>; 245 samsung,cluster-index = <1>; 246 status = "disabled"; 247 }; 248 249 cmu_peri: clock-controller@10030000 { 250 compatible = "samsung,exynos850-cmu-peri"; 251 reg = <0x10030000 0x8000>; 252 #clock-cells = <1>; 253 254 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 255 <&cmu_top CLK_DOUT_PERI_UART>, 256 <&cmu_top CLK_DOUT_PERI_IP>; 257 clock-names = "oscclk", "dout_peri_bus", 258 "dout_peri_uart", "dout_peri_ip"; 259 }; 260 261 cmu_cpucl1: clock-controller@10800000 { 262 compatible = "samsung,exynos850-cmu-cpucl1"; 263 reg = <0x10800000 0x8000>; 264 #clock-cells = <1>; 265 266 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>, 267 <&cmu_top CLK_DOUT_CPUCL1_DBG>; 268 clock-names = "oscclk", "dout_cpucl1_switch", 269 "dout_cpucl1_dbg"; 270 }; 271 272 cmu_cpucl0: clock-controller@10900000 { 273 compatible = "samsung,exynos850-cmu-cpucl0"; 274 reg = <0x10900000 0x8000>; 275 #clock-cells = <1>; 276 277 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>, 278 <&cmu_top CLK_DOUT_CPUCL0_DBG>; 279 clock-names = "oscclk", "dout_cpucl0_switch", 280 "dout_cpucl0_dbg"; 281 }; 282 283 cmu_g3d: clock-controller@11400000 { 284 compatible = "samsung,exynos850-cmu-g3d"; 285 reg = <0x11400000 0x8000>; 286 #clock-cells = <1>; 287 288 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; 289 clock-names = "oscclk", "dout_g3d_switch"; 290 }; 291 292 cmu_apm: clock-controller@11800000 { 293 compatible = "samsung,exynos850-cmu-apm"; 294 reg = <0x11800000 0x8000>; 295 #clock-cells = <1>; 296 297 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 298 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 299 }; 300 301 cmu_cmgp: clock-controller@11c00000 { 302 compatible = "samsung,exynos850-cmu-cmgp"; 303 reg = <0x11c00000 0x8000>; 304 #clock-cells = <1>; 305 306 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 307 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 308 }; 309 310 cmu_core: clock-controller@12000000 { 311 compatible = "samsung,exynos850-cmu-core"; 312 reg = <0x12000000 0x8000>; 313 #clock-cells = <1>; 314 315 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 316 <&cmu_top CLK_DOUT_CORE_CCI>, 317 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 318 <&cmu_top CLK_DOUT_CORE_SSS>; 319 clock-names = "oscclk", "dout_core_bus", 320 "dout_core_cci", "dout_core_mmc_embd", 321 "dout_core_sss"; 322 }; 323 324 cmu_top: clock-controller@120e0000 { 325 compatible = "samsung,exynos850-cmu-top"; 326 reg = <0x120e0000 0x8000>; 327 #clock-cells = <1>; 328 329 clocks = <&oscclk>; 330 clock-names = "oscclk"; 331 }; 332 333 cmu_mfcmscl: clock-controller@12c00000 { 334 compatible = "samsung,exynos850-cmu-mfcmscl"; 335 reg = <0x12c00000 0x8000>; 336 #clock-cells = <1>; 337 338 clocks = <&oscclk>, 339 <&cmu_top CLK_DOUT_MFCMSCL_MFC>, 340 <&cmu_top CLK_DOUT_MFCMSCL_M2M>, 341 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, 342 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; 343 clock-names = "oscclk", "dout_mfcmscl_mfc", 344 "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", 345 "dout_mfcmscl_jpeg"; 346 }; 347 348 cmu_dpu: clock-controller@13000000 { 349 compatible = "samsung,exynos850-cmu-dpu"; 350 reg = <0x13000000 0x8000>; 351 #clock-cells = <1>; 352 353 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 354 clock-names = "oscclk", "dout_dpu"; 355 }; 356 357 cmu_hsi: clock-controller@13400000 { 358 compatible = "samsung,exynos850-cmu-hsi"; 359 reg = <0x13400000 0x8000>; 360 #clock-cells = <1>; 361 362 clocks = <&oscclk>, 363 <&cmu_top CLK_DOUT_HSI_BUS>, 364 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 365 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 366 clock-names = "oscclk", "dout_hsi_bus", 367 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 368 }; 369 370 cmu_is: clock-controller@14500000 { 371 compatible = "samsung,exynos850-cmu-is"; 372 reg = <0x14500000 0x8000>; 373 #clock-cells = <1>; 374 375 clocks = <&oscclk>, 376 <&cmu_top CLK_DOUT_IS_BUS>, 377 <&cmu_top CLK_DOUT_IS_ITP>, 378 <&cmu_top CLK_DOUT_IS_VRA>, 379 <&cmu_top CLK_DOUT_IS_GDC>; 380 clock-names = "oscclk", "dout_is_bus", "dout_is_itp", 381 "dout_is_vra", "dout_is_gdc"; 382 }; 383 384 cmu_aud: clock-controller@14a00000 { 385 compatible = "samsung,exynos850-cmu-aud"; 386 reg = <0x14a00000 0x8000>; 387 #clock-cells = <1>; 388 389 clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; 390 clock-names = "oscclk", "dout_aud"; 391 }; 392 393 pinctrl_alive: pinctrl@11850000 { 394 compatible = "samsung,exynos850-pinctrl"; 395 reg = <0x11850000 0x1000>; 396 397 wakeup-interrupt-controller { 398 compatible = "samsung,exynos850-wakeup-eint", 399 "samsung,exynos7-wakeup-eint"; 400 }; 401 }; 402 403 pinctrl_cmgp: pinctrl@11c30000 { 404 compatible = "samsung,exynos850-pinctrl"; 405 reg = <0x11c30000 0x1000>; 406 407 wakeup-interrupt-controller { 408 compatible = "samsung,exynos850-wakeup-eint", 409 "samsung,exynos7-wakeup-eint"; 410 }; 411 }; 412 413 pinctrl_core: pinctrl@12070000 { 414 compatible = "samsung,exynos850-pinctrl"; 415 reg = <0x12070000 0x1000>; 416 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 417 }; 418 419 trng: rng@12081400 { 420 compatible = "samsung,exynos850-trng"; 421 reg = <0x12081400 0x100>; 422 clocks = <&cmu_core CLK_GOUT_SSS_ACLK>, 423 <&cmu_core CLK_GOUT_SSS_PCLK>; 424 clock-names = "secss", "pclk"; 425 }; 426 427 pinctrl_hsi: pinctrl@13430000 { 428 compatible = "samsung,exynos850-pinctrl"; 429 reg = <0x13430000 0x1000>; 430 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 431 }; 432 433 pinctrl_peri: pinctrl@139b0000 { 434 compatible = "samsung,exynos850-pinctrl"; 435 reg = <0x139b0000 0x1000>; 436 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 437 }; 438 439 pinctrl_aud: pinctrl@14a60000 { 440 compatible = "samsung,exynos850-pinctrl"; 441 reg = <0x14a60000 0x1000>; 442 }; 443 444 rtc: rtc@11a30000 { 445 compatible = "samsung,exynos850-rtc", "samsung,s3c6410-rtc"; 446 reg = <0x11a30000 0x100>; 447 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 450 clock-names = "rtc"; 451 status = "disabled"; 452 }; 453 454 mmc_0: mmc@12100000 { 455 compatible = "samsung,exynos850-dw-mshc-smu", 456 "samsung,exynos7-dw-mshc-smu"; 457 reg = <0x12100000 0x2000>; 458 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 462 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 463 clock-names = "biu", "ciu"; 464 fifo-depth = <0x40>; 465 status = "disabled"; 466 }; 467 468 i2c_0: i2c@13830000 { 469 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 470 reg = <0x13830000 0x100>; 471 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&i2c0_pins>; 476 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 477 clock-names = "i2c"; 478 status = "disabled"; 479 }; 480 481 i2c_1: i2c@13840000 { 482 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 483 reg = <0x13840000 0x100>; 484 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&i2c1_pins>; 489 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 490 clock-names = "i2c"; 491 status = "disabled"; 492 }; 493 494 i2c_2: i2c@13850000 { 495 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 496 reg = <0x13850000 0x100>; 497 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c2_pins>; 502 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 503 clock-names = "i2c"; 504 status = "disabled"; 505 }; 506 507 i2c_3: i2c@13860000 { 508 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 509 reg = <0x13860000 0x100>; 510 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&i2c3_pins>; 515 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 516 clock-names = "i2c"; 517 status = "disabled"; 518 }; 519 520 i2c_4: i2c@13870000 { 521 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 522 reg = <0x13870000 0x100>; 523 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c4_pins>; 528 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 529 clock-names = "i2c"; 530 status = "disabled"; 531 }; 532 533 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 534 i2c_5: i2c@13880000 { 535 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 536 reg = <0x13880000 0x100>; 537 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&i2c5_pins>; 542 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 543 clock-names = "i2c"; 544 status = "disabled"; 545 }; 546 547 /* I2C_6 (also called MOTOR_I2C in TRM) */ 548 i2c_6: i2c@13890000 { 549 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 550 reg = <0x13890000 0x100>; 551 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c6_pins>; 556 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 557 clock-names = "i2c"; 558 status = "disabled"; 559 }; 560 561 sysmmu_mfcmscl: sysmmu@12c50000 { 562 compatible = "samsung,exynos-sysmmu"; 563 reg = <0x12c50000 0x9000>; 564 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 565 clock-names = "sysmmu"; 566 clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; 567 #iommu-cells = <0>; 568 }; 569 570 sysmmu_dpu: sysmmu@130c0000 { 571 compatible = "samsung,exynos-sysmmu"; 572 reg = <0x130c0000 0x9000>; 573 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 574 clock-names = "sysmmu"; 575 clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; 576 #iommu-cells = <0>; 577 }; 578 579 sysmmu_is0: sysmmu@14550000 { 580 compatible = "samsung,exynos-sysmmu"; 581 reg = <0x14550000 0x9000>; 582 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 583 clock-names = "sysmmu"; 584 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; 585 #iommu-cells = <0>; 586 }; 587 588 sysmmu_is1: sysmmu@14570000 { 589 compatible = "samsung,exynos-sysmmu"; 590 reg = <0x14570000 0x9000>; 591 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 592 clock-names = "sysmmu"; 593 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; 594 #iommu-cells = <0>; 595 }; 596 597 sysmmu_aud: sysmmu@14850000 { 598 compatible = "samsung,exynos-sysmmu"; 599 reg = <0x14850000 0x9000>; 600 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 601 clock-names = "sysmmu"; 602 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; 603 #iommu-cells = <0>; 604 }; 605 606 sysreg_peri: syscon@10020000 { 607 compatible = "samsung,exynos850-peri-sysreg", 608 "samsung,exynos850-sysreg", "syscon"; 609 reg = <0x10020000 0x10000>; 610 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 611 }; 612 613 sysreg_cmgp: syscon@11c20000 { 614 compatible = "samsung,exynos850-cmgp-sysreg", 615 "samsung,exynos850-sysreg", "syscon"; 616 reg = <0x11c20000 0x10000>; 617 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 618 }; 619 620 usbdrd: usb@13600000 { 621 compatible = "samsung,exynos850-dwusb3"; 622 ranges = <0x0 0x13600000 0x10000>; 623 clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>, 624 <&cmu_hsi CLK_GOUT_USB_REF_CLK>; 625 clock-names = "bus_early", "ref"; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 status = "disabled"; 629 630 usbdrd_dwc3: usb@0 { 631 compatible = "snps,dwc3"; 632 reg = <0x0 0x10000>; 633 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 634 phys = <&usbdrd_phy 0>; 635 phy-names = "usb2-phy"; 636 }; 637 }; 638 639 usbdrd_phy: phy@135d0000 { 640 compatible = "samsung,exynos850-usbdrd-phy"; 641 reg = <0x135d0000 0x100>; 642 clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>, 643 <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>; 644 clock-names = "phy", "ref"; 645 samsung,pmu-syscon = <&pmu_system_controller>; 646 #phy-cells = <1>; 647 status = "disabled"; 648 }; 649 650 usi_uart: usi@138200c0 { 651 compatible = "samsung,exynos850-usi"; 652 reg = <0x138200c0 0x20>; 653 samsung,sysreg = <&sysreg_peri 0x1010>; 654 samsung,mode = <USI_V2_UART>; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 ranges; 658 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 659 <&cmu_peri CLK_GOUT_UART_IPCLK>; 660 clock-names = "pclk", "ipclk"; 661 status = "disabled"; 662 663 serial_0: serial@13820000 { 664 compatible = "samsung,exynos850-uart"; 665 reg = <0x13820000 0xc0>; 666 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&uart0_pins>; 669 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 670 <&cmu_peri CLK_GOUT_UART_IPCLK>; 671 clock-names = "uart", "clk_uart_baud0"; 672 status = "disabled"; 673 }; 674 }; 675 676 usi_hsi2c_0: usi@138a00c0 { 677 compatible = "samsung,exynos850-usi"; 678 reg = <0x138a00c0 0x20>; 679 samsung,sysreg = <&sysreg_peri 0x1020>; 680 samsung,mode = <USI_V2_I2C>; 681 #address-cells = <1>; 682 #size-cells = <1>; 683 ranges; 684 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 685 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 686 clock-names = "pclk", "ipclk"; 687 status = "disabled"; 688 689 hsi2c_0: i2c@138a0000 { 690 compatible = "samsung,exynos850-hsi2c", 691 "samsung,exynosautov9-hsi2c"; 692 reg = <0x138a0000 0xc0>; 693 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&hsi2c0_pins>; 698 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 699 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 700 clock-names = "hsi2c", "hsi2c_pclk"; 701 status = "disabled"; 702 }; 703 }; 704 705 usi_hsi2c_1: usi@138b00c0 { 706 compatible = "samsung,exynos850-usi"; 707 reg = <0x138b00c0 0x20>; 708 samsung,sysreg = <&sysreg_peri 0x1030>; 709 samsung,mode = <USI_V2_I2C>; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 ranges; 713 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 714 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 715 clock-names = "pclk", "ipclk"; 716 status = "disabled"; 717 718 hsi2c_1: i2c@138b0000 { 719 compatible = "samsung,exynos850-hsi2c", 720 "samsung,exynosautov9-hsi2c"; 721 reg = <0x138b0000 0xc0>; 722 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&hsi2c1_pins>; 727 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 728 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 729 clock-names = "hsi2c", "hsi2c_pclk"; 730 status = "disabled"; 731 }; 732 }; 733 734 usi_hsi2c_2: usi@138c00c0 { 735 compatible = "samsung,exynos850-usi"; 736 reg = <0x138c00c0 0x20>; 737 samsung,sysreg = <&sysreg_peri 0x1040>; 738 samsung,mode = <USI_V2_I2C>; 739 #address-cells = <1>; 740 #size-cells = <1>; 741 ranges; 742 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 743 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 744 clock-names = "pclk", "ipclk"; 745 status = "disabled"; 746 747 hsi2c_2: i2c@138c0000 { 748 compatible = "samsung,exynos850-hsi2c", 749 "samsung,exynosautov9-hsi2c"; 750 reg = <0x138c0000 0xc0>; 751 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 pinctrl-names = "default"; 755 pinctrl-0 = <&hsi2c2_pins>; 756 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 757 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 758 clock-names = "hsi2c", "hsi2c_pclk"; 759 status = "disabled"; 760 }; 761 }; 762 763 usi_spi_0: usi@139400c0 { 764 compatible = "samsung,exynos850-usi"; 765 reg = <0x139400c0 0x20>; 766 samsung,sysreg = <&sysreg_peri 0x1050>; 767 samsung,mode = <USI_V2_SPI>; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges; 771 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 772 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 773 clock-names = "pclk", "ipclk"; 774 status = "disabled"; 775 776 spi_0: spi@13940000 { 777 compatible = "samsung,exynos850-spi"; 778 reg = <0x13940000 0x30>; 779 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 780 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 781 clock-names = "spi", "spi_busclk0"; 782 dmas = <&pdma0 5>, <&pdma0 4>; 783 dma-names = "tx", "rx"; 784 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 785 pinctrl-0 = <&spi0_pins>; 786 pinctrl-names = "default"; 787 num-cs = <1>; 788 samsung,spi-src-clk = <0>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 }; 794 795 usi_cmgp0: usi@11d000c0 { 796 compatible = "samsung,exynos850-usi"; 797 reg = <0x11d000c0 0x20>; 798 samsung,sysreg = <&sysreg_cmgp 0x2000>; 799 samsung,mode = <USI_V2_I2C>; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 ranges; 803 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 804 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 805 clock-names = "pclk", "ipclk"; 806 status = "disabled"; 807 808 hsi2c_3: i2c@11d00000 { 809 compatible = "samsung,exynos850-hsi2c", 810 "samsung,exynosautov9-hsi2c"; 811 reg = <0x11d00000 0xc0>; 812 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&hsi2c3_pins>; 817 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 818 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 819 clock-names = "hsi2c", "hsi2c_pclk"; 820 status = "disabled"; 821 }; 822 823 serial_1: serial@11d00000 { 824 compatible = "samsung,exynos850-uart"; 825 reg = <0x11d00000 0xc0>; 826 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&uart1_single_pins>; 829 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 830 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 831 clock-names = "uart", "clk_uart_baud0"; 832 status = "disabled"; 833 }; 834 835 spi_1: spi@11d00000 { 836 compatible = "samsung,exynos850-spi"; 837 reg = <0x11d00000 0x30>; 838 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 839 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 840 clock-names = "spi", "spi_busclk0"; 841 dmas = <&pdma0 12>, <&pdma0 13>; 842 dma-names = "tx", "rx"; 843 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 844 pinctrl-0 = <&spi1_pins>; 845 pinctrl-names = "default"; 846 num-cs = <1>; 847 samsung,spi-src-clk = <0>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 status = "disabled"; 851 }; 852 }; 853 854 usi_cmgp1: usi@11d200c0 { 855 compatible = "samsung,exynos850-usi"; 856 reg = <0x11d200c0 0x20>; 857 samsung,sysreg = <&sysreg_cmgp 0x2010>; 858 samsung,mode = <USI_V2_I2C>; 859 #address-cells = <1>; 860 #size-cells = <1>; 861 ranges; 862 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 863 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 864 clock-names = "pclk", "ipclk"; 865 status = "disabled"; 866 867 hsi2c_4: i2c@11d20000 { 868 compatible = "samsung,exynos850-hsi2c", 869 "samsung,exynosautov9-hsi2c"; 870 reg = <0x11d20000 0xc0>; 871 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&hsi2c4_pins>; 876 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 877 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 878 clock-names = "hsi2c", "hsi2c_pclk"; 879 status = "disabled"; 880 }; 881 882 serial_2: serial@11d20000 { 883 compatible = "samsung,exynos850-uart"; 884 reg = <0x11d20000 0xc0>; 885 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&uart2_single_pins>; 888 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 889 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 890 clock-names = "uart", "clk_uart_baud0"; 891 status = "disabled"; 892 }; 893 894 spi_2: spi@11d20000 { 895 compatible = "samsung,exynos850-spi"; 896 reg = <0x11d20000 0x30>; 897 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 898 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 899 clock-names = "spi", "spi_busclk0"; 900 dmas = <&pdma0 14>, <&pdma0 15>; 901 dma-names = "tx", "rx"; 902 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 903 pinctrl-0 = <&spi2_pins>; 904 pinctrl-names = "default"; 905 num-cs = <1>; 906 samsung,spi-src-clk = <0>; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 status = "disabled"; 910 }; 911 }; 912 }; 913}; 914 915#include "exynos850-pinctrl.dtsi" 916