1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a55-pmu"; 36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 46 }; 47 48 /* Main system clock (XTCXO); external, must be 26 MHz */ 49 oscclk: clock-oscclk { 50 compatible = "fixed-clock"; 51 clock-output-names = "oscclk"; 52 #clock-cells = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 75 cluster1 { 76 core0 { 77 cpu = <&cpu4>; 78 }; 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 core2 { 83 cpu = <&cpu6>; 84 }; 85 core3 { 86 cpu = <&cpu7>; 87 }; 88 }; 89 }; 90 91 cpu0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 }; 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x1>; 101 enable-method = "psci"; 102 }; 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a55"; 106 reg = <0x2>; 107 enable-method = "psci"; 108 }; 109 cpu3: cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x3>; 113 enable-method = "psci"; 114 }; 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 }; 121 cpu5: cpu@101 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x101>; 125 enable-method = "psci"; 126 }; 127 cpu6: cpu@102 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a55"; 130 reg = <0x102>; 131 enable-method = "psci"; 132 }; 133 cpu7: cpu@103 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a55"; 136 reg = <0x103>; 137 enable-method = "psci"; 138 }; 139 }; 140 141 psci { 142 compatible = "arm,psci-1.0"; 143 method = "smc"; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 149 interrupts = 150 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 154 }; 155 156 soc: soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 ranges = <0x0 0x0 0x0 0x20000000>; 161 162 chipid@10000000 { 163 compatible = "samsung,exynos850-chipid"; 164 reg = <0x10000000 0x100>; 165 }; 166 167 timer@10040000 { 168 compatible = "samsung,exynos850-mct", 169 "samsung,exynos4210-mct"; 170 reg = <0x10040000 0x800>; 171 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 184 clock-names = "fin_pll", "mct"; 185 }; 186 187 pdma0: dma-controller@120c0000 { 188 compatible = "arm,pl330", "arm,primecell"; 189 reg = <0x120c0000 0x1000>; 190 clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>; 191 clock-names = "apb_pclk"; 192 #dma-cells = <1>; 193 interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; 194 arm,pl330-broken-no-flushp; 195 }; 196 197 gic: interrupt-controller@12a01000 { 198 compatible = "arm,gic-400"; 199 #interrupt-cells = <3>; 200 #address-cells = <0>; 201 reg = <0x12a01000 0x1000>, 202 <0x12a02000 0x2000>, 203 <0x12a04000 0x2000>, 204 <0x12a06000 0x2000>; 205 interrupt-controller; 206 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 207 IRQ_TYPE_LEVEL_HIGH)>; 208 }; 209 210 pmu_system_controller: system-controller@11860000 { 211 compatible = "samsung,exynos850-pmu", "syscon"; 212 reg = <0x11860000 0x10000>; 213 214 reboot: syscon-reboot { 215 compatible = "syscon-reboot"; 216 regmap = <&pmu_system_controller>; 217 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 218 mask = <0x2>; /* SWRESET_SYSTEM */ 219 value = <0x2>; /* reset value */ 220 }; 221 }; 222 223 watchdog_cl0: watchdog@10050000 { 224 compatible = "samsung,exynos850-wdt"; 225 reg = <0x10050000 0x100>; 226 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 228 clock-names = "watchdog", "watchdog_src"; 229 samsung,syscon-phandle = <&pmu_system_controller>; 230 samsung,cluster-index = <0>; 231 status = "disabled"; 232 }; 233 234 watchdog_cl1: watchdog@10060000 { 235 compatible = "samsung,exynos850-wdt"; 236 reg = <0x10060000 0x100>; 237 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 239 clock-names = "watchdog", "watchdog_src"; 240 samsung,syscon-phandle = <&pmu_system_controller>; 241 samsung,cluster-index = <1>; 242 status = "disabled"; 243 }; 244 245 cmu_peri: clock-controller@10030000 { 246 compatible = "samsung,exynos850-cmu-peri"; 247 reg = <0x10030000 0x8000>; 248 #clock-cells = <1>; 249 250 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 251 <&cmu_top CLK_DOUT_PERI_UART>, 252 <&cmu_top CLK_DOUT_PERI_IP>; 253 clock-names = "oscclk", "dout_peri_bus", 254 "dout_peri_uart", "dout_peri_ip"; 255 }; 256 257 cmu_g3d: clock-controller@11400000 { 258 compatible = "samsung,exynos850-cmu-g3d"; 259 reg = <0x11400000 0x8000>; 260 #clock-cells = <1>; 261 262 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; 263 clock-names = "oscclk", "dout_g3d_switch"; 264 }; 265 266 cmu_apm: clock-controller@11800000 { 267 compatible = "samsung,exynos850-cmu-apm"; 268 reg = <0x11800000 0x8000>; 269 #clock-cells = <1>; 270 271 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 272 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 273 }; 274 275 cmu_cmgp: clock-controller@11c00000 { 276 compatible = "samsung,exynos850-cmu-cmgp"; 277 reg = <0x11c00000 0x8000>; 278 #clock-cells = <1>; 279 280 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 281 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 282 }; 283 284 cmu_core: clock-controller@12000000 { 285 compatible = "samsung,exynos850-cmu-core"; 286 reg = <0x12000000 0x8000>; 287 #clock-cells = <1>; 288 289 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 290 <&cmu_top CLK_DOUT_CORE_CCI>, 291 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 292 <&cmu_top CLK_DOUT_CORE_SSS>; 293 clock-names = "oscclk", "dout_core_bus", 294 "dout_core_cci", "dout_core_mmc_embd", 295 "dout_core_sss"; 296 }; 297 298 cmu_top: clock-controller@120e0000 { 299 compatible = "samsung,exynos850-cmu-top"; 300 reg = <0x120e0000 0x8000>; 301 #clock-cells = <1>; 302 303 clocks = <&oscclk>; 304 clock-names = "oscclk"; 305 }; 306 307 cmu_mfcmscl: clock-controller@12c00000 { 308 compatible = "samsung,exynos850-cmu-mfcmscl"; 309 reg = <0x12c00000 0x8000>; 310 #clock-cells = <1>; 311 312 clocks = <&oscclk>, 313 <&cmu_top CLK_DOUT_MFCMSCL_MFC>, 314 <&cmu_top CLK_DOUT_MFCMSCL_M2M>, 315 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, 316 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; 317 clock-names = "oscclk", "dout_mfcmscl_mfc", 318 "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", 319 "dout_mfcmscl_jpeg"; 320 }; 321 322 cmu_dpu: clock-controller@13000000 { 323 compatible = "samsung,exynos850-cmu-dpu"; 324 reg = <0x13000000 0x8000>; 325 #clock-cells = <1>; 326 327 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 328 clock-names = "oscclk", "dout_dpu"; 329 }; 330 331 cmu_hsi: clock-controller@13400000 { 332 compatible = "samsung,exynos850-cmu-hsi"; 333 reg = <0x13400000 0x8000>; 334 #clock-cells = <1>; 335 336 clocks = <&oscclk>, 337 <&cmu_top CLK_DOUT_HSI_BUS>, 338 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 339 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 340 clock-names = "oscclk", "dout_hsi_bus", 341 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 342 }; 343 344 cmu_is: clock-controller@14500000 { 345 compatible = "samsung,exynos850-cmu-is"; 346 reg = <0x14500000 0x8000>; 347 #clock-cells = <1>; 348 349 clocks = <&oscclk>, 350 <&cmu_top CLK_DOUT_IS_BUS>, 351 <&cmu_top CLK_DOUT_IS_ITP>, 352 <&cmu_top CLK_DOUT_IS_VRA>, 353 <&cmu_top CLK_DOUT_IS_GDC>; 354 clock-names = "oscclk", "dout_is_bus", "dout_is_itp", 355 "dout_is_vra", "dout_is_gdc"; 356 }; 357 358 cmu_aud: clock-controller@14a00000 { 359 compatible = "samsung,exynos850-cmu-aud"; 360 reg = <0x14a00000 0x8000>; 361 #clock-cells = <1>; 362 363 clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; 364 clock-names = "oscclk", "dout_aud"; 365 }; 366 367 pinctrl_alive: pinctrl@11850000 { 368 compatible = "samsung,exynos850-pinctrl"; 369 reg = <0x11850000 0x1000>; 370 371 wakeup-interrupt-controller { 372 compatible = "samsung,exynos850-wakeup-eint", 373 "samsung,exynos7-wakeup-eint"; 374 }; 375 }; 376 377 pinctrl_cmgp: pinctrl@11c30000 { 378 compatible = "samsung,exynos850-pinctrl"; 379 reg = <0x11c30000 0x1000>; 380 381 wakeup-interrupt-controller { 382 compatible = "samsung,exynos850-wakeup-eint", 383 "samsung,exynos7-wakeup-eint"; 384 }; 385 }; 386 387 pinctrl_core: pinctrl@12070000 { 388 compatible = "samsung,exynos850-pinctrl"; 389 reg = <0x12070000 0x1000>; 390 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 391 }; 392 393 pinctrl_hsi: pinctrl@13430000 { 394 compatible = "samsung,exynos850-pinctrl"; 395 reg = <0x13430000 0x1000>; 396 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 397 }; 398 399 pinctrl_peri: pinctrl@139b0000 { 400 compatible = "samsung,exynos850-pinctrl"; 401 reg = <0x139b0000 0x1000>; 402 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 403 }; 404 405 pinctrl_aud: pinctrl@14a60000 { 406 compatible = "samsung,exynos850-pinctrl"; 407 reg = <0x14a60000 0x1000>; 408 }; 409 410 rtc: rtc@11a30000 { 411 compatible = "samsung,exynos850-rtc", "samsung,s3c6410-rtc"; 412 reg = <0x11a30000 0x100>; 413 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 416 clock-names = "rtc"; 417 status = "disabled"; 418 }; 419 420 mmc_0: mmc@12100000 { 421 compatible = "samsung,exynos850-dw-mshc-smu", 422 "samsung,exynos7-dw-mshc-smu"; 423 reg = <0x12100000 0x2000>; 424 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 428 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 429 clock-names = "biu", "ciu"; 430 fifo-depth = <0x40>; 431 status = "disabled"; 432 }; 433 434 i2c_0: i2c@13830000 { 435 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 436 reg = <0x13830000 0x100>; 437 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&i2c0_pins>; 442 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 443 clock-names = "i2c"; 444 status = "disabled"; 445 }; 446 447 i2c_1: i2c@13840000 { 448 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 449 reg = <0x13840000 0x100>; 450 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&i2c1_pins>; 455 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 456 clock-names = "i2c"; 457 status = "disabled"; 458 }; 459 460 i2c_2: i2c@13850000 { 461 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 462 reg = <0x13850000 0x100>; 463 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&i2c2_pins>; 468 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 469 clock-names = "i2c"; 470 status = "disabled"; 471 }; 472 473 i2c_3: i2c@13860000 { 474 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 475 reg = <0x13860000 0x100>; 476 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&i2c3_pins>; 481 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 482 clock-names = "i2c"; 483 status = "disabled"; 484 }; 485 486 i2c_4: i2c@13870000 { 487 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 488 reg = <0x13870000 0x100>; 489 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&i2c4_pins>; 494 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 495 clock-names = "i2c"; 496 status = "disabled"; 497 }; 498 499 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 500 i2c_5: i2c@13880000 { 501 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 502 reg = <0x13880000 0x100>; 503 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&i2c5_pins>; 508 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 509 clock-names = "i2c"; 510 status = "disabled"; 511 }; 512 513 /* I2C_6 (also called MOTOR_I2C in TRM) */ 514 i2c_6: i2c@13890000 { 515 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 516 reg = <0x13890000 0x100>; 517 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&i2c6_pins>; 522 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 523 clock-names = "i2c"; 524 status = "disabled"; 525 }; 526 527 sysmmu_mfcmscl: sysmmu@12c50000 { 528 compatible = "samsung,exynos-sysmmu"; 529 reg = <0x12c50000 0x9000>; 530 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 531 clock-names = "sysmmu"; 532 clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; 533 #iommu-cells = <0>; 534 }; 535 536 sysmmu_dpu: sysmmu@130c0000 { 537 compatible = "samsung,exynos-sysmmu"; 538 reg = <0x130c0000 0x9000>; 539 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 540 clock-names = "sysmmu"; 541 clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; 542 #iommu-cells = <0>; 543 }; 544 545 sysmmu_is0: sysmmu@14550000 { 546 compatible = "samsung,exynos-sysmmu"; 547 reg = <0x14550000 0x9000>; 548 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 549 clock-names = "sysmmu"; 550 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; 551 #iommu-cells = <0>; 552 }; 553 554 sysmmu_is1: sysmmu@14570000 { 555 compatible = "samsung,exynos-sysmmu"; 556 reg = <0x14570000 0x9000>; 557 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 558 clock-names = "sysmmu"; 559 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; 560 #iommu-cells = <0>; 561 }; 562 563 sysmmu_aud: sysmmu@14850000 { 564 compatible = "samsung,exynos-sysmmu"; 565 reg = <0x14850000 0x9000>; 566 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 567 clock-names = "sysmmu"; 568 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; 569 #iommu-cells = <0>; 570 }; 571 572 sysreg_peri: syscon@10020000 { 573 compatible = "samsung,exynos850-peri-sysreg", 574 "samsung,exynos850-sysreg", "syscon"; 575 reg = <0x10020000 0x10000>; 576 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 577 }; 578 579 sysreg_cmgp: syscon@11c20000 { 580 compatible = "samsung,exynos850-cmgp-sysreg", 581 "samsung,exynos850-sysreg", "syscon"; 582 reg = <0x11c20000 0x10000>; 583 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 584 }; 585 586 usbdrd: usb@13600000 { 587 compatible = "samsung,exynos850-dwusb3"; 588 ranges = <0x0 0x13600000 0x10000>; 589 clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>, 590 <&cmu_hsi CLK_GOUT_USB_REF_CLK>; 591 clock-names = "bus_early", "ref"; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 status = "disabled"; 595 596 usbdrd_dwc3: usb@0 { 597 compatible = "snps,dwc3"; 598 reg = <0x0 0x10000>; 599 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 600 phys = <&usbdrd_phy 0>; 601 phy-names = "usb2-phy"; 602 }; 603 }; 604 605 usbdrd_phy: phy@135d0000 { 606 compatible = "samsung,exynos850-usbdrd-phy"; 607 reg = <0x135d0000 0x100>; 608 clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>, 609 <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>; 610 clock-names = "phy", "ref"; 611 samsung,pmu-syscon = <&pmu_system_controller>; 612 #phy-cells = <1>; 613 status = "disabled"; 614 }; 615 616 usi_uart: usi@138200c0 { 617 compatible = "samsung,exynos850-usi"; 618 reg = <0x138200c0 0x20>; 619 samsung,sysreg = <&sysreg_peri 0x1010>; 620 samsung,mode = <USI_V2_UART>; 621 #address-cells = <1>; 622 #size-cells = <1>; 623 ranges; 624 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 625 <&cmu_peri CLK_GOUT_UART_IPCLK>; 626 clock-names = "pclk", "ipclk"; 627 status = "disabled"; 628 629 serial_0: serial@13820000 { 630 compatible = "samsung,exynos850-uart"; 631 reg = <0x13820000 0xc0>; 632 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&uart0_pins>; 635 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 636 <&cmu_peri CLK_GOUT_UART_IPCLK>; 637 clock-names = "uart", "clk_uart_baud0"; 638 status = "disabled"; 639 }; 640 }; 641 642 usi_hsi2c_0: usi@138a00c0 { 643 compatible = "samsung,exynos850-usi"; 644 reg = <0x138a00c0 0x20>; 645 samsung,sysreg = <&sysreg_peri 0x1020>; 646 samsung,mode = <USI_V2_I2C>; 647 #address-cells = <1>; 648 #size-cells = <1>; 649 ranges; 650 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 651 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 652 clock-names = "pclk", "ipclk"; 653 status = "disabled"; 654 655 hsi2c_0: i2c@138a0000 { 656 compatible = "samsung,exynos850-hsi2c", 657 "samsung,exynosautov9-hsi2c"; 658 reg = <0x138a0000 0xc0>; 659 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 pinctrl-names = "default"; 663 pinctrl-0 = <&hsi2c0_pins>; 664 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 665 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 666 clock-names = "hsi2c", "hsi2c_pclk"; 667 status = "disabled"; 668 }; 669 }; 670 671 usi_hsi2c_1: usi@138b00c0 { 672 compatible = "samsung,exynos850-usi"; 673 reg = <0x138b00c0 0x20>; 674 samsung,sysreg = <&sysreg_peri 0x1030>; 675 samsung,mode = <USI_V2_I2C>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges; 679 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 680 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 681 clock-names = "pclk", "ipclk"; 682 status = "disabled"; 683 684 hsi2c_1: i2c@138b0000 { 685 compatible = "samsung,exynos850-hsi2c", 686 "samsung,exynosautov9-hsi2c"; 687 reg = <0x138b0000 0xc0>; 688 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&hsi2c1_pins>; 693 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 694 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 695 clock-names = "hsi2c", "hsi2c_pclk"; 696 status = "disabled"; 697 }; 698 }; 699 700 usi_hsi2c_2: usi@138c00c0 { 701 compatible = "samsung,exynos850-usi"; 702 reg = <0x138c00c0 0x20>; 703 samsung,sysreg = <&sysreg_peri 0x1040>; 704 samsung,mode = <USI_V2_I2C>; 705 #address-cells = <1>; 706 #size-cells = <1>; 707 ranges; 708 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 709 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 710 clock-names = "pclk", "ipclk"; 711 status = "disabled"; 712 713 hsi2c_2: i2c@138c0000 { 714 compatible = "samsung,exynos850-hsi2c", 715 "samsung,exynosautov9-hsi2c"; 716 reg = <0x138c0000 0xc0>; 717 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&hsi2c2_pins>; 722 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 723 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 724 clock-names = "hsi2c", "hsi2c_pclk"; 725 status = "disabled"; 726 }; 727 }; 728 729 usi_spi_0: usi@139400c0 { 730 compatible = "samsung,exynos850-usi"; 731 reg = <0x139400c0 0x20>; 732 samsung,sysreg = <&sysreg_peri 0x1050>; 733 samsung,mode = <USI_V2_SPI>; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 ranges; 737 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 738 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 739 clock-names = "pclk", "ipclk"; 740 status = "disabled"; 741 742 spi_0: spi@13940000 { 743 compatible = "samsung,exynos850-spi"; 744 reg = <0x13940000 0x30>; 745 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 746 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 747 clock-names = "spi", "spi_busclk0"; 748 dmas = <&pdma0 5>, <&pdma0 4>; 749 dma-names = "tx", "rx"; 750 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 751 pinctrl-0 = <&spi0_pins>; 752 pinctrl-names = "default"; 753 num-cs = <1>; 754 samsung,spi-src-clk = <0>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 status = "disabled"; 758 }; 759 }; 760 761 usi_cmgp0: usi@11d000c0 { 762 compatible = "samsung,exynos850-usi"; 763 reg = <0x11d000c0 0x20>; 764 samsung,sysreg = <&sysreg_cmgp 0x2000>; 765 samsung,mode = <USI_V2_I2C>; 766 #address-cells = <1>; 767 #size-cells = <1>; 768 ranges; 769 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 770 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 771 clock-names = "pclk", "ipclk"; 772 status = "disabled"; 773 774 hsi2c_3: i2c@11d00000 { 775 compatible = "samsung,exynos850-hsi2c", 776 "samsung,exynosautov9-hsi2c"; 777 reg = <0x11d00000 0xc0>; 778 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&hsi2c3_pins>; 783 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 784 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 785 clock-names = "hsi2c", "hsi2c_pclk"; 786 status = "disabled"; 787 }; 788 789 serial_1: serial@11d00000 { 790 compatible = "samsung,exynos850-uart"; 791 reg = <0x11d00000 0xc0>; 792 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&uart1_single_pins>; 795 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 796 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 797 clock-names = "uart", "clk_uart_baud0"; 798 status = "disabled"; 799 }; 800 801 spi_1: spi@11d00000 { 802 compatible = "samsung,exynos850-spi"; 803 reg = <0x11d00000 0x30>; 804 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 805 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 806 clock-names = "spi", "spi_busclk0"; 807 dmas = <&pdma0 12>, <&pdma0 13>; 808 dma-names = "tx", "rx"; 809 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 810 pinctrl-0 = <&spi1_pins>; 811 pinctrl-names = "default"; 812 num-cs = <1>; 813 samsung,spi-src-clk = <0>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 }; 819 820 usi_cmgp1: usi@11d200c0 { 821 compatible = "samsung,exynos850-usi"; 822 reg = <0x11d200c0 0x20>; 823 samsung,sysreg = <&sysreg_cmgp 0x2010>; 824 samsung,mode = <USI_V2_I2C>; 825 #address-cells = <1>; 826 #size-cells = <1>; 827 ranges; 828 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 829 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 830 clock-names = "pclk", "ipclk"; 831 status = "disabled"; 832 833 hsi2c_4: i2c@11d20000 { 834 compatible = "samsung,exynos850-hsi2c", 835 "samsung,exynosautov9-hsi2c"; 836 reg = <0x11d20000 0xc0>; 837 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 pinctrl-names = "default"; 841 pinctrl-0 = <&hsi2c4_pins>; 842 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 843 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 844 clock-names = "hsi2c", "hsi2c_pclk"; 845 status = "disabled"; 846 }; 847 848 serial_2: serial@11d20000 { 849 compatible = "samsung,exynos850-uart"; 850 reg = <0x11d20000 0xc0>; 851 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&uart2_single_pins>; 854 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 855 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 856 clock-names = "uart", "clk_uart_baud0"; 857 status = "disabled"; 858 }; 859 860 spi_2: spi@11d20000 { 861 compatible = "samsung,exynos850-spi"; 862 reg = <0x11d20000 0x30>; 863 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 864 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 865 clock-names = "spi", "spi_busclk0"; 866 dmas = <&pdma0 14>, <&pdma0 15>; 867 dma-names = "tx", "rx"; 868 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 869 pinctrl-0 = <&spi2_pins>; 870 pinctrl-names = "default"; 871 num-cs = <1>; 872 samsung,spi-src-clk = <0>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 }; 878 }; 879}; 880 881#include "exynos850-pinctrl.dtsi" 882