xref: /linux/arch/arm64/boot/dts/exynos/exynos7885.dtsi (revision 06874015327ba7bf6aae49ca825a492a2679237f)
1*06874015SDavid Virag// SPDX-License-Identifier: GPL-2.0
2*06874015SDavid Virag/*
3*06874015SDavid Virag * Samsung Exynos7885 SoC device tree source
4*06874015SDavid Virag *
5*06874015SDavid Virag * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6*06874015SDavid Virag * Copyright (c) 2021 Dávid Virág
7*06874015SDavid Virag */
8*06874015SDavid Virag
9*06874015SDavid Virag#include <dt-bindings/clock/exynos7885.h>
10*06874015SDavid Virag#include <dt-bindings/interrupt-controller/arm-gic.h>
11*06874015SDavid Virag
12*06874015SDavid Virag/ {
13*06874015SDavid Virag	compatible = "samsung,exynos7885";
14*06874015SDavid Virag	#address-cells = <2>;
15*06874015SDavid Virag	#size-cells = <1>;
16*06874015SDavid Virag
17*06874015SDavid Virag	interrupt-parent = <&gic>;
18*06874015SDavid Virag
19*06874015SDavid Virag	aliases {
20*06874015SDavid Virag		pinctrl0 = &pinctrl_alive;
21*06874015SDavid Virag		pinctrl1 = &pinctrl_dispaud;
22*06874015SDavid Virag		pinctrl2 = &pinctrl_fsys;
23*06874015SDavid Virag		pinctrl3 = &pinctrl_top;
24*06874015SDavid Virag	};
25*06874015SDavid Virag
26*06874015SDavid Virag	arm-a53-pmu {
27*06874015SDavid Virag		compatible = "arm,cortex-a53-pmu";
28*06874015SDavid Virag		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
29*06874015SDavid Virag			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
30*06874015SDavid Virag			     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
31*06874015SDavid Virag			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
32*06874015SDavid Virag			     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
33*06874015SDavid Virag			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
34*06874015SDavid Virag		interrupt-affinity = <&cpu0>,
35*06874015SDavid Virag				     <&cpu1>,
36*06874015SDavid Virag				     <&cpu2>,
37*06874015SDavid Virag				     <&cpu3>,
38*06874015SDavid Virag				     <&cpu4>,
39*06874015SDavid Virag				     <&cpu5>;
40*06874015SDavid Virag	};
41*06874015SDavid Virag
42*06874015SDavid Virag	arm-a73-pmu {
43*06874015SDavid Virag		compatible = "arm,cortex-a73-pmu";
44*06874015SDavid Virag		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
45*06874015SDavid Virag			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
46*06874015SDavid Virag		interrupt-affinity = <&cpu6>,
47*06874015SDavid Virag				     <&cpu7>;
48*06874015SDavid Virag	};
49*06874015SDavid Virag
50*06874015SDavid Virag	cpus {
51*06874015SDavid Virag		#address-cells = <1>;
52*06874015SDavid Virag		#size-cells = <0>;
53*06874015SDavid Virag
54*06874015SDavid Virag		cpu-map {
55*06874015SDavid Virag			cluster0 {
56*06874015SDavid Virag				core0 {
57*06874015SDavid Virag					cpu = <&cpu0>;
58*06874015SDavid Virag				};
59*06874015SDavid Virag				core1 {
60*06874015SDavid Virag					cpu = <&cpu1>;
61*06874015SDavid Virag				};
62*06874015SDavid Virag				core2 {
63*06874015SDavid Virag					cpu = <&cpu2>;
64*06874015SDavid Virag				};
65*06874015SDavid Virag				core3 {
66*06874015SDavid Virag					cpu = <&cpu3>;
67*06874015SDavid Virag				};
68*06874015SDavid Virag				core4 {
69*06874015SDavid Virag					cpu = <&cpu4>;
70*06874015SDavid Virag				};
71*06874015SDavid Virag				core5 {
72*06874015SDavid Virag					cpu = <&cpu5>;
73*06874015SDavid Virag				};
74*06874015SDavid Virag			};
75*06874015SDavid Virag
76*06874015SDavid Virag			cluster1 {
77*06874015SDavid Virag				core0 {
78*06874015SDavid Virag					cpu = <&cpu6>;
79*06874015SDavid Virag				};
80*06874015SDavid Virag				core1 {
81*06874015SDavid Virag					cpu = <&cpu7>;
82*06874015SDavid Virag				};
83*06874015SDavid Virag			};
84*06874015SDavid Virag		};
85*06874015SDavid Virag
86*06874015SDavid Virag		cpu0: cpu@100 {
87*06874015SDavid Virag			device_type = "cpu";
88*06874015SDavid Virag			compatible = "arm,cortex-a53";
89*06874015SDavid Virag			reg = <0x100>;
90*06874015SDavid Virag			enable-method = "psci";
91*06874015SDavid Virag		};
92*06874015SDavid Virag
93*06874015SDavid Virag		cpu1: cpu@101 {
94*06874015SDavid Virag			device_type = "cpu";
95*06874015SDavid Virag			compatible = "arm,cortex-a53";
96*06874015SDavid Virag			reg = <0x101>;
97*06874015SDavid Virag			enable-method = "psci";
98*06874015SDavid Virag		};
99*06874015SDavid Virag
100*06874015SDavid Virag		cpu2: cpu@102 {
101*06874015SDavid Virag			device_type = "cpu";
102*06874015SDavid Virag			compatible = "arm,cortex-a53";
103*06874015SDavid Virag			reg = <0x102>;
104*06874015SDavid Virag			enable-method = "psci";
105*06874015SDavid Virag		};
106*06874015SDavid Virag
107*06874015SDavid Virag		cpu3: cpu@103 {
108*06874015SDavid Virag			device_type = "cpu";
109*06874015SDavid Virag			compatible = "arm,cortex-a53";
110*06874015SDavid Virag			reg = <0x103>;
111*06874015SDavid Virag			enable-method = "psci";
112*06874015SDavid Virag		};
113*06874015SDavid Virag
114*06874015SDavid Virag		cpu4: cpu@200 {
115*06874015SDavid Virag			device_type = "cpu";
116*06874015SDavid Virag			compatible = "arm,cortex-a53";
117*06874015SDavid Virag			reg = <0x200>;
118*06874015SDavid Virag			enable-method = "psci";
119*06874015SDavid Virag		};
120*06874015SDavid Virag
121*06874015SDavid Virag		cpu5: cpu@201 {
122*06874015SDavid Virag			device_type = "cpu";
123*06874015SDavid Virag			compatible = "arm,cortex-a53";
124*06874015SDavid Virag			reg = <0x201>;
125*06874015SDavid Virag			enable-method = "psci";
126*06874015SDavid Virag		};
127*06874015SDavid Virag
128*06874015SDavid Virag		cpu6: cpu@0 {
129*06874015SDavid Virag			device_type = "cpu";
130*06874015SDavid Virag			compatible = "arm,cortex-a73";
131*06874015SDavid Virag			reg = <0x0>;
132*06874015SDavid Virag			enable-method = "psci";
133*06874015SDavid Virag		};
134*06874015SDavid Virag
135*06874015SDavid Virag		cpu7: cpu@1 {
136*06874015SDavid Virag			device_type = "cpu";
137*06874015SDavid Virag			compatible = "arm,cortex-a73";
138*06874015SDavid Virag			reg = <0x1>;
139*06874015SDavid Virag			enable-method = "psci";
140*06874015SDavid Virag		};
141*06874015SDavid Virag	};
142*06874015SDavid Virag
143*06874015SDavid Virag	psci {
144*06874015SDavid Virag		compatible = "arm,psci";
145*06874015SDavid Virag		method = "smc";
146*06874015SDavid Virag		cpu_suspend = <0xc4000001>;
147*06874015SDavid Virag		cpu_off = <0x84000002>;
148*06874015SDavid Virag		cpu_on = <0xc4000003>;
149*06874015SDavid Virag	};
150*06874015SDavid Virag
151*06874015SDavid Virag	timer {
152*06874015SDavid Virag		compatible = "arm,armv8-timer";
153*06874015SDavid Virag		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
154*06874015SDavid Virag		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
155*06874015SDavid Virag			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
156*06874015SDavid Virag			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
157*06874015SDavid Virag			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
158*06874015SDavid Virag	};
159*06874015SDavid Virag
160*06874015SDavid Virag	fixed-rate-clocks {
161*06874015SDavid Virag		oscclk: osc-clock {
162*06874015SDavid Virag			compatible = "fixed-clock";
163*06874015SDavid Virag			#clock-cells = <0>;
164*06874015SDavid Virag			clock-output-names = "oscclk";
165*06874015SDavid Virag		};
166*06874015SDavid Virag	};
167*06874015SDavid Virag
168*06874015SDavid Virag	soc: soc@0 {
169*06874015SDavid Virag		compatible = "simple-bus";
170*06874015SDavid Virag		#address-cells = <1>;
171*06874015SDavid Virag		#size-cells = <1>;
172*06874015SDavid Virag		ranges = <0x0 0x0 0x0 0x20000000>;
173*06874015SDavid Virag
174*06874015SDavid Virag		chipid@10000000 {
175*06874015SDavid Virag			compatible = "samsung,exynos850-chipid";
176*06874015SDavid Virag			reg = <0x10000000 0x24>;
177*06874015SDavid Virag		};
178*06874015SDavid Virag
179*06874015SDavid Virag		gic: interrupt-controller@12301000 {
180*06874015SDavid Virag			compatible = "arm,gic-400";
181*06874015SDavid Virag			#interrupt-cells = <3>;
182*06874015SDavid Virag			#address-cells = <0>;
183*06874015SDavid Virag			interrupt-controller;
184*06874015SDavid Virag			reg = <0x12301000 0x1000>,
185*06874015SDavid Virag			      <0x12302000 0x2000>,
186*06874015SDavid Virag			      <0x12304000 0x2000>,
187*06874015SDavid Virag			      <0x12306000 0x2000>;
188*06874015SDavid Virag			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
189*06874015SDavid Virag						 IRQ_TYPE_LEVEL_HIGH)>;
190*06874015SDavid Virag		};
191*06874015SDavid Virag
192*06874015SDavid Virag		cmu_peri: clock-controller@10010000 {
193*06874015SDavid Virag			compatible = "samsung,exynos7885-cmu-peri";
194*06874015SDavid Virag			reg = <0x10010000 0x8000>;
195*06874015SDavid Virag			#clock-cells = <1>;
196*06874015SDavid Virag
197*06874015SDavid Virag			clocks = <&oscclk>,
198*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_BUS>,
199*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_SPI0>,
200*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_SPI1>,
201*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_UART0>,
202*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_UART1>,
203*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_UART2>,
204*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_USI0>,
205*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_USI1>,
206*06874015SDavid Virag				 <&cmu_top CLK_DOUT_PERI_USI2>;
207*06874015SDavid Virag			clock-names = "oscclk",
208*06874015SDavid Virag				      "dout_peri_bus",
209*06874015SDavid Virag				      "dout_peri_spi0",
210*06874015SDavid Virag				      "dout_peri_spi1",
211*06874015SDavid Virag				      "dout_peri_uart0",
212*06874015SDavid Virag				      "dout_peri_uart1",
213*06874015SDavid Virag				      "dout_peri_uart2",
214*06874015SDavid Virag				      "dout_peri_usi0",
215*06874015SDavid Virag				      "dout_peri_usi1",
216*06874015SDavid Virag				      "dout_peri_usi2";
217*06874015SDavid Virag		};
218*06874015SDavid Virag
219*06874015SDavid Virag		cmu_core: clock-controller@12000000 {
220*06874015SDavid Virag			compatible = "samsung,exynos7885-cmu-core";
221*06874015SDavid Virag			reg = <0x12000000 0x8000>;
222*06874015SDavid Virag			#clock-cells = <1>;
223*06874015SDavid Virag
224*06874015SDavid Virag			clocks = <&oscclk>,
225*06874015SDavid Virag				 <&cmu_top CLK_DOUT_CORE_BUS>,
226*06874015SDavid Virag				 <&cmu_top CLK_DOUT_CORE_CCI>,
227*06874015SDavid Virag				 <&cmu_top CLK_DOUT_CORE_G3D>;
228*06874015SDavid Virag			clock-names = "oscclk",
229*06874015SDavid Virag				      "dout_core_bus",
230*06874015SDavid Virag				      "dout_core_cci",
231*06874015SDavid Virag				      "dout_core_g3d";
232*06874015SDavid Virag		};
233*06874015SDavid Virag
234*06874015SDavid Virag		cmu_top: clock-controller@12060000 {
235*06874015SDavid Virag			compatible = "samsung,exynos7885-cmu-top";
236*06874015SDavid Virag			reg = <0x12060000 0x8000>;
237*06874015SDavid Virag			#clock-cells = <1>;
238*06874015SDavid Virag
239*06874015SDavid Virag			clocks = <&oscclk>;
240*06874015SDavid Virag			clock-names = "oscclk";
241*06874015SDavid Virag		};
242*06874015SDavid Virag
243*06874015SDavid Virag		pinctrl_alive: pinctrl@11cb0000 {
244*06874015SDavid Virag			compatible = "samsung,exynos7885-pinctrl";
245*06874015SDavid Virag			reg = <0x11cb0000 0x1000>;
246*06874015SDavid Virag
247*06874015SDavid Virag			wakeup-interrupt-controller {
248*06874015SDavid Virag				compatible = "samsung,exynos7-wakeup-eint";
249*06874015SDavid Virag				interrupt-parent = <&gic>;
250*06874015SDavid Virag				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
251*06874015SDavid Virag			};
252*06874015SDavid Virag		};
253*06874015SDavid Virag
254*06874015SDavid Virag		pinctrl_fsys: pinctrl@13430000 {
255*06874015SDavid Virag			compatible = "samsung,exynos7885-pinctrl";
256*06874015SDavid Virag			reg = <0x13430000 0x1000>;
257*06874015SDavid Virag			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
258*06874015SDavid Virag		};
259*06874015SDavid Virag
260*06874015SDavid Virag		pinctrl_top: pinctrl@139b0000 {
261*06874015SDavid Virag			compatible = "samsung,exynos7885-pinctrl";
262*06874015SDavid Virag			reg = <0x139b0000 0x1000>;
263*06874015SDavid Virag			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
264*06874015SDavid Virag		};
265*06874015SDavid Virag
266*06874015SDavid Virag		pinctrl_dispaud: pinctrl@148f0000 {
267*06874015SDavid Virag			compatible = "samsung,exynos7885-pinctrl";
268*06874015SDavid Virag			reg = <0x148f0000 0x1000>;
269*06874015SDavid Virag			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
270*06874015SDavid Virag		};
271*06874015SDavid Virag
272*06874015SDavid Virag		pmu_system_controller: system-controller@11c80000 {
273*06874015SDavid Virag			compatible = "samsung,exynos7-pmu", "syscon";
274*06874015SDavid Virag			reg = <0x11c80000 0x10000>;
275*06874015SDavid Virag		};
276*06874015SDavid Virag
277*06874015SDavid Virag		serial_0: serial@13800000 {
278*06874015SDavid Virag			compatible = "samsung,exynos5433-uart";
279*06874015SDavid Virag			reg = <0x13800000 0x100>;
280*06874015SDavid Virag			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
281*06874015SDavid Virag			pinctrl-names = "default";
282*06874015SDavid Virag			pinctrl-0 = <&uart0_bus>;
283*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
284*06874015SDavid Virag				 <&cmu_peri CLK_GOUT_UART0_PCLK>;
285*06874015SDavid Virag			clock-names = "uart", "clk_uart_baud0";
286*06874015SDavid Virag			samsung,uart-fifosize = <64>;
287*06874015SDavid Virag			status = "disabled";
288*06874015SDavid Virag		};
289*06874015SDavid Virag
290*06874015SDavid Virag		serial_1: serial@13810000 {
291*06874015SDavid Virag			compatible = "samsung,exynos5433-uart";
292*06874015SDavid Virag			reg = <0x13810000 0x100>;
293*06874015SDavid Virag			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
294*06874015SDavid Virag			pinctrl-names = "default";
295*06874015SDavid Virag			pinctrl-0 = <&uart1_bus>;
296*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
297*06874015SDavid Virag				 <&cmu_peri CLK_GOUT_UART1_PCLK>;
298*06874015SDavid Virag			clock-names = "uart", "clk_uart_baud0";
299*06874015SDavid Virag			samsung,uart-fifosize = <256>;
300*06874015SDavid Virag			status = "disabled";
301*06874015SDavid Virag		};
302*06874015SDavid Virag
303*06874015SDavid Virag		serial_2: serial@13820000 {
304*06874015SDavid Virag			compatible = "samsung,exynos5433-uart";
305*06874015SDavid Virag			reg = <0x13820000 0x100>;
306*06874015SDavid Virag			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
307*06874015SDavid Virag			pinctrl-names = "default";
308*06874015SDavid Virag			pinctrl-0 = <&uart2_bus>;
309*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
310*06874015SDavid Virag				 <&cmu_peri CLK_GOUT_UART2_PCLK>;
311*06874015SDavid Virag			clock-names = "uart", "clk_uart_baud0";
312*06874015SDavid Virag			samsung,uart-fifosize = <256>;
313*06874015SDavid Virag			status = "disabled";
314*06874015SDavid Virag		};
315*06874015SDavid Virag
316*06874015SDavid Virag		i2c_0: i2c@13830000 {
317*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
318*06874015SDavid Virag			reg = <0x13830000 0x100>;
319*06874015SDavid Virag			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
320*06874015SDavid Virag			#address-cells = <1>;
321*06874015SDavid Virag			#size-cells = <0>;
322*06874015SDavid Virag			pinctrl-names = "default";
323*06874015SDavid Virag			pinctrl-0 = <&i2c0_bus>;
324*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
325*06874015SDavid Virag			clock-names = "i2c";
326*06874015SDavid Virag			status = "disabled";
327*06874015SDavid Virag		};
328*06874015SDavid Virag
329*06874015SDavid Virag		i2c_1: i2c@13840000 {
330*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
331*06874015SDavid Virag			reg = <0x13840000 0x100>;
332*06874015SDavid Virag			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
333*06874015SDavid Virag			#address-cells = <1>;
334*06874015SDavid Virag			#size-cells = <0>;
335*06874015SDavid Virag			pinctrl-names = "default";
336*06874015SDavid Virag			pinctrl-0 = <&i2c1_bus>;
337*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
338*06874015SDavid Virag			clock-names = "i2c";
339*06874015SDavid Virag			status = "disabled";
340*06874015SDavid Virag		};
341*06874015SDavid Virag
342*06874015SDavid Virag		i2c_2: i2c@13850000 {
343*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
344*06874015SDavid Virag			reg = <0x13850000 0x100>;
345*06874015SDavid Virag			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
346*06874015SDavid Virag			#address-cells = <1>;
347*06874015SDavid Virag			#size-cells = <0>;
348*06874015SDavid Virag			pinctrl-names = "default";
349*06874015SDavid Virag			pinctrl-0 = <&i2c2_bus>;
350*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
351*06874015SDavid Virag			clock-names = "i2c";
352*06874015SDavid Virag			status = "disabled";
353*06874015SDavid Virag		};
354*06874015SDavid Virag
355*06874015SDavid Virag		i2c_3: i2c@13860000 {
356*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
357*06874015SDavid Virag			reg = <0x13860000 0x100>;
358*06874015SDavid Virag			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
359*06874015SDavid Virag			#address-cells = <1>;
360*06874015SDavid Virag			#size-cells = <0>;
361*06874015SDavid Virag			pinctrl-names = "default";
362*06874015SDavid Virag			pinctrl-0 = <&i2c3_bus>;
363*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
364*06874015SDavid Virag			clock-names = "i2c";
365*06874015SDavid Virag			status = "disabled";
366*06874015SDavid Virag		};
367*06874015SDavid Virag
368*06874015SDavid Virag		i2c_4: i2c@13870000 {
369*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
370*06874015SDavid Virag			reg = <0x13870000 0x100>;
371*06874015SDavid Virag			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
372*06874015SDavid Virag			#address-cells = <1>;
373*06874015SDavid Virag			#size-cells = <0>;
374*06874015SDavid Virag			pinctrl-names = "default";
375*06874015SDavid Virag			pinctrl-0 = <&i2c4_bus>;
376*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
377*06874015SDavid Virag			clock-names = "i2c";
378*06874015SDavid Virag			status = "disabled";
379*06874015SDavid Virag		};
380*06874015SDavid Virag
381*06874015SDavid Virag		i2c_5: i2c@13880000 {
382*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
383*06874015SDavid Virag			reg = <0x13880000 0x100>;
384*06874015SDavid Virag			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
385*06874015SDavid Virag			#address-cells = <1>;
386*06874015SDavid Virag			#size-cells = <0>;
387*06874015SDavid Virag			pinctrl-names = "default";
388*06874015SDavid Virag			pinctrl-0 = <&i2c5_bus>;
389*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
390*06874015SDavid Virag			clock-names = "i2c";
391*06874015SDavid Virag			status = "disabled";
392*06874015SDavid Virag		};
393*06874015SDavid Virag
394*06874015SDavid Virag		i2c_6: i2c@13890000 {
395*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
396*06874015SDavid Virag			reg = <0x13890000 0x100>;
397*06874015SDavid Virag			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
398*06874015SDavid Virag			#address-cells = <1>;
399*06874015SDavid Virag			#size-cells = <0>;
400*06874015SDavid Virag			pinctrl-names = "default";
401*06874015SDavid Virag			pinctrl-0 = <&i2c6_bus>;
402*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
403*06874015SDavid Virag			clock-names = "i2c";
404*06874015SDavid Virag			status = "disabled";
405*06874015SDavid Virag		};
406*06874015SDavid Virag
407*06874015SDavid Virag		i2c_7: i2c@11cd0000 {
408*06874015SDavid Virag			compatible = "samsung,s3c2440-i2c";
409*06874015SDavid Virag			reg = <0x11cd0000 0x100>;
410*06874015SDavid Virag			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
411*06874015SDavid Virag			#address-cells = <1>;
412*06874015SDavid Virag			#size-cells = <0>;
413*06874015SDavid Virag			pinctrl-names = "default";
414*06874015SDavid Virag			pinctrl-0 = <&i2c7_bus>;
415*06874015SDavid Virag			clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
416*06874015SDavid Virag			clock-names = "i2c";
417*06874015SDavid Virag			status = "disabled";
418*06874015SDavid Virag		};
419*06874015SDavid Virag	};
420*06874015SDavid Virag};
421*06874015SDavid Virag
422*06874015SDavid Virag#include "exynos7885-pinctrl.dtsi"
423*06874015SDavid Virag#include "arm/exynos-syscon-restart.dtsi"
424