1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos7870 SoC device tree source 4 * 5 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 6 * Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org> 7 */ 8 9#include <dt-bindings/clock/samsung,exynos7870-cmu.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7870"; 14 #address-cells = <2>; 15 #size-cells = <1>; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 pinctrl0 = &pinctrl_alive; 21 pinctrl1 = &pinctrl_dispaud; 22 pinctrl2 = &pinctrl_ese; 23 pinctrl3 = &pinctrl_fsys; 24 pinctrl4 = &pinctrl_mif; 25 pinctrl5 = &pinctrl_nfc; 26 pinctrl6 = &pinctrl_top; 27 pinctrl7 = &pinctrl_touch; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu-map { 35 cluster0 { 36 core0 { 37 cpu = <&cpu0>; 38 }; 39 core1 { 40 cpu = <&cpu1>; 41 }; 42 core2 { 43 cpu = <&cpu2>; 44 }; 45 core3 { 46 cpu = <&cpu3>; 47 }; 48 }; 49 50 cluster1 { 51 core0 { 52 cpu = <&cpu4>; 53 }; 54 core1 { 55 cpu = <&cpu5>; 56 }; 57 core2 { 58 cpu = <&cpu6>; 59 }; 60 core3 { 61 cpu = <&cpu7>; 62 }; 63 }; 64 }; 65 66 cpu0: cpu@0 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0>; 70 enable-method = "psci"; 71 }; 72 73 cpu1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x1>; 77 enable-method = "psci"; 78 }; 79 80 cpu2: cpu@2 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x2>; 84 enable-method = "psci"; 85 }; 86 87 cpu3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x3>; 91 enable-method = "psci"; 92 }; 93 94 cpu4: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x100>; 98 enable-method = "psci"; 99 }; 100 101 cpu5: cpu@101 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x101>; 105 enable-method = "psci"; 106 }; 107 108 cpu6: cpu@102 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x102>; 112 enable-method = "psci"; 113 }; 114 115 cpu7: cpu@103 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x103>; 119 enable-method = "psci"; 120 }; 121 }; 122 123 oscclk: oscclk { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 }; 127 128 psci { 129 compatible = "arm,psci"; 130 method = "smc"; 131 cpu_suspend = <0xc4000001>; 132 cpu_off = <0x84000002>; 133 cpu_on = <0xc4000003>; 134 }; 135 136 soc: soc@0 { 137 compatible = "simple-bus"; 138 ranges = <0x0 0x0 0x0 0x20000000>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 142 chipid@10100000 { 143 compatible = "samsung,exynos7870-chipid", 144 "samsung,exynos4210-chipid"; 145 reg = <0x10100000 0x100>; 146 }; 147 148 cmu_peri: clock-controller@101f0000 { 149 compatible = "samsung,exynos7870-cmu-peri"; 150 reg = <0x101f0000 0x1000>; 151 #clock-cells = <1>; 152 153 clock-names = "oscclk", "bus", "spi0", "spi1", "spi2", 154 "spi3", "spi4", "uart0", "uart1", "uart2"; 155 clocks = <&oscclk>, 156 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>, 157 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>, 158 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>, 159 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>, 160 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>, 161 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>, 162 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>, 163 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>, 164 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>; 165 }; 166 167 cmu_mif: clock-controller@10460000 { 168 compatible = "samsung,exynos7870-cmu-mif"; 169 reg = <0x10460000 0x1000>; 170 #clock-cells = <1>; 171 172 clock-names = "oscclk"; 173 clocks = <&oscclk>; 174 }; 175 176 pmu_system_controller: system-controller@10480000 { 177 compatible = "samsung,exynos7870-pmu", 178 "samsung,exynos7-pmu", "syscon"; 179 reg = <0x10480000 0x10000>; 180 181 reboot-mode { 182 compatible = "syscon-reboot-mode"; 183 offset = <0x080c>; 184 mode-bootloader = <0x1234567d>; 185 mode-download = <0x12345671>; 186 mode-recovery = <0x12345674>; 187 }; 188 }; 189 190 gic: interrupt-controller@104e1000 { 191 compatible = "arm,cortex-a15-gic"; 192 reg = <0x104e1000 0x1000>, 193 <0x104e2000 0x1000>, 194 <0x104e4000 0x2000>, 195 <0x104e6000 0x2000>; 196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 197 IRQ_TYPE_LEVEL_HIGH)>; 198 interrupt-controller; 199 #address-cells = <0>; 200 #interrupt-cells = <3>; 201 }; 202 203 hsi2c0: i2c@10510000 { 204 compatible = "samsung,exynos7870-hsi2c", 205 "samsung,exynos7-hsi2c"; 206 reg = <0x10510000 0x2000>; 207 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 208 209 pinctrl-names = "default"; 210 pinctrl-0 = <&hsi2c0_bus>; 211 212 clock-names = "hsi2c"; 213 clocks = <&cmu_mif CLK_GOUT_MIF_HSI2C_IPCLK>; 214 215 status = "disabled"; 216 }; 217 218 pinctrl_mif: pinctrl@10530000 { 219 compatible = "samsung,exynos7870-pinctrl"; 220 reg = <0x10530000 0x1000>; 221 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 gpu: gpu@11400000 { 225 compatible = "samsung,exynos7870-mali", "arm,mali-t830"; 226 reg = <0x11400000 0x5000>; 227 interrupt-names = "job", "mmu", "gpu"; 228 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 231 232 clock-names = "core", "bus"; 233 clocks = <&cmu_g3d CLK_GOUT_G3D_CLK>, 234 <&cmu_g3d CLK_GOUT_G3D_ASYNCS_D0_CLK>; 235 236 status = "disabled"; 237 }; 238 239 cmu_g3d: clock-controller@11460000 { 240 compatible = "samsung,exynos7870-cmu-g3d"; 241 reg = <0x11460000 0x1000>; 242 #clock-cells = <1>; 243 244 clock-names = "oscclk", "switch"; 245 clocks = <&oscclk>, 246 <&cmu_mif CLK_GOUT_MIF_CMU_G3D_SWITCH>; 247 }; 248 249 cmu_mfcmscl: clock-controller@12cb0000 { 250 compatible = "samsung,exynos7870-cmu-mfcmscl"; 251 reg = <0x12cb0000 0x1000>; 252 #clock-cells = <1>; 253 254 clock-names = "oscclk", "mfc", "mscl"; 255 clocks = <&oscclk>, 256 <&cmu_mif CLK_GOUT_MIF_CMU_MFCMSCL_MFC>, 257 <&cmu_mif CLK_GOUT_MIF_CMU_MFCMSCL_MSCL>; 258 }; 259 260 mmc0: mmc@13540000 { 261 compatible = "samsung,exynos7870-dw-mshc-smu"; 262 reg = <0x13540000 0x2000>; 263 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 264 265 clock-names = "biu", "ciu"; 266 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC0_ACLK>, 267 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC0>; 268 269 status = "disabled"; 270 }; 271 272 mmc1: mmc@13550000 { 273 compatible = "samsung,exynos7870-dw-mshc-smu"; 274 reg = <0x13550000 0x2000>; 275 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 276 277 clock-names = "biu", "ciu"; 278 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC1_ACLK>, 279 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC1>; 280 281 status = "disabled"; 282 }; 283 284 mmc2: mmc@13560000 { 285 compatible = "samsung,exynos7870-dw-mshc-smu"; 286 reg = <0x13560000 0x2000>; 287 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 288 289 clock-names = "biu", "ciu"; 290 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC2_ACLK>, 291 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC2>; 292 293 status = "disabled"; 294 }; 295 296 usbdrd_phy: phy@135c0000 { 297 compatible = "samsung,exynos7870-usbdrd-phy"; 298 reg = <0x135c0000 0x100>; 299 #phy-cells = <1>; 300 301 clock-names = "phy", "ref"; 302 clocks = <&cmu_fsys CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER>, 303 <&cmu_fsys CLK_GOUT_FSYS_MUX_USB_PLL>; 304 305 samsung,pmu-syscon = <&pmu_system_controller>; 306 }; 307 308 usbdrd: usb@13600000 { 309 compatible = "samsung,exynos7870-dwusb3"; 310 ranges = <0x0 0x13600000 0x10000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 314 clock-names = "bus_early", "ref", "ctrl"; 315 clocks = <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD>, 316 <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK>, 317 <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL>; 318 319 status = "disabled"; 320 321 usb@0 { 322 compatible = "snps,dwc3"; 323 reg = <0x0 0x10000>; 324 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 325 326 phy-names = "usb2-phy"; 327 phys = <&usbdrd_phy 0>; 328 329 usb-role-switch; 330 }; 331 }; 332 333 cmu_fsys: clock-controller@13730000 { 334 compatible = "samsung,exynos7870-cmu-fsys"; 335 reg = <0x13730000 0x1000>; 336 #clock-cells = <1>; 337 338 clock-names = "oscclk", "bus", "usb20drd"; 339 clocks = <&oscclk>, 340 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_BUS>, 341 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK>; 342 }; 343 344 pinctrl_fsys: pinctrl@13750000 { 345 compatible = "samsung,exynos7870-pinctrl"; 346 reg = <0x13750000 0x1000>; 347 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 348 }; 349 350 serial0: serial@13800000 { 351 compatible = "samsung,exynos7870-uart", 352 "samsung,exynos8895-uart"; 353 reg = <0x13800000 0x100>; 354 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 355 356 pinctrl-names = "default"; 357 pinctrl-0 = <&uart0_bus>; 358 359 clock-names = "uart", "clk_uart_baud0"; 360 clocks = <&cmu_peri CLK_GOUT_PERI_UART0_PCLK>, 361 <&cmu_peri CLK_GOUT_PERI_UART0_EXT_UCLK>; 362 363 samsung,uart-fifosize = <16>; 364 365 status = "disabled"; 366 }; 367 368 serial1: serial@13810000 { 369 compatible = "samsung,exynos7870-uart", 370 "samsung,exynos8895-uart"; 371 reg = <0x13810000 0x100>; 372 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 373 374 pinctrl-names = "default"; 375 pinctrl-0 = <&uart1_bus>; 376 377 clock-names = "uart", "clk_uart_baud0"; 378 clocks = <&cmu_peri CLK_GOUT_PERI_UART1_PCLK>, 379 <&cmu_peri CLK_GOUT_PERI_UART1_EXT_UCLK>; 380 381 samsung,uart-fifosize = <256>; 382 383 status = "disabled"; 384 }; 385 386 serial2: serial@13820000 { 387 compatible = "samsung,exynos7870-uart", 388 "samsung,exynos8895-uart"; 389 reg = <0x13820000 0x100>; 390 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 391 392 pinctrl-names = "default"; 393 pinctrl-0 = <&uart2_bus>; 394 395 clock-names = "uart", "clk_uart_baud0"; 396 clocks = <&cmu_peri CLK_GOUT_PERI_UART2_PCLK>, 397 <&cmu_peri CLK_GOUT_PERI_UART2_EXT_UCLK>; 398 399 samsung,uart-fifosize = <256>; 400 401 status = "disabled"; 402 }; 403 404 i2c0: i2c@13830000 { 405 compatible = "samsung,exynos7870-i2c", 406 "samsung,s3c2440-i2c"; 407 reg = <0x13830000 0x100>; 408 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 409 410 pinctrl-names = "default"; 411 pinctrl-0 = <&i2c0_bus>; 412 413 clock-names = "i2c"; 414 clocks = <&cmu_peri CLK_GOUT_PERI_I2C0_PCLK>; 415 416 status = "disabled"; 417 }; 418 419 i2c1: i2c@13840000 { 420 compatible = "samsung,exynos7870-i2c", 421 "samsung,s3c2440-i2c"; 422 reg = <0x13840000 0x100>; 423 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 424 425 pinctrl-names = "default"; 426 pinctrl-0 = <&i2c1_bus>; 427 428 clock-names = "i2c"; 429 clocks = <&cmu_peri CLK_GOUT_PERI_I2C1_PCLK>; 430 431 status = "disabled"; 432 }; 433 434 i2c2: i2c@13850000 { 435 compatible = "samsung,exynos7870-i2c", 436 "samsung,s3c2440-i2c"; 437 reg = <0x13850000 0x100>; 438 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; 439 440 pinctrl-names = "default"; 441 pinctrl-0 = <&i2c2_bus>; 442 443 clock-names = "i2c"; 444 clocks = <&cmu_peri CLK_GOUT_PERI_I2C2_PCLK>; 445 446 status = "disabled"; 447 }; 448 449 i2c3: i2c@13860000 { 450 compatible = "samsung,exynos7870-i2c", 451 "samsung,s3c2440-i2c"; 452 reg = <0x13860000 0x100>; 453 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; 454 455 pinctrl-names = "default"; 456 pinctrl-0 = <&i2c3_bus>; 457 458 clock-names = "i2c"; 459 clocks = <&cmu_peri CLK_GOUT_PERI_I2C3_PCLK>; 460 461 status = "disabled"; 462 }; 463 464 i2c4: i2c@13870000 { 465 compatible = "samsung,exynos7870-i2c", 466 "samsung,s3c2440-i2c"; 467 reg = <0x13870000 0x100>; 468 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; 469 470 pinctrl-names = "default"; 471 pinctrl-0 = <&i2c4_bus>; 472 473 clock-names = "i2c"; 474 clocks = <&cmu_peri CLK_GOUT_PERI_I2C4_PCLK>; 475 476 status = "disabled"; 477 }; 478 479 i2c5: i2c@13880000 { 480 compatible = "samsung,exynos7870-i2c", 481 "samsung,s3c2440-i2c"; 482 reg = <0x13880000 0x100>; 483 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 484 485 pinctrl-names = "default"; 486 pinctrl-0 = <&i2c5_bus>; 487 488 clock-names = "i2c"; 489 clocks = <&cmu_peri CLK_GOUT_PERI_I2C5_PCLK>; 490 491 status = "disabled"; 492 }; 493 494 i2c6: i2c@13890000 { 495 compatible = "samsung,exynos7870-i2c", 496 "samsung,s3c2440-i2c"; 497 reg = <0x13890000 0x100>; 498 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 499 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c6_bus>; 502 503 clock-names = "i2c"; 504 clocks = <&cmu_peri CLK_GOUT_PERI_I2C6_PCLK>; 505 506 status = "disabled"; 507 }; 508 509 hsi2c1: i2c@138a0000 { 510 compatible = "samsung,exynos7870-hsi2c", 511 "samsung,exynos7-hsi2c"; 512 reg = <0x138a0000 0x1000>; 513 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 514 515 pinctrl-names = "default"; 516 pinctrl-0 = <&hsi2c1_bus>; 517 518 clock-names = "hsi2c"; 519 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C1_IPCLK>; 520 521 status = "disabled"; 522 }; 523 524 hsi2c2: i2c@138b0000 { 525 compatible = "samsung,exynos7870-hsi2c", 526 "samsung,exynos7-hsi2c"; 527 reg = <0x138b0000 0x1000>; 528 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>; 529 530 pinctrl-names = "default"; 531 pinctrl-0 = <&hsi2c2_bus>; 532 533 clock-names = "hsi2c"; 534 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C2_IPCLK>; 535 536 status = "disabled"; 537 }; 538 539 hsi2c3: i2c@138c0000 { 540 compatible = "samsung,exynos7870-hsi2c", 541 "samsung,exynos7-hsi2c"; 542 reg = <0x138c0000 0x1000>; 543 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 544 545 pinctrl-names = "default"; 546 pinctrl-0 = <&hsi2c3_bus>; 547 548 clock-names = "hsi2c"; 549 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C3_IPCLK>; 550 551 status = "disabled"; 552 }; 553 554 i2c7: i2c@138d0000 { 555 compatible = "samsung,exynos7870-i2c", 556 "samsung,s3c2440-i2c"; 557 reg = <0x138d0000 0x100>; 558 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 559 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c7_bus>; 562 563 clock-names = "i2c"; 564 clocks = <&cmu_peri CLK_GOUT_PERI_I2C7_PCLK>; 565 566 status = "disabled"; 567 }; 568 569 i2c8: i2c@138e0000 { 570 compatible = "samsung,exynos7870-i2c", 571 "samsung,s3c2440-i2c"; 572 reg = <0x138e0000 0x100>; 573 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 574 575 pinctrl-names = "default"; 576 pinctrl-0 = <&i2c8_bus>; 577 578 clock-names = "i2c"; 579 clocks = <&cmu_peri CLK_GOUT_PERI_I2C8_PCLK>; 580 581 status = "disabled"; 582 }; 583 584 hsi2c4: i2c@138f0000 { 585 compatible = "samsung,exynos7870-hsi2c", 586 "samsung,exynos7-hsi2c"; 587 reg = <0x138f0000 0x1000>; 588 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 589 590 pinctrl-names = "default"; 591 pinctrl-0 = <&hsi2c4_bus>; 592 593 clock-names = "hsi2c"; 594 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C4_IPCLK>; 595 596 status = "disabled"; 597 }; 598 599 hsi2c5: i2c@13950000 { 600 compatible = "samsung,exynos7870-hsi2c", 601 "samsung,exynos7-hsi2c"; 602 reg = <0x13950000 0x1000>; 603 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 604 605 pinctrl-names = "default"; 606 pinctrl-0 = <&hsi2c5_bus>; 607 608 clock-names = "hsi2c"; 609 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C5_IPCLK>; 610 611 status = "disabled"; 612 }; 613 614 hsi2c6: i2c@13960000 { 615 compatible = "samsung,exynos7870-hsi2c", 616 "samsung,exynos7-hsi2c"; 617 reg = <0x13960000 0x1000>; 618 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 619 620 pinctrl-names = "default"; 621 pinctrl-0 = <&hsi2c6_bus>; 622 623 clock-names = "hsi2c"; 624 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C6_IPCLK>; 625 626 status = "disabled"; 627 }; 628 629 pinctrl_top: pinctrl@139b0000 { 630 compatible = "samsung,exynos7870-pinctrl"; 631 reg = <0x139b0000 0x1000>; 632 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 633 }; 634 635 pinctrl_nfc: pinctrl@139c0000 { 636 compatible = "samsung,exynos7870-pinctrl"; 637 reg = <0x139c0000 0x1000>; 638 interrupts = <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 639 }; 640 641 pinctrl_touch: pinctrl@139d0000 { 642 compatible = "samsung,exynos7870-pinctrl"; 643 reg = <0x139d0000 0x1000>; 644 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 645 }; 646 647 pinctrl_ese: pinctrl@139e0000 { 648 compatible = "samsung,exynos7870-pinctrl"; 649 reg = <0x139e0000 0x1000>; 650 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 651 }; 652 653 pinctrl_alive: pinctrl@139f0000 { 654 compatible = "samsung,exynos7870-pinctrl"; 655 reg = <0x139f0000 0x1000>; 656 657 wakeup-interrupt-controller { 658 compatible = "samsung,exynos7870-wakeup-eint", 659 "samsung,exynos7-wakeup-eint"; 660 interrupt-parent = <&gic>; 661 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 662 }; 663 }; 664 665 cmu_isp: clock-controller@144d0000 { 666 compatible = "samsung,exynos7870-cmu-isp"; 667 reg = <0x144d0000 0x1000>; 668 #clock-cells = <1>; 669 670 clock-names = "oscclk", "cam", "isp", "vra"; 671 clocks = <&oscclk>, 672 <&cmu_mif CLK_GOUT_MIF_CMU_ISP_CAM>, 673 <&cmu_mif CLK_GOUT_MIF_CMU_ISP_ISP>, 674 <&cmu_mif CLK_GOUT_MIF_CMU_ISP_VRA>; 675 }; 676 677 pinctrl_dispaud: pinctrl@148c0000 { 678 compatible = "samsung,exynos7870-pinctrl"; 679 reg = <0x148c0000 0x1000>; 680 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 681 }; 682 683 cmu_dispaud: clock-controller@148d0000 { 684 compatible = "samsung,exynos7870-cmu-dispaud"; 685 reg = <0x148d0000 0x1000>; 686 #clock-cells = <1>; 687 688 clock-names = "oscclk", "bus", "decon_eclk", "decon_vclk"; 689 clocks = <&oscclk>, 690 <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_BUS>, 691 <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK>, 692 <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK>; 693 }; 694 }; 695 696 timer { 697 compatible = "arm,armv8-timer"; 698 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 699 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 700 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 701 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 702 703 /* 704 * Non-updatable, broken stock Samsung bootloader does not 705 * configure CNTFRQ_EL0 706 */ 707 clock-frequency = <26000000>; 708 }; 709}; 710 711#include "exynos7870-pinctrl.dtsi" 712#include "arm/samsung/exynos-syscon-restart.dtsi" 713