1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos7 SoC device tree source 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 */ 8 9#include <dt-bindings/clock/exynos7-clk.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 pinctrl0 = &pinctrl_alive; 20 pinctrl1 = &pinctrl_bus0; 21 pinctrl2 = &pinctrl_nfc; 22 pinctrl3 = &pinctrl_touch; 23 pinctrl4 = &pinctrl_ff; 24 pinctrl5 = &pinctrl_ese; 25 pinctrl6 = &pinctrl_fsys0; 26 pinctrl7 = &pinctrl_fsys1; 27 pinctrl8 = &pinctrl_bus1; 28 tmuctrl0 = &tmuctrl_0; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a57-pmu"; 33 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, 38 <&cpu_atlas2>, <&cpu_atlas3>; 39 }; 40 41 fin_pll: clock { 42 /* XXTI */ 43 compatible = "fixed-clock"; 44 clock-output-names = "fin_pll"; 45 #clock-cells = <0>; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu_atlas0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a57"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 }; 58 59 cpu_atlas1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a57"; 62 reg = <0x1>; 63 enable-method = "psci"; 64 }; 65 66 cpu_atlas2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a57"; 69 reg = <0x2>; 70 enable-method = "psci"; 71 }; 72 73 cpu_atlas3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a57"; 76 reg = <0x3>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 psci { 82 compatible = "arm,psci"; 83 method = "smc"; 84 cpu_off = <0x84000002>; 85 cpu_on = <0xC4000003>; 86 }; 87 88 soc: soc@0 { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0 0 0 0x18000000>; 93 94 chipid@10000000 { 95 compatible = "samsung,exynos4210-chipid"; 96 reg = <0x10000000 0x100>; 97 }; 98 99 gic: interrupt-controller@11001000 { 100 compatible = "arm,gic-400"; 101 #interrupt-cells = <3>; 102 #address-cells = <0>; 103 interrupt-controller; 104 reg = <0x11001000 0x1000>, 105 <0x11002000 0x1000>, 106 <0x11004000 0x2000>, 107 <0x11006000 0x2000>; 108 }; 109 110 pdma0: pdma@10e10000 { 111 compatible = "arm,pl330", "arm,primecell"; 112 reg = <0x10E10000 0x1000>; 113 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&clock_fsys0 ACLK_PDMA0>; 115 clock-names = "apb_pclk"; 116 #dma-cells = <1>; 117 #dma-channels = <8>; 118 #dma-requests = <32>; 119 }; 120 121 pdma1: pdma@10eb0000 { 122 compatible = "arm,pl330", "arm,primecell"; 123 reg = <0x10EB0000 0x1000>; 124 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&clock_fsys0 ACLK_PDMA1>; 126 clock-names = "apb_pclk"; 127 #dma-cells = <1>; 128 #dma-channels = <8>; 129 #dma-requests = <32>; 130 }; 131 132 clock_topc: clock-controller@10570000 { 133 compatible = "samsung,exynos7-clock-topc"; 134 reg = <0x10570000 0x10000>; 135 #clock-cells = <1>; 136 }; 137 138 clock_top0: clock-controller@105d0000 { 139 compatible = "samsung,exynos7-clock-top0"; 140 reg = <0x105d0000 0xb000>; 141 #clock-cells = <1>; 142 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 143 <&clock_topc DOUT_SCLK_BUS1_PLL>, 144 <&clock_topc DOUT_SCLK_CC_PLL>, 145 <&clock_topc DOUT_SCLK_MFC_PLL>; 146 clock-names = "fin_pll", "dout_sclk_bus0_pll", 147 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 148 "dout_sclk_mfc_pll"; 149 }; 150 151 clock_top1: clock-controller@105e0000 { 152 compatible = "samsung,exynos7-clock-top1"; 153 reg = <0x105e0000 0xb000>; 154 #clock-cells = <1>; 155 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 156 <&clock_topc DOUT_SCLK_BUS1_PLL>, 157 <&clock_topc DOUT_SCLK_CC_PLL>, 158 <&clock_topc DOUT_SCLK_MFC_PLL>; 159 clock-names = "fin_pll", "dout_sclk_bus0_pll", 160 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 161 "dout_sclk_mfc_pll"; 162 }; 163 164 clock_ccore: clock-controller@105b0000 { 165 compatible = "samsung,exynos7-clock-ccore"; 166 reg = <0x105b0000 0xd00>; 167 #clock-cells = <1>; 168 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 169 clock-names = "fin_pll", "dout_aclk_ccore_133"; 170 }; 171 172 clock_peric0: clock-controller@13610000 { 173 compatible = "samsung,exynos7-clock-peric0"; 174 reg = <0x13610000 0xd00>; 175 #clock-cells = <1>; 176 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 177 <&clock_top0 CLK_SCLK_UART0>; 178 clock-names = "fin_pll", "dout_aclk_peric0_66", 179 "sclk_uart0"; 180 }; 181 182 clock_peric1: clock-controller@14c80000 { 183 compatible = "samsung,exynos7-clock-peric1"; 184 reg = <0x14c80000 0xd00>; 185 #clock-cells = <1>; 186 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 187 <&clock_top0 CLK_SCLK_UART1>, 188 <&clock_top0 CLK_SCLK_UART2>, 189 <&clock_top0 CLK_SCLK_UART3>; 190 clock-names = "fin_pll", "dout_aclk_peric1_66", 191 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 192 }; 193 194 clock_peris: clock-controller@10040000 { 195 compatible = "samsung,exynos7-clock-peris"; 196 reg = <0x10040000 0xd00>; 197 #clock-cells = <1>; 198 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 199 clock-names = "fin_pll", "dout_aclk_peris_66"; 200 }; 201 202 clock_fsys0: clock-controller@10e90000 { 203 compatible = "samsung,exynos7-clock-fsys0"; 204 reg = <0x10e90000 0xd00>; 205 #clock-cells = <1>; 206 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 207 <&clock_top1 DOUT_SCLK_MMC2>; 208 clock-names = "fin_pll", "dout_aclk_fsys0_200", 209 "dout_sclk_mmc2"; 210 }; 211 212 clock_fsys1: clock-controller@156e0000 { 213 compatible = "samsung,exynos7-clock-fsys1"; 214 reg = <0x156e0000 0xd00>; 215 #clock-cells = <1>; 216 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 217 <&clock_top1 DOUT_SCLK_MMC0>, 218 <&clock_top1 DOUT_SCLK_MMC1>, 219 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>, 220 <&clock_top1 DOUT_SCLK_PHY_FSYS1>, 221 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>; 222 clock-names = "fin_pll", "dout_aclk_fsys1_200", 223 "dout_sclk_mmc0", "dout_sclk_mmc1", 224 "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1", 225 "dout_sclk_phy_fsys1_26m"; 226 }; 227 228 serial_0: serial@13630000 { 229 compatible = "samsung,exynos4210-uart"; 230 reg = <0x13630000 0x100>; 231 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&clock_peric0 PCLK_UART0>, 233 <&clock_peric0 SCLK_UART0>; 234 clock-names = "uart", "clk_uart_baud0"; 235 status = "disabled"; 236 }; 237 238 serial_1: serial@14c20000 { 239 compatible = "samsung,exynos4210-uart"; 240 reg = <0x14c20000 0x100>; 241 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&clock_peric1 PCLK_UART1>, 243 <&clock_peric1 SCLK_UART1>; 244 clock-names = "uart", "clk_uart_baud0"; 245 status = "disabled"; 246 }; 247 248 serial_2: serial@14c30000 { 249 compatible = "samsung,exynos4210-uart"; 250 reg = <0x14c30000 0x100>; 251 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&clock_peric1 PCLK_UART2>, 253 <&clock_peric1 SCLK_UART2>; 254 clock-names = "uart", "clk_uart_baud0"; 255 status = "disabled"; 256 }; 257 258 serial_3: serial@14c40000 { 259 compatible = "samsung,exynos4210-uart"; 260 reg = <0x14c40000 0x100>; 261 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clock_peric1 PCLK_UART3>, 263 <&clock_peric1 SCLK_UART3>; 264 clock-names = "uart", "clk_uart_baud0"; 265 status = "disabled"; 266 }; 267 268 pinctrl_alive: pinctrl@10580000 { 269 compatible = "samsung,exynos7-pinctrl"; 270 reg = <0x10580000 0x1000>; 271 272 wakeup-interrupt-controller { 273 compatible = "samsung,exynos7-wakeup-eint"; 274 interrupt-parent = <&gic>; 275 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 }; 278 279 pinctrl_bus0: pinctrl@13470000 { 280 compatible = "samsung,exynos7-pinctrl"; 281 reg = <0x13470000 0x1000>; 282 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 283 }; 284 285 pinctrl_nfc: pinctrl@14cd0000 { 286 compatible = "samsung,exynos7-pinctrl"; 287 reg = <0x14cd0000 0x1000>; 288 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 289 }; 290 291 pinctrl_touch: pinctrl@14ce0000 { 292 compatible = "samsung,exynos7-pinctrl"; 293 reg = <0x14ce0000 0x1000>; 294 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 295 }; 296 297 pinctrl_ff: pinctrl@14c90000 { 298 compatible = "samsung,exynos7-pinctrl"; 299 reg = <0x14c90000 0x1000>; 300 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 301 }; 302 303 pinctrl_ese: pinctrl@14ca0000 { 304 compatible = "samsung,exynos7-pinctrl"; 305 reg = <0x14ca0000 0x1000>; 306 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 307 }; 308 309 pinctrl_fsys0: pinctrl@10e60000 { 310 compatible = "samsung,exynos7-pinctrl"; 311 reg = <0x10e60000 0x1000>; 312 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 pinctrl_fsys1: pinctrl@15690000 { 316 compatible = "samsung,exynos7-pinctrl"; 317 reg = <0x15690000 0x1000>; 318 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 319 }; 320 321 pinctrl_bus1: pinctrl@14870000 { 322 compatible = "samsung,exynos7-pinctrl"; 323 reg = <0x14870000 0x1000>; 324 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 325 }; 326 327 hsi2c_0: hsi2c@13640000 { 328 compatible = "samsung,exynos7-hsi2c"; 329 reg = <0x13640000 0x1000>; 330 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&hs_i2c0_bus>; 335 clocks = <&clock_peric0 PCLK_HSI2C0>; 336 clock-names = "hsi2c"; 337 status = "disabled"; 338 }; 339 340 hsi2c_1: hsi2c@13650000 { 341 compatible = "samsung,exynos7-hsi2c"; 342 reg = <0x13650000 0x1000>; 343 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&hs_i2c1_bus>; 348 clocks = <&clock_peric0 PCLK_HSI2C1>; 349 clock-names = "hsi2c"; 350 status = "disabled"; 351 }; 352 353 hsi2c_2: hsi2c@14e60000 { 354 compatible = "samsung,exynos7-hsi2c"; 355 reg = <0x14e60000 0x1000>; 356 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&hs_i2c2_bus>; 361 clocks = <&clock_peric1 PCLK_HSI2C2>; 362 clock-names = "hsi2c"; 363 status = "disabled"; 364 }; 365 366 hsi2c_3: hsi2c@14e70000 { 367 compatible = "samsung,exynos7-hsi2c"; 368 reg = <0x14e70000 0x1000>; 369 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&hs_i2c3_bus>; 374 clocks = <&clock_peric1 PCLK_HSI2C3>; 375 clock-names = "hsi2c"; 376 status = "disabled"; 377 }; 378 379 hsi2c_4: hsi2c@13660000 { 380 compatible = "samsung,exynos7-hsi2c"; 381 reg = <0x13660000 0x1000>; 382 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&hs_i2c4_bus>; 387 clocks = <&clock_peric0 PCLK_HSI2C4>; 388 clock-names = "hsi2c"; 389 status = "disabled"; 390 }; 391 392 hsi2c_5: hsi2c@13670000 { 393 compatible = "samsung,exynos7-hsi2c"; 394 reg = <0x13670000 0x1000>; 395 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&hs_i2c5_bus>; 400 clocks = <&clock_peric0 PCLK_HSI2C5>; 401 clock-names = "hsi2c"; 402 status = "disabled"; 403 }; 404 405 hsi2c_6: hsi2c@14e00000 { 406 compatible = "samsung,exynos7-hsi2c"; 407 reg = <0x14e00000 0x1000>; 408 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&hs_i2c6_bus>; 413 clocks = <&clock_peric1 PCLK_HSI2C6>; 414 clock-names = "hsi2c"; 415 status = "disabled"; 416 }; 417 418 hsi2c_7: hsi2c@13e10000 { 419 compatible = "samsung,exynos7-hsi2c"; 420 reg = <0x13e10000 0x1000>; 421 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&hs_i2c7_bus>; 426 clocks = <&clock_peric1 PCLK_HSI2C7>; 427 clock-names = "hsi2c"; 428 status = "disabled"; 429 }; 430 431 hsi2c_8: hsi2c@14e20000 { 432 compatible = "samsung,exynos7-hsi2c"; 433 reg = <0x14e20000 0x1000>; 434 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&hs_i2c8_bus>; 439 clocks = <&clock_peric1 PCLK_HSI2C8>; 440 clock-names = "hsi2c"; 441 status = "disabled"; 442 }; 443 444 hsi2c_9: hsi2c@13680000 { 445 compatible = "samsung,exynos7-hsi2c"; 446 reg = <0x13680000 0x1000>; 447 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&hs_i2c9_bus>; 452 clocks = <&clock_peric0 PCLK_HSI2C9>; 453 clock-names = "hsi2c"; 454 status = "disabled"; 455 }; 456 457 hsi2c_10: hsi2c@13690000 { 458 compatible = "samsung,exynos7-hsi2c"; 459 reg = <0x13690000 0x1000>; 460 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&hs_i2c10_bus>; 465 clocks = <&clock_peric0 PCLK_HSI2C10>; 466 clock-names = "hsi2c"; 467 status = "disabled"; 468 }; 469 470 hsi2c_11: hsi2c@136a0000 { 471 compatible = "samsung,exynos7-hsi2c"; 472 reg = <0x136a0000 0x1000>; 473 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&hs_i2c11_bus>; 478 clocks = <&clock_peric0 PCLK_HSI2C11>; 479 clock-names = "hsi2c"; 480 status = "disabled"; 481 }; 482 483 pmu_system_controller: system-controller@105c0000 { 484 compatible = "samsung,exynos7-pmu", "syscon"; 485 reg = <0x105c0000 0x5000>; 486 }; 487 488 rtc: rtc@10590000 { 489 compatible = "samsung,s3c6410-rtc"; 490 reg = <0x10590000 0x100>; 491 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&clock_ccore PCLK_RTC>; 494 clock-names = "rtc"; 495 status = "disabled"; 496 }; 497 498 watchdog: watchdog@101d0000 { 499 compatible = "samsung,exynos7-wdt"; 500 reg = <0x101d0000 0x100>; 501 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clock_peris PCLK_WDT>; 503 clock-names = "watchdog"; 504 samsung,syscon-phandle = <&pmu_system_controller>; 505 status = "disabled"; 506 }; 507 508 gpu: gpu@14ac0000 { 509 compatible = "samsung,exynos5433-mali", "arm,mali-t760"; 510 reg = <0x14ac0000 0x5000>; 511 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 514 interrupt-names = "job", "mmu", "gpu"; 515 status = "disabled"; 516 /* TODO: operating points for DVFS, cooling device */ 517 }; 518 519 mmc_0: mmc@15740000 { 520 compatible = "samsung,exynos7-dw-mshc-smu"; 521 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0x15740000 0x2000>; 525 clocks = <&clock_fsys1 ACLK_MMC0>, 526 <&clock_top1 CLK_SCLK_MMC0>; 527 clock-names = "biu", "ciu"; 528 fifo-depth = <0x40>; 529 status = "disabled"; 530 }; 531 532 mmc_1: mmc@15750000 { 533 compatible = "samsung,exynos7-dw-mshc"; 534 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 reg = <0x15750000 0x2000>; 538 clocks = <&clock_fsys1 ACLK_MMC1>, 539 <&clock_top1 CLK_SCLK_MMC1>; 540 clock-names = "biu", "ciu"; 541 fifo-depth = <0x40>; 542 status = "disabled"; 543 }; 544 545 mmc_2: mmc@15560000 { 546 compatible = "samsung,exynos7-dw-mshc-smu"; 547 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 reg = <0x15560000 0x2000>; 551 clocks = <&clock_fsys0 ACLK_MMC2>, 552 <&clock_top1 CLK_SCLK_MMC2>; 553 clock-names = "biu", "ciu"; 554 fifo-depth = <0x40>; 555 status = "disabled"; 556 }; 557 558 adc: adc@13620000 { 559 compatible = "samsung,exynos7-adc"; 560 reg = <0x13620000 0x100>; 561 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&clock_peric0 PCLK_ADCIF>; 563 clock-names = "adc"; 564 #io-channel-cells = <1>; 565 status = "disabled"; 566 }; 567 568 pwm: pwm@136c0000 { 569 compatible = "samsung,exynos4210-pwm"; 570 reg = <0x136c0000 0x100>; 571 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 576 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 577 #pwm-cells = <3>; 578 clocks = <&clock_peric0 PCLK_PWM>; 579 clock-names = "timers"; 580 }; 581 582 tmuctrl_0: tmu@10060000 { 583 compatible = "samsung,exynos7-tmu"; 584 reg = <0x10060000 0x200>; 585 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&clock_peris PCLK_TMU>, 587 <&clock_peris SCLK_TMU>; 588 clock-names = "tmu_apbif", "tmu_sclk"; 589 #thermal-sensor-cells = <0>; 590 }; 591 592 ufs: ufs@15570000 { 593 compatible = "samsung,exynos7-ufs"; 594 reg = <0x15570000 0x100>, /* 0: HCI standard */ 595 <0x15570100 0x100>, /* 1: Vendor specificed */ 596 <0x15571000 0x200>, /* 2: UNIPRO */ 597 <0x15572000 0x300>; /* 3: UFS protector */ 598 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 599 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&clock_fsys1 ACLK_UFS20_LINK>, 601 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; 602 clock-names = "core_clk", "sclk_unipro_main"; 603 freq-table-hz = <0 0>, <0 0>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 606 phys = <&ufs_phy>; 607 phy-names = "ufs-phy"; 608 status = "disabled"; 609 }; 610 611 ufs_phy: ufs-phy@15571800 { 612 compatible = "samsung,exynos7-ufs-phy"; 613 reg = <0x15571800 0x240>; 614 reg-names = "phy-pma"; 615 samsung,pmu-syscon = <&pmu_system_controller>; 616 #phy-cells = <0>; 617 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, 618 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, 619 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, 620 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; 621 clock-names = "ref_clk", "rx1_symbol_clk", 622 "rx0_symbol_clk", 623 "tx0_symbol_clk"; 624 }; 625 626 usbdrd_phy: phy@15500000 { 627 compatible = "samsung,exynos7-usbdrd-phy"; 628 reg = <0x15500000 0x100>; 629 clocks = <&clock_fsys0 ACLK_USBDRD300>, 630 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, 631 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, 632 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, 633 <&clock_fsys0 SCLK_USBDRD300_REFCLK>; 634 clock-names = "phy", "ref", "phy_pipe", 635 "phy_utmi", "itp"; 636 samsung,pmu-syscon = <&pmu_system_controller>; 637 #phy-cells = <1>; 638 }; 639 640 usbdrd3 { 641 compatible = "samsung,exynos7-dwusb3"; 642 clocks = <&clock_fsys0 ACLK_USBDRD300>, 643 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, 644 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; 645 clock-names = "usbdrd30", "usbdrd30_susp_clk", 646 "usbdrd30_axius_clk"; 647 #address-cells = <1>; 648 #size-cells = <1>; 649 ranges; 650 651 usb@15400000 { 652 compatible = "snps,dwc3"; 653 reg = <0x15400000 0x10000>; 654 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 655 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 656 phy-names = "usb2-phy", "usb3-phy"; 657 }; 658 }; 659 }; 660 661 thermal-zones { 662 atlas_thermal: cluster0-thermal { 663 polling-delay-passive = <0>; /* milliseconds */ 664 polling-delay = <0>; /* milliseconds */ 665 thermal-sensors = <&tmuctrl_0>; 666 #include "exynos7-trip-points.dtsi" 667 }; 668 }; 669 670 timer { 671 compatible = "arm,armv8-timer"; 672 interrupts = <GIC_PPI 13 673 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 674 <GIC_PPI 14 675 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 676 <GIC_PPI 11 677 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 678 <GIC_PPI 10 679 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 680 }; 681}; 682 683#include "exynos7-pinctrl.dtsi" 684#include "arm/exynos-syscon-restart.dtsi" 685