1/* 2 * SAMSUNG EXYNOS7 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <dt-bindings/clock/exynos7-clk.h> 13 14/ { 15 compatible = "samsung,exynos7"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 pinctrl0 = &pinctrl_alive; 22 pinctrl1 = &pinctrl_bus0; 23 pinctrl2 = &pinctrl_nfc; 24 pinctrl3 = &pinctrl_touch; 25 pinctrl4 = &pinctrl_ff; 26 pinctrl5 = &pinctrl_ese; 27 pinctrl6 = &pinctrl_fsys0; 28 pinctrl7 = &pinctrl_fsys1; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a57", "arm,armv8"; 38 reg = <0x0>; 39 enable-method = "psci"; 40 }; 41 42 cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a57", "arm,armv8"; 45 reg = <0x1>; 46 enable-method = "psci"; 47 }; 48 49 cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a57", "arm,armv8"; 52 reg = <0x2>; 53 enable-method = "psci"; 54 }; 55 56 cpu@3 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a57", "arm,armv8"; 59 reg = <0x3>; 60 enable-method = "psci"; 61 }; 62 }; 63 64 psci { 65 compatible = "arm,psci-0.2"; 66 method = "smc"; 67 }; 68 69 soc: soc { 70 compatible = "simple-bus"; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 ranges = <0 0 0 0x18000000>; 74 75 chipid@10000000 { 76 compatible = "samsung,exynos4210-chipid"; 77 reg = <0x10000000 0x100>; 78 }; 79 80 fin_pll: xxti { 81 compatible = "fixed-clock"; 82 clock-output-names = "fin_pll"; 83 #clock-cells = <0>; 84 }; 85 86 gic: interrupt-controller@11001000 { 87 compatible = "arm,gic-400"; 88 #interrupt-cells = <3>; 89 #address-cells = <0>; 90 interrupt-controller; 91 reg = <0x11001000 0x1000>, 92 <0x11002000 0x1000>, 93 <0x11004000 0x2000>, 94 <0x11006000 0x2000>; 95 }; 96 97 clock_topc: clock-controller@10570000 { 98 compatible = "samsung,exynos7-clock-topc"; 99 reg = <0x10570000 0x10000>; 100 #clock-cells = <1>; 101 }; 102 103 clock_top0: clock-controller@105d0000 { 104 compatible = "samsung,exynos7-clock-top0"; 105 reg = <0x105d0000 0xb000>; 106 #clock-cells = <1>; 107 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 108 <&clock_topc DOUT_SCLK_BUS1_PLL>, 109 <&clock_topc DOUT_SCLK_CC_PLL>, 110 <&clock_topc DOUT_SCLK_MFC_PLL>; 111 clock-names = "fin_pll", "dout_sclk_bus0_pll", 112 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 113 "dout_sclk_mfc_pll"; 114 }; 115 116 clock_top1: clock-controller@105e0000 { 117 compatible = "samsung,exynos7-clock-top1"; 118 reg = <0x105e0000 0xb000>; 119 #clock-cells = <1>; 120 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 121 <&clock_topc DOUT_SCLK_BUS1_PLL>, 122 <&clock_topc DOUT_SCLK_CC_PLL>, 123 <&clock_topc DOUT_SCLK_MFC_PLL>; 124 clock-names = "fin_pll", "dout_sclk_bus0_pll", 125 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 126 "dout_sclk_mfc_pll"; 127 }; 128 129 clock_ccore: clock-controller@105b0000 { 130 compatible = "samsung,exynos7-clock-ccore"; 131 reg = <0x105b0000 0xd00>; 132 #clock-cells = <1>; 133 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 134 clock-names = "fin_pll", "dout_aclk_ccore_133"; 135 }; 136 137 clock_peric0: clock-controller@13610000 { 138 compatible = "samsung,exynos7-clock-peric0"; 139 reg = <0x13610000 0xd00>; 140 #clock-cells = <1>; 141 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 142 <&clock_top0 CLK_SCLK_UART0>; 143 clock-names = "fin_pll", "dout_aclk_peric0_66", 144 "sclk_uart0"; 145 }; 146 147 clock_peric1: clock-controller@14c80000 { 148 compatible = "samsung,exynos7-clock-peric1"; 149 reg = <0x14c80000 0xd00>; 150 #clock-cells = <1>; 151 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 152 <&clock_top0 CLK_SCLK_UART1>, 153 <&clock_top0 CLK_SCLK_UART2>, 154 <&clock_top0 CLK_SCLK_UART3>; 155 clock-names = "fin_pll", "dout_aclk_peric1_66", 156 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 157 }; 158 159 clock_peris: clock-controller@10040000 { 160 compatible = "samsung,exynos7-clock-peris"; 161 reg = <0x10040000 0xd00>; 162 #clock-cells = <1>; 163 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 164 clock-names = "fin_pll", "dout_aclk_peris_66"; 165 }; 166 167 clock_fsys0: clock-controller@10e90000 { 168 compatible = "samsung,exynos7-clock-fsys0"; 169 reg = <0x10e90000 0xd00>; 170 #clock-cells = <1>; 171 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 172 <&clock_top1 DOUT_SCLK_MMC2>; 173 clock-names = "fin_pll", "dout_aclk_fsys0_200", 174 "dout_sclk_mmc2"; 175 }; 176 177 clock_fsys1: clock-controller@156e0000 { 178 compatible = "samsung,exynos7-clock-fsys1"; 179 reg = <0x156e0000 0xd00>; 180 #clock-cells = <1>; 181 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 182 <&clock_top1 DOUT_SCLK_MMC0>, 183 <&clock_top1 DOUT_SCLK_MMC1>; 184 clock-names = "fin_pll", "dout_aclk_fsys1_200", 185 "dout_sclk_mmc0", "dout_sclk_mmc1"; 186 }; 187 188 serial_0: serial@13630000 { 189 compatible = "samsung,exynos4210-uart"; 190 reg = <0x13630000 0x100>; 191 interrupts = <0 440 0>; 192 clocks = <&clock_peric0 PCLK_UART0>, 193 <&clock_peric0 SCLK_UART0>; 194 clock-names = "uart", "clk_uart_baud0"; 195 status = "disabled"; 196 }; 197 198 serial_1: serial@14c20000 { 199 compatible = "samsung,exynos4210-uart"; 200 reg = <0x14c20000 0x100>; 201 interrupts = <0 456 0>; 202 clocks = <&clock_peric1 PCLK_UART1>, 203 <&clock_peric1 SCLK_UART1>; 204 clock-names = "uart", "clk_uart_baud0"; 205 status = "disabled"; 206 }; 207 208 serial_2: serial@14c30000 { 209 compatible = "samsung,exynos4210-uart"; 210 reg = <0x14c30000 0x100>; 211 interrupts = <0 457 0>; 212 clocks = <&clock_peric1 PCLK_UART2>, 213 <&clock_peric1 SCLK_UART2>; 214 clock-names = "uart", "clk_uart_baud0"; 215 status = "disabled"; 216 }; 217 218 serial_3: serial@14c40000 { 219 compatible = "samsung,exynos4210-uart"; 220 reg = <0x14c40000 0x100>; 221 interrupts = <0 458 0>; 222 clocks = <&clock_peric1 PCLK_UART3>, 223 <&clock_peric1 SCLK_UART3>; 224 clock-names = "uart", "clk_uart_baud0"; 225 status = "disabled"; 226 }; 227 228 pinctrl_alive: pinctrl@10580000 { 229 compatible = "samsung,exynos7-pinctrl"; 230 reg = <0x10580000 0x1000>; 231 232 wakeup-interrupt-controller { 233 compatible = "samsung,exynos7-wakeup-eint"; 234 interrupt-parent = <&gic>; 235 interrupts = <0 16 0>; 236 }; 237 }; 238 239 pinctrl_bus0: pinctrl@13470000 { 240 compatible = "samsung,exynos7-pinctrl"; 241 reg = <0x13470000 0x1000>; 242 interrupts = <0 383 0>; 243 }; 244 245 pinctrl_nfc: pinctrl@14cd0000 { 246 compatible = "samsung,exynos7-pinctrl"; 247 reg = <0x14cd0000 0x1000>; 248 interrupts = <0 473 0>; 249 }; 250 251 pinctrl_touch: pinctrl@14ce0000 { 252 compatible = "samsung,exynos7-pinctrl"; 253 reg = <0x14ce0000 0x1000>; 254 interrupts = <0 474 0>; 255 }; 256 257 pinctrl_ff: pinctrl@14c90000 { 258 compatible = "samsung,exynos7-pinctrl"; 259 reg = <0x14c90000 0x1000>; 260 interrupts = <0 475 0>; 261 }; 262 263 pinctrl_ese: pinctrl@14ca0000 { 264 compatible = "samsung,exynos7-pinctrl"; 265 reg = <0x14ca0000 0x1000>; 266 interrupts = <0 476 0>; 267 }; 268 269 pinctrl_fsys0: pinctrl@10e60000 { 270 compatible = "samsung,exynos7-pinctrl"; 271 reg = <0x10e60000 0x1000>; 272 interrupts = <0 221 0>; 273 }; 274 275 pinctrl_fsys1: pinctrl@15690000 { 276 compatible = "samsung,exynos7-pinctrl"; 277 reg = <0x15690000 0x1000>; 278 interrupts = <0 203 0>; 279 }; 280 281 hsi2c_0: hsi2c@13640000 { 282 compatible = "samsung,exynos7-hsi2c"; 283 reg = <0x13640000 0x1000>; 284 interrupts = <0 441 0>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&hs_i2c0_bus>; 289 clocks = <&clock_peric0 PCLK_HSI2C0>; 290 clock-names = "hsi2c"; 291 status = "disabled"; 292 }; 293 294 hsi2c_1: hsi2c@13650000 { 295 compatible = "samsung,exynos7-hsi2c"; 296 reg = <0x13650000 0x1000>; 297 interrupts = <0 442 0>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&hs_i2c1_bus>; 302 clocks = <&clock_peric0 PCLK_HSI2C1>; 303 clock-names = "hsi2c"; 304 status = "disabled"; 305 }; 306 307 hsi2c_2: hsi2c@14e60000 { 308 compatible = "samsung,exynos7-hsi2c"; 309 reg = <0x14e60000 0x1000>; 310 interrupts = <0 459 0>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&hs_i2c2_bus>; 315 clocks = <&clock_peric1 PCLK_HSI2C2>; 316 clock-names = "hsi2c"; 317 status = "disabled"; 318 }; 319 320 hsi2c_3: hsi2c@14e70000 { 321 compatible = "samsung,exynos7-hsi2c"; 322 reg = <0x14e70000 0x1000>; 323 interrupts = <0 460 0>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&hs_i2c3_bus>; 328 clocks = <&clock_peric1 PCLK_HSI2C3>; 329 clock-names = "hsi2c"; 330 status = "disabled"; 331 }; 332 333 hsi2c_4: hsi2c@13660000 { 334 compatible = "samsung,exynos7-hsi2c"; 335 reg = <0x13660000 0x1000>; 336 interrupts = <0 443 0>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&hs_i2c4_bus>; 341 clocks = <&clock_peric0 PCLK_HSI2C4>; 342 clock-names = "hsi2c"; 343 status = "disabled"; 344 }; 345 346 hsi2c_5: hsi2c@13670000 { 347 compatible = "samsung,exynos7-hsi2c"; 348 reg = <0x13670000 0x1000>; 349 interrupts = <0 444 0>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&hs_i2c5_bus>; 354 clocks = <&clock_peric0 PCLK_HSI2C5>; 355 clock-names = "hsi2c"; 356 status = "disabled"; 357 }; 358 359 hsi2c_6: hsi2c@14e00000 { 360 compatible = "samsung,exynos7-hsi2c"; 361 reg = <0x14e00000 0x1000>; 362 interrupts = <0 461 0>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&hs_i2c6_bus>; 367 clocks = <&clock_peric1 PCLK_HSI2C6>; 368 clock-names = "hsi2c"; 369 status = "disabled"; 370 }; 371 372 hsi2c_7: hsi2c@13e10000 { 373 compatible = "samsung,exynos7-hsi2c"; 374 reg = <0x13e10000 0x1000>; 375 interrupts = <0 462 0>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&hs_i2c7_bus>; 380 clocks = <&clock_peric1 PCLK_HSI2C7>; 381 clock-names = "hsi2c"; 382 status = "disabled"; 383 }; 384 385 hsi2c_8: hsi2c@14e20000 { 386 compatible = "samsung,exynos7-hsi2c"; 387 reg = <0x14e20000 0x1000>; 388 interrupts = <0 463 0>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&hs_i2c8_bus>; 393 clocks = <&clock_peric1 PCLK_HSI2C8>; 394 clock-names = "hsi2c"; 395 status = "disabled"; 396 }; 397 398 hsi2c_9: hsi2c@13680000 { 399 compatible = "samsung,exynos7-hsi2c"; 400 reg = <0x13680000 0x1000>; 401 interrupts = <0 445 0>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&hs_i2c9_bus>; 406 clocks = <&clock_peric0 PCLK_HSI2C9>; 407 clock-names = "hsi2c"; 408 status = "disabled"; 409 }; 410 411 hsi2c_10: hsi2c@13690000 { 412 compatible = "samsung,exynos7-hsi2c"; 413 reg = <0x13690000 0x1000>; 414 interrupts = <0 446 0>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&hs_i2c10_bus>; 419 clocks = <&clock_peric0 PCLK_HSI2C10>; 420 clock-names = "hsi2c"; 421 status = "disabled"; 422 }; 423 424 hsi2c_11: hsi2c@136a0000 { 425 compatible = "samsung,exynos7-hsi2c"; 426 reg = <0x136a0000 0x1000>; 427 interrupts = <0 447 0>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&hs_i2c11_bus>; 432 clocks = <&clock_peric0 PCLK_HSI2C11>; 433 clock-names = "hsi2c"; 434 status = "disabled"; 435 }; 436 437 timer { 438 compatible = "arm,armv8-timer"; 439 interrupts = <1 13 0xff01>, 440 <1 14 0xff01>, 441 <1 11 0xff01>, 442 <1 10 0xff01>; 443 }; 444 445 pmu_system_controller: system-controller@105c0000 { 446 compatible = "samsung,exynos7-pmu", "syscon"; 447 reg = <0x105c0000 0x5000>; 448 }; 449 450 rtc: rtc@10590000 { 451 compatible = "samsung,s3c6410-rtc"; 452 reg = <0x10590000 0x100>; 453 interrupts = <0 355 0>, <0 356 0>; 454 clocks = <&clock_ccore PCLK_RTC>; 455 clock-names = "rtc"; 456 status = "disabled"; 457 }; 458 459 watchdog: watchdog@101d0000 { 460 compatible = "samsung,exynos7-wdt"; 461 reg = <0x101d0000 0x100>; 462 interrupts = <0 110 0>; 463 clocks = <&clock_peris PCLK_WDT>; 464 clock-names = "watchdog"; 465 samsung,syscon-phandle = <&pmu_system_controller>; 466 status = "disabled"; 467 }; 468 469 mmc_0: mmc@15740000 { 470 compatible = "samsung,exynos7-dw-mshc-smu"; 471 interrupts = <0 201 0>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 reg = <0x15740000 0x2000>; 475 clocks = <&clock_fsys1 ACLK_MMC0>, 476 <&clock_top1 CLK_SCLK_MMC0>; 477 clock-names = "biu", "ciu"; 478 fifo-depth = <0x40>; 479 status = "disabled"; 480 }; 481 482 mmc_1: mmc@15750000 { 483 compatible = "samsung,exynos7-dw-mshc"; 484 interrupts = <0 202 0>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0x15750000 0x2000>; 488 clocks = <&clock_fsys1 ACLK_MMC1>, 489 <&clock_top1 CLK_SCLK_MMC1>; 490 clock-names = "biu", "ciu"; 491 fifo-depth = <0x40>; 492 status = "disabled"; 493 }; 494 495 mmc_2: mmc@15560000 { 496 compatible = "samsung,exynos7-dw-mshc-smu"; 497 interrupts = <0 216 0>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 reg = <0x15560000 0x2000>; 501 clocks = <&clock_fsys0 ACLK_MMC2>, 502 <&clock_top1 CLK_SCLK_MMC2>; 503 clock-names = "biu", "ciu"; 504 fifo-depth = <0x40>; 505 status = "disabled"; 506 }; 507 508 adc: adc@13620000 { 509 compatible = "samsung,exynos7-adc"; 510 reg = <0x13620000 0x100>; 511 interrupts = <0 448 0>; 512 clocks = <&clock_peric0 PCLK_ADCIF>; 513 clock-names = "adc"; 514 #io-channel-cells = <1>; 515 io-channel-ranges; 516 status = "disabled"; 517 }; 518 519 pwm: pwm@136c0000 { 520 compatible = "samsung,exynos4210-pwm"; 521 reg = <0x136c0000 0x100>; 522 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 523 #pwm-cells = <3>; 524 clocks = <&clock_peric0 PCLK_PWM>; 525 clock-names = "timers"; 526 }; 527 }; 528}; 529 530#include "exynos7-pinctrl.dtsi" 531