1/* 2 * SAMSUNG EXYNOS7 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <dt-bindings/clock/exynos7-clk.h> 13 14/ { 15 compatible = "samsung,exynos7"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 pinctrl0 = &pinctrl_alive; 22 pinctrl1 = &pinctrl_bus0; 23 pinctrl2 = &pinctrl_nfc; 24 pinctrl3 = &pinctrl_touch; 25 pinctrl4 = &pinctrl_ff; 26 pinctrl5 = &pinctrl_ese; 27 pinctrl6 = &pinctrl_fsys0; 28 pinctrl7 = &pinctrl_fsys1; 29 pinctrl8 = &pinctrl_bus1; 30 tmuctrl0 = &tmuctrl_0; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a57", "arm,armv8"; 40 reg = <0x0>; 41 enable-method = "psci"; 42 }; 43 44 cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a57", "arm,armv8"; 47 reg = <0x1>; 48 enable-method = "psci"; 49 }; 50 51 cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a57", "arm,armv8"; 54 reg = <0x2>; 55 enable-method = "psci"; 56 }; 57 58 cpu@3 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a57", "arm,armv8"; 61 reg = <0x3>; 62 enable-method = "psci"; 63 }; 64 }; 65 66 psci { 67 compatible = "arm,psci-0.2"; 68 method = "smc"; 69 }; 70 71 soc: soc { 72 compatible = "simple-bus"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges = <0 0 0 0x18000000>; 76 77 chipid@10000000 { 78 compatible = "samsung,exynos4210-chipid"; 79 reg = <0x10000000 0x100>; 80 }; 81 82 fin_pll: xxti { 83 compatible = "fixed-clock"; 84 clock-output-names = "fin_pll"; 85 #clock-cells = <0>; 86 }; 87 88 gic: interrupt-controller@11001000 { 89 compatible = "arm,gic-400"; 90 #interrupt-cells = <3>; 91 #address-cells = <0>; 92 interrupt-controller; 93 reg = <0x11001000 0x1000>, 94 <0x11002000 0x1000>, 95 <0x11004000 0x2000>, 96 <0x11006000 0x2000>; 97 }; 98 99 amba { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 ranges; 104 105 pdma0: pdma@10E10000 { 106 compatible = "arm,pl330", "arm,primecell"; 107 reg = <0x10E10000 0x1000>; 108 interrupts = <0 225 0>; 109 clocks = <&clock_fsys0 ACLK_PDMA0>; 110 clock-names = "apb_pclk"; 111 #dma-cells = <1>; 112 #dma-channels = <8>; 113 #dma-requests = <32>; 114 }; 115 116 pdma1: pdma@10EB0000 { 117 compatible = "arm,pl330", "arm,primecell"; 118 reg = <0x10EB0000 0x1000>; 119 interrupts = <0 226 0>; 120 clocks = <&clock_fsys0 ACLK_PDMA1>; 121 clock-names = "apb_pclk"; 122 #dma-cells = <1>; 123 #dma-channels = <8>; 124 #dma-requests = <32>; 125 }; 126 }; 127 128 clock_topc: clock-controller@10570000 { 129 compatible = "samsung,exynos7-clock-topc"; 130 reg = <0x10570000 0x10000>; 131 #clock-cells = <1>; 132 }; 133 134 clock_top0: clock-controller@105d0000 { 135 compatible = "samsung,exynos7-clock-top0"; 136 reg = <0x105d0000 0xb000>; 137 #clock-cells = <1>; 138 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 139 <&clock_topc DOUT_SCLK_BUS1_PLL>, 140 <&clock_topc DOUT_SCLK_CC_PLL>, 141 <&clock_topc DOUT_SCLK_MFC_PLL>; 142 clock-names = "fin_pll", "dout_sclk_bus0_pll", 143 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 144 "dout_sclk_mfc_pll"; 145 }; 146 147 clock_top1: clock-controller@105e0000 { 148 compatible = "samsung,exynos7-clock-top1"; 149 reg = <0x105e0000 0xb000>; 150 #clock-cells = <1>; 151 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 152 <&clock_topc DOUT_SCLK_BUS1_PLL>, 153 <&clock_topc DOUT_SCLK_CC_PLL>, 154 <&clock_topc DOUT_SCLK_MFC_PLL>; 155 clock-names = "fin_pll", "dout_sclk_bus0_pll", 156 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 157 "dout_sclk_mfc_pll"; 158 }; 159 160 clock_ccore: clock-controller@105b0000 { 161 compatible = "samsung,exynos7-clock-ccore"; 162 reg = <0x105b0000 0xd00>; 163 #clock-cells = <1>; 164 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 165 clock-names = "fin_pll", "dout_aclk_ccore_133"; 166 }; 167 168 clock_peric0: clock-controller@13610000 { 169 compatible = "samsung,exynos7-clock-peric0"; 170 reg = <0x13610000 0xd00>; 171 #clock-cells = <1>; 172 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 173 <&clock_top0 CLK_SCLK_UART0>; 174 clock-names = "fin_pll", "dout_aclk_peric0_66", 175 "sclk_uart0"; 176 }; 177 178 clock_peric1: clock-controller@14c80000 { 179 compatible = "samsung,exynos7-clock-peric1"; 180 reg = <0x14c80000 0xd00>; 181 #clock-cells = <1>; 182 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 183 <&clock_top0 CLK_SCLK_UART1>, 184 <&clock_top0 CLK_SCLK_UART2>, 185 <&clock_top0 CLK_SCLK_UART3>; 186 clock-names = "fin_pll", "dout_aclk_peric1_66", 187 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 188 }; 189 190 clock_peris: clock-controller@10040000 { 191 compatible = "samsung,exynos7-clock-peris"; 192 reg = <0x10040000 0xd00>; 193 #clock-cells = <1>; 194 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 195 clock-names = "fin_pll", "dout_aclk_peris_66"; 196 }; 197 198 clock_fsys0: clock-controller@10e90000 { 199 compatible = "samsung,exynos7-clock-fsys0"; 200 reg = <0x10e90000 0xd00>; 201 #clock-cells = <1>; 202 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 203 <&clock_top1 DOUT_SCLK_MMC2>; 204 clock-names = "fin_pll", "dout_aclk_fsys0_200", 205 "dout_sclk_mmc2"; 206 }; 207 208 clock_fsys1: clock-controller@156e0000 { 209 compatible = "samsung,exynos7-clock-fsys1"; 210 reg = <0x156e0000 0xd00>; 211 #clock-cells = <1>; 212 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 213 <&clock_top1 DOUT_SCLK_MMC0>, 214 <&clock_top1 DOUT_SCLK_MMC1>; 215 clock-names = "fin_pll", "dout_aclk_fsys1_200", 216 "dout_sclk_mmc0", "dout_sclk_mmc1"; 217 }; 218 219 serial_0: serial@13630000 { 220 compatible = "samsung,exynos4210-uart"; 221 reg = <0x13630000 0x100>; 222 interrupts = <0 440 0>; 223 clocks = <&clock_peric0 PCLK_UART0>, 224 <&clock_peric0 SCLK_UART0>; 225 clock-names = "uart", "clk_uart_baud0"; 226 status = "disabled"; 227 }; 228 229 serial_1: serial@14c20000 { 230 compatible = "samsung,exynos4210-uart"; 231 reg = <0x14c20000 0x100>; 232 interrupts = <0 456 0>; 233 clocks = <&clock_peric1 PCLK_UART1>, 234 <&clock_peric1 SCLK_UART1>; 235 clock-names = "uart", "clk_uart_baud0"; 236 status = "disabled"; 237 }; 238 239 serial_2: serial@14c30000 { 240 compatible = "samsung,exynos4210-uart"; 241 reg = <0x14c30000 0x100>; 242 interrupts = <0 457 0>; 243 clocks = <&clock_peric1 PCLK_UART2>, 244 <&clock_peric1 SCLK_UART2>; 245 clock-names = "uart", "clk_uart_baud0"; 246 status = "disabled"; 247 }; 248 249 serial_3: serial@14c40000 { 250 compatible = "samsung,exynos4210-uart"; 251 reg = <0x14c40000 0x100>; 252 interrupts = <0 458 0>; 253 clocks = <&clock_peric1 PCLK_UART3>, 254 <&clock_peric1 SCLK_UART3>; 255 clock-names = "uart", "clk_uart_baud0"; 256 status = "disabled"; 257 }; 258 259 pinctrl_alive: pinctrl@10580000 { 260 compatible = "samsung,exynos7-pinctrl"; 261 reg = <0x10580000 0x1000>; 262 263 wakeup-interrupt-controller { 264 compatible = "samsung,exynos7-wakeup-eint"; 265 interrupt-parent = <&gic>; 266 interrupts = <0 16 0>; 267 }; 268 }; 269 270 pinctrl_bus0: pinctrl@13470000 { 271 compatible = "samsung,exynos7-pinctrl"; 272 reg = <0x13470000 0x1000>; 273 interrupts = <0 383 0>; 274 }; 275 276 pinctrl_nfc: pinctrl@14cd0000 { 277 compatible = "samsung,exynos7-pinctrl"; 278 reg = <0x14cd0000 0x1000>; 279 interrupts = <0 473 0>; 280 }; 281 282 pinctrl_touch: pinctrl@14ce0000 { 283 compatible = "samsung,exynos7-pinctrl"; 284 reg = <0x14ce0000 0x1000>; 285 interrupts = <0 474 0>; 286 }; 287 288 pinctrl_ff: pinctrl@14c90000 { 289 compatible = "samsung,exynos7-pinctrl"; 290 reg = <0x14c90000 0x1000>; 291 interrupts = <0 475 0>; 292 }; 293 294 pinctrl_ese: pinctrl@14ca0000 { 295 compatible = "samsung,exynos7-pinctrl"; 296 reg = <0x14ca0000 0x1000>; 297 interrupts = <0 476 0>; 298 }; 299 300 pinctrl_fsys0: pinctrl@10e60000 { 301 compatible = "samsung,exynos7-pinctrl"; 302 reg = <0x10e60000 0x1000>; 303 interrupts = <0 221 0>; 304 }; 305 306 pinctrl_fsys1: pinctrl@15690000 { 307 compatible = "samsung,exynos7-pinctrl"; 308 reg = <0x15690000 0x1000>; 309 interrupts = <0 203 0>; 310 }; 311 312 pinctrl_bus1: pinctrl@14870000 { 313 compatible = "samsung,exynos7-pinctrl"; 314 reg = <0x14870000 0x1000>; 315 interrupts = <0 384 0>; 316 }; 317 318 hsi2c_0: hsi2c@13640000 { 319 compatible = "samsung,exynos7-hsi2c"; 320 reg = <0x13640000 0x1000>; 321 interrupts = <0 441 0>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&hs_i2c0_bus>; 326 clocks = <&clock_peric0 PCLK_HSI2C0>; 327 clock-names = "hsi2c"; 328 status = "disabled"; 329 }; 330 331 hsi2c_1: hsi2c@13650000 { 332 compatible = "samsung,exynos7-hsi2c"; 333 reg = <0x13650000 0x1000>; 334 interrupts = <0 442 0>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&hs_i2c1_bus>; 339 clocks = <&clock_peric0 PCLK_HSI2C1>; 340 clock-names = "hsi2c"; 341 status = "disabled"; 342 }; 343 344 hsi2c_2: hsi2c@14e60000 { 345 compatible = "samsung,exynos7-hsi2c"; 346 reg = <0x14e60000 0x1000>; 347 interrupts = <0 459 0>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&hs_i2c2_bus>; 352 clocks = <&clock_peric1 PCLK_HSI2C2>; 353 clock-names = "hsi2c"; 354 status = "disabled"; 355 }; 356 357 hsi2c_3: hsi2c@14e70000 { 358 compatible = "samsung,exynos7-hsi2c"; 359 reg = <0x14e70000 0x1000>; 360 interrupts = <0 460 0>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&hs_i2c3_bus>; 365 clocks = <&clock_peric1 PCLK_HSI2C3>; 366 clock-names = "hsi2c"; 367 status = "disabled"; 368 }; 369 370 hsi2c_4: hsi2c@13660000 { 371 compatible = "samsung,exynos7-hsi2c"; 372 reg = <0x13660000 0x1000>; 373 interrupts = <0 443 0>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&hs_i2c4_bus>; 378 clocks = <&clock_peric0 PCLK_HSI2C4>; 379 clock-names = "hsi2c"; 380 status = "disabled"; 381 }; 382 383 hsi2c_5: hsi2c@13670000 { 384 compatible = "samsung,exynos7-hsi2c"; 385 reg = <0x13670000 0x1000>; 386 interrupts = <0 444 0>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&hs_i2c5_bus>; 391 clocks = <&clock_peric0 PCLK_HSI2C5>; 392 clock-names = "hsi2c"; 393 status = "disabled"; 394 }; 395 396 hsi2c_6: hsi2c@14e00000 { 397 compatible = "samsung,exynos7-hsi2c"; 398 reg = <0x14e00000 0x1000>; 399 interrupts = <0 461 0>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&hs_i2c6_bus>; 404 clocks = <&clock_peric1 PCLK_HSI2C6>; 405 clock-names = "hsi2c"; 406 status = "disabled"; 407 }; 408 409 hsi2c_7: hsi2c@13e10000 { 410 compatible = "samsung,exynos7-hsi2c"; 411 reg = <0x13e10000 0x1000>; 412 interrupts = <0 462 0>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&hs_i2c7_bus>; 417 clocks = <&clock_peric1 PCLK_HSI2C7>; 418 clock-names = "hsi2c"; 419 status = "disabled"; 420 }; 421 422 hsi2c_8: hsi2c@14e20000 { 423 compatible = "samsung,exynos7-hsi2c"; 424 reg = <0x14e20000 0x1000>; 425 interrupts = <0 463 0>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&hs_i2c8_bus>; 430 clocks = <&clock_peric1 PCLK_HSI2C8>; 431 clock-names = "hsi2c"; 432 status = "disabled"; 433 }; 434 435 hsi2c_9: hsi2c@13680000 { 436 compatible = "samsung,exynos7-hsi2c"; 437 reg = <0x13680000 0x1000>; 438 interrupts = <0 445 0>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&hs_i2c9_bus>; 443 clocks = <&clock_peric0 PCLK_HSI2C9>; 444 clock-names = "hsi2c"; 445 status = "disabled"; 446 }; 447 448 hsi2c_10: hsi2c@13690000 { 449 compatible = "samsung,exynos7-hsi2c"; 450 reg = <0x13690000 0x1000>; 451 interrupts = <0 446 0>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&hs_i2c10_bus>; 456 clocks = <&clock_peric0 PCLK_HSI2C10>; 457 clock-names = "hsi2c"; 458 status = "disabled"; 459 }; 460 461 hsi2c_11: hsi2c@136a0000 { 462 compatible = "samsung,exynos7-hsi2c"; 463 reg = <0x136a0000 0x1000>; 464 interrupts = <0 447 0>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&hs_i2c11_bus>; 469 clocks = <&clock_peric0 PCLK_HSI2C11>; 470 clock-names = "hsi2c"; 471 status = "disabled"; 472 }; 473 474 timer { 475 compatible = "arm,armv8-timer"; 476 interrupts = <1 13 0xff01>, 477 <1 14 0xff01>, 478 <1 11 0xff01>, 479 <1 10 0xff01>; 480 }; 481 482 pmu_system_controller: system-controller@105c0000 { 483 compatible = "samsung,exynos7-pmu", "syscon"; 484 reg = <0x105c0000 0x5000>; 485 }; 486 487 reboot: syscon-reboot { 488 compatible = "syscon-reboot"; 489 regmap = <&pmu_system_controller>; 490 offset = <0x0400>; 491 mask = <0x1>; 492 }; 493 494 rtc: rtc@10590000 { 495 compatible = "samsung,s3c6410-rtc"; 496 reg = <0x10590000 0x100>; 497 interrupts = <0 355 0>, <0 356 0>; 498 clocks = <&clock_ccore PCLK_RTC>; 499 clock-names = "rtc"; 500 status = "disabled"; 501 }; 502 503 watchdog: watchdog@101d0000 { 504 compatible = "samsung,exynos7-wdt"; 505 reg = <0x101d0000 0x100>; 506 interrupts = <0 110 0>; 507 clocks = <&clock_peris PCLK_WDT>; 508 clock-names = "watchdog"; 509 samsung,syscon-phandle = <&pmu_system_controller>; 510 status = "disabled"; 511 }; 512 513 mmc_0: mmc@15740000 { 514 compatible = "samsung,exynos7-dw-mshc-smu"; 515 interrupts = <0 201 0>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 reg = <0x15740000 0x2000>; 519 clocks = <&clock_fsys1 ACLK_MMC0>, 520 <&clock_top1 CLK_SCLK_MMC0>; 521 clock-names = "biu", "ciu"; 522 fifo-depth = <0x40>; 523 status = "disabled"; 524 }; 525 526 mmc_1: mmc@15750000 { 527 compatible = "samsung,exynos7-dw-mshc"; 528 interrupts = <0 202 0>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 reg = <0x15750000 0x2000>; 532 clocks = <&clock_fsys1 ACLK_MMC1>, 533 <&clock_top1 CLK_SCLK_MMC1>; 534 clock-names = "biu", "ciu"; 535 fifo-depth = <0x40>; 536 status = "disabled"; 537 }; 538 539 mmc_2: mmc@15560000 { 540 compatible = "samsung,exynos7-dw-mshc-smu"; 541 interrupts = <0 216 0>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <0x15560000 0x2000>; 545 clocks = <&clock_fsys0 ACLK_MMC2>, 546 <&clock_top1 CLK_SCLK_MMC2>; 547 clock-names = "biu", "ciu"; 548 fifo-depth = <0x40>; 549 status = "disabled"; 550 }; 551 552 adc: adc@13620000 { 553 compatible = "samsung,exynos7-adc"; 554 reg = <0x13620000 0x100>; 555 interrupts = <0 448 0>; 556 clocks = <&clock_peric0 PCLK_ADCIF>; 557 clock-names = "adc"; 558 #io-channel-cells = <1>; 559 io-channel-ranges; 560 status = "disabled"; 561 }; 562 563 pwm: pwm@136c0000 { 564 compatible = "samsung,exynos4210-pwm"; 565 reg = <0x136c0000 0x100>; 566 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 567 #pwm-cells = <3>; 568 clocks = <&clock_peric0 PCLK_PWM>; 569 clock-names = "timers"; 570 }; 571 572 tmuctrl_0: tmu@10060000 { 573 compatible = "samsung,exynos7-tmu"; 574 reg = <0x10060000 0x200>; 575 interrupts = <0 108 0>; 576 clocks = <&clock_peris PCLK_TMU>, 577 <&clock_peris SCLK_TMU>; 578 clock-names = "tmu_apbif", "tmu_sclk"; 579 #include "exynos7-tmu-sensor-conf.dtsi" 580 }; 581 582 thermal-zones { 583 atlas_thermal: cluster0-thermal { 584 polling-delay-passive = <0>; /* milliseconds */ 585 polling-delay = <0>; /* milliseconds */ 586 thermal-sensors = <&tmuctrl_0>; 587 #include "exynos7-trip-points.dtsi" 588 }; 589 }; 590 }; 591}; 592 593#include "exynos7-pinctrl.dtsi" 594