1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright 2025 Cix Technology Group Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/cix,sky1.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a520"; 21 enable-method = "psci"; 22 reg = <0x0 0x0>; 23 device_type = "cpu"; 24 capacity-dmips-mhz = <403>; 25 }; 26 27 cpu1: cpu@100 { 28 compatible = "arm,cortex-a520"; 29 enable-method = "psci"; 30 reg = <0x0 0x100>; 31 device_type = "cpu"; 32 capacity-dmips-mhz = <403>; 33 }; 34 35 cpu2: cpu@200 { 36 compatible = "arm,cortex-a520"; 37 enable-method = "psci"; 38 reg = <0x0 0x200>; 39 device_type = "cpu"; 40 capacity-dmips-mhz = <403>; 41 }; 42 43 cpu3: cpu@300 { 44 compatible = "arm,cortex-a520"; 45 enable-method = "psci"; 46 reg = <0x0 0x300>; 47 device_type = "cpu"; 48 capacity-dmips-mhz = <403>; 49 }; 50 51 cpu4: cpu@400 { 52 compatible = "arm,cortex-a720"; 53 enable-method = "psci"; 54 reg = <0x0 0x400>; 55 device_type = "cpu"; 56 capacity-dmips-mhz = <1024>; 57 }; 58 59 cpu5: cpu@500 { 60 compatible = "arm,cortex-a720"; 61 enable-method = "psci"; 62 reg = <0x0 0x500>; 63 device_type = "cpu"; 64 capacity-dmips-mhz = <1024>; 65 }; 66 67 cpu6: cpu@600 { 68 compatible = "arm,cortex-a720"; 69 enable-method = "psci"; 70 reg = <0x0 0x600>; 71 device_type = "cpu"; 72 capacity-dmips-mhz = <1024>; 73 }; 74 75 cpu7: cpu@700 { 76 compatible = "arm,cortex-a720"; 77 enable-method = "psci"; 78 reg = <0x0 0x700>; 79 device_type = "cpu"; 80 capacity-dmips-mhz = <1024>; 81 }; 82 83 cpu8: cpu@800 { 84 compatible = "arm,cortex-a720"; 85 enable-method = "psci"; 86 reg = <0x0 0x800>; 87 device_type = "cpu"; 88 capacity-dmips-mhz = <1024>; 89 }; 90 91 cpu9: cpu@900 { 92 compatible = "arm,cortex-a720"; 93 enable-method = "psci"; 94 reg = <0x0 0x900>; 95 device_type = "cpu"; 96 capacity-dmips-mhz = <1024>; 97 }; 98 99 cpu10: cpu@a00 { 100 compatible = "arm,cortex-a720"; 101 enable-method = "psci"; 102 reg = <0x0 0xa00>; 103 device_type = "cpu"; 104 capacity-dmips-mhz = <1024>; 105 }; 106 107 cpu11: cpu@b00 { 108 compatible = "arm,cortex-a720"; 109 enable-method = "psci"; 110 reg = <0x0 0xb00>; 111 device_type = "cpu"; 112 capacity-dmips-mhz = <1024>; 113 }; 114 115 cpu-map { 116 cluster0 { 117 core0 { 118 cpu = <&cpu0>; 119 }; 120 core1 { 121 cpu = <&cpu1>; 122 }; 123 core2 { 124 cpu = <&cpu2>; 125 }; 126 core3 { 127 cpu = <&cpu3>; 128 }; 129 core4 { 130 cpu = <&cpu4>; 131 }; 132 core5 { 133 cpu = <&cpu5>; 134 }; 135 core6 { 136 cpu = <&cpu6>; 137 }; 138 core7 { 139 cpu = <&cpu7>; 140 }; 141 core8 { 142 cpu = <&cpu8>; 143 }; 144 core9 { 145 cpu = <&cpu9>; 146 }; 147 core10 { 148 cpu = <&cpu10>; 149 }; 150 core11 { 151 cpu = <&cpu11>; 152 }; 153 }; 154 }; 155 }; 156 157 firmware { 158 ap_to_pm_scmi: scmi { 159 compatible = "arm,scmi"; 160 mbox-names = "tx", "rx"; 161 mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>; 162 shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 scmi_clk: protocol@14 { 167 reg = <0x14>; 168 #clock-cells = <1>; 169 }; 170 }; 171 }; 172 173 pmu-a520 { 174 compatible = "arm,cortex-a520-pmu"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>; 176 }; 177 178 pmu-a720 { 179 compatible = "arm,cortex-a720-pmu"; 180 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>; 181 }; 182 183 psci { 184 compatible = "arm,psci-1.0"; 185 method = "smc"; 186 }; 187 188 soc@0 { 189 compatible = "simple-bus"; 190 ranges = <0 0 0 0 0x20 0>; 191 dma-ranges; 192 #address-cells = <2>; 193 #size-cells = <2>; 194 195 i2c0: i2c@4010000 { 196 compatible = "cdns,i2c-r1p14"; 197 reg = <0x0 0x04010000 0x0 0x10000>; 198 clock-frequency = <400000>; 199 clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>; 200 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>; 201 status = "disabled"; 202 }; 203 204 i2c1: i2c@4020000 { 205 compatible = "cdns,i2c-r1p14"; 206 reg = <0x0 0x04020000 0x0 0x10000>; 207 clock-frequency = <400000>; 208 clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>; 209 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0>; 210 status = "disabled"; 211 }; 212 213 i2c2: i2c@4030000 { 214 compatible = "cdns,i2c-r1p14"; 215 reg = <0x0 0x04030000 0x0 0x10000>; 216 clock-frequency = <400000>; 217 clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>; 218 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>; 219 status = "disabled"; 220 }; 221 222 i2c3: i2c@4040000 { 223 compatible = "cdns,i2c-r1p14"; 224 reg = <0x0 0x04040000 0x0 0x10000>; 225 clock-frequency = <400000>; 226 clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>; 227 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 228 status = "disabled"; 229 }; 230 231 i2c4: i2c@4050000 { 232 compatible = "cdns,i2c-r1p14"; 233 reg = <0x0 0x04050000 0x0 0x10000>; 234 clock-frequency = <400000>; 235 clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>; 236 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>; 237 status = "disabled"; 238 }; 239 240 i2c5: i2c@4060000 { 241 compatible = "cdns,i2c-r1p14"; 242 reg = <0x0 0x04060000 0x0 0x10000>; 243 clock-frequency = <400000>; 244 clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>; 245 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>; 246 status = "disabled"; 247 }; 248 249 i2c6: i2c@4070000 { 250 compatible = "cdns,i2c-r1p14"; 251 reg = <0x0 0x04070000 0x0 0x10000>; 252 clock-frequency = <400000>; 253 clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>; 254 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0>; 255 status = "disabled"; 256 }; 257 258 i2c7: i2c@4080000 { 259 compatible = "cdns,i2c-r1p14"; 260 reg = <0x0 0x04080000 0x0 0x10000>; 261 clock-frequency = <400000>; 262 clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>; 263 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 264 status = "disabled"; 265 }; 266 267 spi0: spi@4090000 { 268 compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; 269 reg = <0x0 0x04090000 0x0 0x10000>; 270 clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>, 271 <&scmi_clk CLK_TREE_FCH_SPI0_APB>; 272 clock-names = "ref_clk", "pclk"; 273 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 274 status = "disabled"; 275 }; 276 277 spi1: spi@40a0000 { 278 compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; 279 reg = <0x0 0x040a0000 0x0 0x10000>; 280 clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>, 281 <&scmi_clk CLK_TREE_FCH_SPI1_APB>; 282 clock-names = "ref_clk", "pclk"; 283 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 284 status = "disabled"; 285 }; 286 287 uart0: serial@40b0000 { 288 compatible = "arm,pl011", "arm,primecell"; 289 reg = <0x0 0x040b0000 0x0 0x1000>; 290 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>; 291 clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>; 292 clock-names = "uartclk", "apb_pclk"; 293 status = "disabled"; 294 }; 295 296 uart1: serial@40c0000 { 297 compatible = "arm,pl011", "arm,primecell"; 298 reg = <0x0 0x040c0000 0x0 0x1000>; 299 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 300 clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>; 301 clock-names = "uartclk", "apb_pclk"; 302 status = "disabled"; 303 }; 304 305 uart2: serial@40d0000 { 306 compatible = "arm,pl011", "arm,primecell"; 307 reg = <0x0 0x040d0000 0x0 0x1000>; 308 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 309 clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>; 310 clock-names = "uartclk", "apb_pclk"; 311 status = "disabled"; 312 }; 313 314 uart3: serial@40e0000 { 315 compatible = "arm,pl011", "arm,primecell"; 316 reg = <0x0 0x040e0000 0x0 0x1000>; 317 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 318 clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>; 319 clock-names = "uartclk", "apb_pclk"; 320 status = "disabled"; 321 }; 322 323 i3c0: i3c@40f0000 { 324 compatible = "cdns,i3c-master"; 325 reg = <0x0 0x040f0000 0x0 0x10000>; 326 #address-cells = <3>; 327 #size-cells = <0>; 328 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 329 clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>, 330 <&scmi_clk CLK_TREE_FCH_I3C0_FUNC>; 331 clock-names = "pclk", "sysclk"; 332 i3c-scl-hz = <400000>; 333 i2c-scl-hz = <100000>; 334 status = "disabled"; 335 }; 336 337 i3c1: i3c@4100000 { 338 compatible = "cdns,i3c-master"; 339 reg = <0x0 0x04100000 0x0 0x10000>; 340 #address-cells = <3>; 341 #size-cells = <0>; 342 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 343 clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>, 344 <&scmi_clk CLK_TREE_FCH_I3C1_FUNC>; 345 clock-names = "pclk", "sysclk"; 346 i3c-scl-hz = <400000>; 347 i2c-scl-hz = <100000>; 348 status = "disabled"; 349 }; 350 351 iomuxc: pinctrl@4170000 { 352 compatible = "cix,sky1-pinctrl"; 353 reg = <0x0 0x04170000 0x0 0x1000>; 354 }; 355 356 mbox_ap2se: mailbox@5060000 { 357 compatible = "cix,sky1-mbox"; 358 reg = <0x0 0x05060000 0x0 0x10000>; 359 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>; 360 #mbox-cells = <1>; 361 cix,mbox-dir = "tx"; 362 }; 363 364 mbox_se2ap: mailbox@5070000 { 365 compatible = "cix,sky1-mbox"; 366 reg = <0x0 0x05070000 0x0 0x10000>; 367 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 368 #mbox-cells = <1>; 369 cix,mbox-dir = "rx"; 370 }; 371 372 ap2pm_scmi_mem: shmem@6590000 { 373 compatible = "arm,scmi-shmem"; 374 reg = <0x0 0x06590000 0x0 0x80>; 375 reg-io-width = <4>; 376 }; 377 378 mbox_ap2pm: mailbox@6590080 { 379 compatible = "cix,sky1-mbox"; 380 reg = <0x0 0x06590080 0x0 0xff80>; 381 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 382 #mbox-cells = <1>; 383 cix,mbox-dir = "tx"; 384 }; 385 386 pm2ap_scmi_mem: shmem@65a0000 { 387 compatible = "arm,scmi-shmem"; 388 reg = <0x0 0x065a0000 0x0 0x80>; 389 reg-io-width = <4>; 390 }; 391 392 mbox_pm2ap: mailbox@65a0080 { 393 compatible = "cix,sky1-mbox"; 394 reg = <0x0 0x065a0080 0x0 0xff80>; 395 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>; 396 #mbox-cells = <1>; 397 cix,mbox-dir = "rx"; 398 }; 399 400 mbox_sfh2ap: mailbox@8090000 { 401 compatible = "cix,sky1-mbox"; 402 reg = <0x0 0x08090000 0x0 0x10000>; 403 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 404 #mbox-cells = <1>; 405 cix,mbox-dir = "rx"; 406 }; 407 408 mbox_ap2sfh: mailbox@80a0000 { 409 compatible = "cix,sky1-mbox"; 410 reg = <0x0 0x080a0000 0x0 0x10000>; 411 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 412 #mbox-cells = <1>; 413 cix,mbox-dir = "tx"; 414 }; 415 416 pcie_x8_rc: pcie@a010000 { 417 compatible = "cix,sky1-pcie-host"; 418 reg = <0x00 0x0a010000 0x00 0x10000>, 419 <0x00 0x2c000000 0x00 0x4000000>, 420 <0x00 0x0a000300 0x00 0x100>, 421 <0x00 0x0a000400 0x00 0x100>, 422 <0x00 0x60000000 0x00 0x00100000>; 423 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 424 ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, 425 <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, 426 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; 427 #address-cells = <3>; 428 #size-cells = <2>; 429 bus-range = <0xc0 0xff>; 430 device_type = "pci"; 431 #interrupt-cells = <1>; 432 interrupt-map-mask = <0 0 0 0x7>; 433 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 434 <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 435 <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 436 <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; 437 msi-map = <0xc000 &gic_its 0xc000 0x4000>; 438 status = "disabled"; 439 }; 440 441 pcie_x4_rc: pcie@a070000 { 442 compatible = "cix,sky1-pcie-host"; 443 reg = <0x00 0x0a070000 0x00 0x10000>, 444 <0x00 0x29000000 0x00 0x3000000>, 445 <0x00 0x0a060300 0x00 0x40>, 446 <0x00 0x0a060400 0x00 0x40>, 447 <0x00 0x50000000 0x00 0x00100000>; 448 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 449 ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, 450 <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, 451 <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; 452 #address-cells = <3>; 453 #size-cells = <2>; 454 bus-range = <0x90 0xbf>; 455 device_type = "pci"; 456 #interrupt-cells = <1>; 457 interrupt-map-mask = <0 0 0 0x7>; 458 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, 459 <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 460 <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 461 <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; 462 msi-map = <0x9000 &gic_its 0x9000 0x3000>; 463 status = "disabled"; 464 }; 465 466 pcie_x2_rc: pcie@a0c0000 { 467 compatible = "cix,sky1-pcie-host"; 468 reg = <0x00 0x0a0c0000 0x00 0x10000>, 469 <0x00 0x26000000 0x00 0x3000000>, 470 <0x00 0x0a0600340 0x00 0x20>, 471 <0x00 0x0a0600440 0x00 0x20>, 472 <0x00 0x40000000 0x00 0x00100000>; 473 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 474 ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, 475 <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, 476 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; 477 #address-cells = <3>; 478 #size-cells = <2>; 479 bus-range = <0x60 0x8f>; 480 device_type = "pci"; 481 #interrupt-cells = <1>; 482 interrupt-map-mask = <0 0 0 0x7>; 483 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, 484 <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, 485 <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, 486 <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; 487 msi-map = <0x6000 &gic_its 0x6000 0x3000>; 488 status = "disabled"; 489 }; 490 491 pcie_x1_0_rc: pcie@a0d0000 { 492 compatible = "cix,sky1-pcie-host"; 493 reg = <0x00 0x0a0d0000 0x00 0x10000>, 494 <0x00 0x20000000 0x00 0x3000000>, 495 <0x00 0x0a060360 0x00 0x20>, 496 <0x00 0x0a060460 0x00 0x20>, 497 <0x00 0x30000000 0x00 0x00100000>; 498 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 499 ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, 500 <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, 501 <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; 502 #address-cells = <3>; 503 #size-cells = <2>; 504 bus-range = <0x00 0x2f>; 505 device_type = "pci"; 506 #interrupt-cells = <1>; 507 interrupt-map-mask = <0 0 0 0x7>; 508 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, 509 <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, 510 <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 511 <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; 512 msi-map = <0x0000 &gic_its 0x0000 0x3000>; 513 status = "disabled"; 514 }; 515 516 pcie_x1_1_rc: pcie@a0e0000 { 517 compatible = "cix,sky1-pcie-host"; 518 reg = <0x00 0x0a0e0000 0x00 0x10000>, 519 <0x00 0x23000000 0x00 0x3000000>, 520 <0x00 0x0a060380 0x00 0x20>, 521 <0x00 0x0a060480 0x00 0x20>, 522 <0x00 0x38000000 0x00 0x00100000>; 523 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 524 ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, 525 <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, 526 <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; 527 #address-cells = <3>; 528 #size-cells = <2>; 529 bus-range = <0x30 0x5f>; 530 device_type = "pci"; 531 532 #interrupt-cells = <1>; 533 interrupt-map-mask = <0 0 0 0x7>; 534 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, 535 <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, 536 <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, 537 <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; 538 msi-map = <0x3000 &gic_its 0x3000 0x3000>; 539 status = "disabled"; 540 }; 541 542 gic: interrupt-controller@e010000 { 543 compatible = "arm,gic-v3"; 544 reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ 545 <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ 546 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 547 #interrupt-cells = <4>; 548 interrupt-controller; 549 #address-cells = <2>; 550 #size-cells = <2>; 551 ranges; 552 553 gic_its: msi-controller@e050000 { 554 compatible = "arm,gic-v3-its"; 555 reg = <0x0 0x0e050000 0x0 0x30000>; 556 msi-controller; 557 #msi-cells = <1>; 558 }; 559 560 ppi-partitions { 561 ppi_partition0: interrupt-partition-0 { 562 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 563 }; 564 565 ppi_partition1: interrupt-partition-1 { 566 affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>; 567 }; 568 }; 569 }; 570 571 iomuxc_s5: pinctrl@16007000 { 572 compatible = "cix,sky1-pinctrl-s5"; 573 reg = <0x0 0x16007000 0x0 0x1000>; 574 }; 575 }; 576 577 timer { 578 compatible = "arm,armv8-timer"; 579 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 580 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 581 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 582 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 583 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>, 584 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 585 }; 586}; 587