1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright 2025 Cix Technology Group Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/cix,sky1.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a520"; 21 enable-method = "psci"; 22 reg = <0x0 0x0>; 23 device_type = "cpu"; 24 capacity-dmips-mhz = <403>; 25 }; 26 27 cpu1: cpu@100 { 28 compatible = "arm,cortex-a520"; 29 enable-method = "psci"; 30 reg = <0x0 0x100>; 31 device_type = "cpu"; 32 capacity-dmips-mhz = <403>; 33 }; 34 35 cpu2: cpu@200 { 36 compatible = "arm,cortex-a520"; 37 enable-method = "psci"; 38 reg = <0x0 0x200>; 39 device_type = "cpu"; 40 capacity-dmips-mhz = <403>; 41 }; 42 43 cpu3: cpu@300 { 44 compatible = "arm,cortex-a520"; 45 enable-method = "psci"; 46 reg = <0x0 0x300>; 47 device_type = "cpu"; 48 capacity-dmips-mhz = <403>; 49 }; 50 51 cpu4: cpu@400 { 52 compatible = "arm,cortex-a720"; 53 enable-method = "psci"; 54 reg = <0x0 0x400>; 55 device_type = "cpu"; 56 capacity-dmips-mhz = <1024>; 57 }; 58 59 cpu5: cpu@500 { 60 compatible = "arm,cortex-a720"; 61 enable-method = "psci"; 62 reg = <0x0 0x500>; 63 device_type = "cpu"; 64 capacity-dmips-mhz = <1024>; 65 }; 66 67 cpu6: cpu@600 { 68 compatible = "arm,cortex-a720"; 69 enable-method = "psci"; 70 reg = <0x0 0x600>; 71 device_type = "cpu"; 72 capacity-dmips-mhz = <1024>; 73 }; 74 75 cpu7: cpu@700 { 76 compatible = "arm,cortex-a720"; 77 enable-method = "psci"; 78 reg = <0x0 0x700>; 79 device_type = "cpu"; 80 capacity-dmips-mhz = <1024>; 81 }; 82 83 cpu8: cpu@800 { 84 compatible = "arm,cortex-a720"; 85 enable-method = "psci"; 86 reg = <0x0 0x800>; 87 device_type = "cpu"; 88 capacity-dmips-mhz = <1024>; 89 }; 90 91 cpu9: cpu@900 { 92 compatible = "arm,cortex-a720"; 93 enable-method = "psci"; 94 reg = <0x0 0x900>; 95 device_type = "cpu"; 96 capacity-dmips-mhz = <1024>; 97 }; 98 99 cpu10: cpu@a00 { 100 compatible = "arm,cortex-a720"; 101 enable-method = "psci"; 102 reg = <0x0 0xa00>; 103 device_type = "cpu"; 104 capacity-dmips-mhz = <1024>; 105 }; 106 107 cpu11: cpu@b00 { 108 compatible = "arm,cortex-a720"; 109 enable-method = "psci"; 110 reg = <0x0 0xb00>; 111 device_type = "cpu"; 112 capacity-dmips-mhz = <1024>; 113 }; 114 115 cpu-map { 116 cluster0 { 117 core0 { 118 cpu = <&cpu0>; 119 }; 120 core1 { 121 cpu = <&cpu1>; 122 }; 123 core2 { 124 cpu = <&cpu2>; 125 }; 126 core3 { 127 cpu = <&cpu3>; 128 }; 129 core4 { 130 cpu = <&cpu4>; 131 }; 132 core5 { 133 cpu = <&cpu5>; 134 }; 135 core6 { 136 cpu = <&cpu6>; 137 }; 138 core7 { 139 cpu = <&cpu7>; 140 }; 141 core8 { 142 cpu = <&cpu8>; 143 }; 144 core9 { 145 cpu = <&cpu9>; 146 }; 147 core10 { 148 cpu = <&cpu10>; 149 }; 150 core11 { 151 cpu = <&cpu11>; 152 }; 153 }; 154 }; 155 }; 156 157 firmware { 158 ap_to_pm_scmi: scmi { 159 compatible = "arm,scmi"; 160 mbox-names = "tx", "rx"; 161 mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>; 162 shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 scmi_clk: protocol@14 { 167 reg = <0x14>; 168 #clock-cells = <1>; 169 }; 170 }; 171 }; 172 173 pmu-a520 { 174 compatible = "arm,cortex-a520-pmu"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>; 176 }; 177 178 pmu-a720 { 179 compatible = "arm,cortex-a720-pmu"; 180 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>; 181 }; 182 183 psci { 184 compatible = "arm,psci-1.0"; 185 method = "smc"; 186 }; 187 188 soc@0 { 189 compatible = "simple-bus"; 190 ranges = <0 0 0 0 0x20 0>; 191 dma-ranges; 192 #address-cells = <2>; 193 #size-cells = <2>; 194 195 i2c0: i2c@4010000 { 196 compatible = "cdns,i2c-r1p14"; 197 reg = <0x0 0x04010000 0x0 0x10000>; 198 clock-frequency = <400000>; 199 clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>; 200 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>; 201 status = "disabled"; 202 }; 203 204 i2c1: i2c@4020000 { 205 compatible = "cdns,i2c-r1p14"; 206 reg = <0x0 0x04020000 0x0 0x10000>; 207 clock-frequency = <400000>; 208 clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>; 209 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0>; 210 status = "disabled"; 211 }; 212 213 i2c2: i2c@4030000 { 214 compatible = "cdns,i2c-r1p14"; 215 reg = <0x0 0x04030000 0x0 0x10000>; 216 clock-frequency = <400000>; 217 clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>; 218 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>; 219 status = "disabled"; 220 }; 221 222 i2c3: i2c@4040000 { 223 compatible = "cdns,i2c-r1p14"; 224 reg = <0x0 0x04040000 0x0 0x10000>; 225 clock-frequency = <400000>; 226 clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>; 227 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 228 status = "disabled"; 229 }; 230 231 i2c4: i2c@4050000 { 232 compatible = "cdns,i2c-r1p14"; 233 reg = <0x0 0x04050000 0x0 0x10000>; 234 clock-frequency = <400000>; 235 clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>; 236 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>; 237 status = "disabled"; 238 }; 239 240 i2c5: i2c@4060000 { 241 compatible = "cdns,i2c-r1p14"; 242 reg = <0x0 0x04060000 0x0 0x10000>; 243 clock-frequency = <400000>; 244 clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>; 245 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>; 246 status = "disabled"; 247 }; 248 249 i2c6: i2c@4070000 { 250 compatible = "cdns,i2c-r1p14"; 251 reg = <0x0 0x04070000 0x0 0x10000>; 252 clock-frequency = <400000>; 253 clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>; 254 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0>; 255 status = "disabled"; 256 }; 257 258 i2c7: i2c@4080000 { 259 compatible = "cdns,i2c-r1p14"; 260 reg = <0x0 0x04080000 0x0 0x10000>; 261 clock-frequency = <400000>; 262 clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>; 263 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 264 status = "disabled"; 265 }; 266 267 uart0: serial@40b0000 { 268 compatible = "arm,pl011", "arm,primecell"; 269 reg = <0x0 0x040b0000 0x0 0x1000>; 270 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>; 271 clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>; 272 clock-names = "uartclk", "apb_pclk"; 273 status = "disabled"; 274 }; 275 276 uart1: serial@40c0000 { 277 compatible = "arm,pl011", "arm,primecell"; 278 reg = <0x0 0x040c0000 0x0 0x1000>; 279 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 280 clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>; 281 clock-names = "uartclk", "apb_pclk"; 282 status = "disabled"; 283 }; 284 285 uart2: serial@40d0000 { 286 compatible = "arm,pl011", "arm,primecell"; 287 reg = <0x0 0x040d0000 0x0 0x1000>; 288 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 289 clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>; 290 clock-names = "uartclk", "apb_pclk"; 291 status = "disabled"; 292 }; 293 294 uart3: serial@40e0000 { 295 compatible = "arm,pl011", "arm,primecell"; 296 reg = <0x0 0x040e0000 0x0 0x1000>; 297 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 298 clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>; 299 clock-names = "uartclk", "apb_pclk"; 300 status = "disabled"; 301 }; 302 303 i3c0: i3c@40f0000 { 304 compatible = "cdns,i3c-master"; 305 reg = <0x0 0x040f0000 0x0 0x10000>; 306 #address-cells = <3>; 307 #size-cells = <0>; 308 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 309 clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>, 310 <&scmi_clk CLK_TREE_FCH_I3C0_FUNC>; 311 clock-names = "pclk", "sysclk"; 312 i3c-scl-hz = <400000>; 313 i2c-scl-hz = <100000>; 314 status = "disabled"; 315 }; 316 317 i3c1: i3c@4100000 { 318 compatible = "cdns,i3c-master"; 319 reg = <0x0 0x04100000 0x0 0x10000>; 320 #address-cells = <3>; 321 #size-cells = <0>; 322 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 323 clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>, 324 <&scmi_clk CLK_TREE_FCH_I3C1_FUNC>; 325 clock-names = "pclk", "sysclk"; 326 i3c-scl-hz = <400000>; 327 i2c-scl-hz = <100000>; 328 status = "disabled"; 329 }; 330 331 mbox_ap2se: mailbox@5060000 { 332 compatible = "cix,sky1-mbox"; 333 reg = <0x0 0x05060000 0x0 0x10000>; 334 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>; 335 #mbox-cells = <1>; 336 cix,mbox-dir = "tx"; 337 }; 338 339 mbox_se2ap: mailbox@5070000 { 340 compatible = "cix,sky1-mbox"; 341 reg = <0x0 0x05070000 0x0 0x10000>; 342 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 343 #mbox-cells = <1>; 344 cix,mbox-dir = "rx"; 345 }; 346 347 ap2pm_scmi_mem: shmem@6590000 { 348 compatible = "arm,scmi-shmem"; 349 reg = <0x0 0x06590000 0x0 0x80>; 350 reg-io-width = <4>; 351 }; 352 353 mbox_ap2pm: mailbox@6590080 { 354 compatible = "cix,sky1-mbox"; 355 reg = <0x0 0x06590080 0x0 0xff80>; 356 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 357 #mbox-cells = <1>; 358 cix,mbox-dir = "tx"; 359 }; 360 361 pm2ap_scmi_mem: shmem@65a0000 { 362 compatible = "arm,scmi-shmem"; 363 reg = <0x0 0x065a0000 0x0 0x80>; 364 reg-io-width = <4>; 365 }; 366 367 mbox_pm2ap: mailbox@65a0080 { 368 compatible = "cix,sky1-mbox"; 369 reg = <0x0 0x065a0080 0x0 0xff80>; 370 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>; 371 #mbox-cells = <1>; 372 cix,mbox-dir = "rx"; 373 }; 374 375 mbox_sfh2ap: mailbox@8090000 { 376 compatible = "cix,sky1-mbox"; 377 reg = <0x0 0x08090000 0x0 0x10000>; 378 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 379 #mbox-cells = <1>; 380 cix,mbox-dir = "rx"; 381 }; 382 383 mbox_ap2sfh: mailbox@80a0000 { 384 compatible = "cix,sky1-mbox"; 385 reg = <0x0 0x080a0000 0x0 0x10000>; 386 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 387 #mbox-cells = <1>; 388 cix,mbox-dir = "tx"; 389 }; 390 391 gic: interrupt-controller@e010000 { 392 compatible = "arm,gic-v3"; 393 reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ 394 <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ 395 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 396 #interrupt-cells = <4>; 397 interrupt-controller; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 402 gic_its: msi-controller@e050000 { 403 compatible = "arm,gic-v3-its"; 404 reg = <0x0 0x0e050000 0x0 0x30000>; 405 msi-controller; 406 #msi-cells = <1>; 407 }; 408 409 ppi-partitions { 410 ppi_partition0: interrupt-partition-0 { 411 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 412 }; 413 414 ppi_partition1: interrupt-partition-1 { 415 affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>; 416 }; 417 }; 418 }; 419 }; 420 421 timer { 422 compatible = "arm,armv8-timer"; 423 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 424 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 425 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 426 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 427 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>, 428 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 429 }; 430}; 431