1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015-2017 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/clock/bcm-sr.h> 34#include <dt-bindings/interrupt-controller/arm-gic.h> 35 36/ { 37 compatible = "brcm,stingray"; 38 interrupt-parent = <&gic>; 39 #address-cells = <2>; 40 #size-cells = <2>; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a72"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 next-level-cache = <&CLUSTER0_L2>; 52 }; 53 54 cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a72"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 next-level-cache = <&CLUSTER0_L2>; 60 }; 61 62 cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a72"; 65 reg = <0x0 0x100>; 66 enable-method = "psci"; 67 next-level-cache = <&CLUSTER1_L2>; 68 }; 69 70 cpu@101 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a72"; 73 reg = <0x0 0x101>; 74 enable-method = "psci"; 75 next-level-cache = <&CLUSTER1_L2>; 76 }; 77 78 cpu@200 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 reg = <0x0 0x200>; 82 enable-method = "psci"; 83 next-level-cache = <&CLUSTER2_L2>; 84 }; 85 86 cpu@201 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a72"; 89 reg = <0x0 0x201>; 90 enable-method = "psci"; 91 next-level-cache = <&CLUSTER2_L2>; 92 }; 93 94 cpu@300 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a72"; 97 reg = <0x0 0x300>; 98 enable-method = "psci"; 99 next-level-cache = <&CLUSTER3_L2>; 100 }; 101 102 cpu@301 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a72"; 105 reg = <0x0 0x301>; 106 enable-method = "psci"; 107 next-level-cache = <&CLUSTER3_L2>; 108 }; 109 110 CLUSTER0_L2: l2-cache@0 { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 }; 115 116 CLUSTER1_L2: l2-cache@100 { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 }; 121 122 CLUSTER2_L2: l2-cache@200 { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 }; 127 128 CLUSTER3_L2: l2-cache@300 { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 }; 133 }; 134 135 memory: memory@80000000 { 136 device_type = "memory"; 137 reg = <0x00000000 0x80000000 0 0x40000000>; 138 }; 139 140 psci { 141 compatible = "arm,psci-0.2"; 142 method = "smc"; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a72-pmu"; 147 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 153 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 154 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 155 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 156 }; 157 158 mhb: syscon@60401000 { 159 compatible = "brcm,sr-mhb", "syscon"; 160 reg = <0 0x60401000 0 0x38c>; 161 }; 162 163 osc: clock-50000000 { 164 #clock-cells = <0>; 165 compatible = "fixed-clock"; 166 clock-frequency = <50000000>; 167 }; 168 169 crmu_ref25m: hsls_25m_clk: clock-25000000 { 170 #clock-cells = <0>; 171 compatible = "fixed-factor-clock"; 172 clocks = <&osc>; 173 clock-div = <2>; 174 clock-mult = <1>; 175 }; 176 177 hsls_div2_clk: hsls_div2_clk { 178 #clock-cells = <0>; 179 compatible = "fixed-factor-clock"; 180 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; 181 clock-div = <2>; 182 clock-mult = <1>; 183 184 }; 185 186 hsls_div4_clk: hsls_div4_clk { 187 #clock-cells = <0>; 188 compatible = "fixed-factor-clock"; 189 clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; 190 clock-div = <4>; 191 clock-mult = <1>; 192 }; 193 194 hsls_25m_div2_clk: clock-12500000 { 195 #clock-cells = <0>; 196 compatible = "fixed-factor-clock"; 197 clocks = <&hsls_25m_clk>; 198 clock-div = <2>; 199 clock-mult = <1>; 200 }; 201 202 scr-bus@61000000 { 203 compatible = "simple-bus"; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges = <0x0 0x0 0x61000000 0x05000000>; 207 208 ccn: ccn@0 { 209 compatible = "arm,ccn-502"; 210 reg = <0x00000000 0x900000>; 211 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 212 }; 213 214 gic: interrupt-controller@2c00000 { 215 compatible = "arm,gic-v3"; 216 #interrupt-cells = <3>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 ranges; 220 interrupt-controller; 221 reg = <0x02c00000 0x010000>, /* GICD */ 222 <0x02e00000 0x600000>; /* GICR */ 223 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 224 225 gic_its: msi-controller@63c20000 { 226 compatible = "arm,gic-v3-its"; 227 msi-controller; 228 #msi-cells = <1>; 229 reg = <0x02c20000 0x10000>; 230 }; 231 }; 232 233 smmu: iommu@3000000 { 234 compatible = "arm,mmu-500"; 235 reg = <0x03000000 0x80000>; 236 #global-interrupts = <1>; 237 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; 302 #iommu-cells = <2>; 303 }; 304 }; 305 306 crmu: crmu-bus@66400000 { 307 compatible = "simple-bus"; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0x0 0x0 0x66400000 0x100000>; 311 312 otp: otp@1c400 { 313 compatible = "brcm,ocotp-v2"; 314 reg = <0x0001c400 0x68>; 315 brcm,ocotp-size = <2048>; 316 status = "okay"; 317 }; 318 319 cdru: syscon@1d000 { 320 compatible = "brcm,sr-cdru", "syscon"; 321 reg = <0x0001d000 0x400>; 322 }; 323 324 lcpll0: clock-controller@1d0c4 { 325 #clock-cells = <1>; 326 compatible = "brcm,sr-lcpll0"; 327 reg = <0x0001d0c4 0x3c>, 328 <0x0001c870 0x4>; 329 clocks = <&osc>; 330 clock-output-names = "lcpll0", "clk_sata_refp", 331 "clk_sata_refn", "clk_sata_350", 332 "clk_sata_500"; 333 }; 334 335 genpll0: clock-controller@1d104 { 336 #clock-cells = <1>; 337 compatible = "brcm,sr-genpll0"; 338 reg = <0x0001d104 0x32>, 339 <0x0001c854 0x4>; 340 clocks = <&osc>; 341 clock-output-names = "genpll0", "clk_125m", "clk_scr", 342 "clk_250", "clk_pcie_axi", 343 "clk_paxc_axi_x2", 344 "clk_paxc_axi"; 345 }; 346 347 lcpll1: clock-controller@1d138 { 348 #clock-cells = <1>; 349 compatible = "brcm,sr-lcpll1"; 350 reg = <0x0001d138 0x3c>, 351 <0x0001c870 0x4>; 352 clocks = <&osc>; 353 clock-output-names = "lcpll1", "clk_wan", 354 "clk_usb_ref", 355 "clk_crmu_ts"; 356 }; 357 358 genpll2: clock-controller@1d1ac { 359 #clock-cells = <1>; 360 compatible = "brcm,sr-genpll2"; 361 reg = <0x0001d1ac 0x32>, 362 <0x0001c854 0x4>; 363 clocks = <&osc>; 364 clock-output-names = "genpll2", "clk_nic", 365 "clk_ts_500_ref", "clk_125_nitro", 366 "clk_chimp", "clk_nic_flash", 367 "clk_fs"; 368 }; 369 370 genpll3: clock-controller@1d1e0 { 371 #clock-cells = <1>; 372 compatible = "brcm,sr-genpll3"; 373 reg = <0x0001d1e0 0x32>, 374 <0x0001c854 0x4>; 375 clocks = <&osc>; 376 clock-output-names = "genpll3", "clk_hsls", 377 "clk_sdio"; 378 }; 379 380 genpll4: clock-controller@1d214 { 381 #clock-cells = <1>; 382 compatible = "brcm,sr-genpll4"; 383 reg = <0x0001d214 0x32>, 384 <0x0001c854 0x4>; 385 clocks = <&osc>; 386 clock-output-names = "genpll4", "clk_ccn", 387 "clk_tpiu_pll", "clk_noc", 388 "clk_chclk_fs4", 389 "clk_bridge_fscpu"; 390 }; 391 392 genpll5: clock-controller@1d248 { 393 #clock-cells = <1>; 394 compatible = "brcm,sr-genpll5"; 395 reg = <0x0001d248 0x32>, 396 <0x0001c870 0x4>; 397 clocks = <&osc>; 398 clock-output-names = "genpll5", "clk_fs4_hf", 399 "clk_crypto_ae", "clk_raid_ae"; 400 }; 401 402 gpio_crmu: gpio@24800 { 403 compatible = "brcm,iproc-gpio"; 404 reg = <0x00024800 0x4c>; 405 ngpios = <6>; 406 #gpio-cells = <2>; 407 gpio-controller; 408 }; 409 }; 410 411 #include "stingray-fs4.dtsi" 412 #include "stingray-pcie.dtsi" 413 #include "stingray-usb.dtsi" 414 415 hsls-bus@68900000 { 416 compatible = "simple-bus"; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 ranges = <0x0 0x0 0x68900000 0x17700000>; 420 421 #include "stingray-pinctrl.dtsi" 422 423 mdio_mux_iproc: mdio-mux@20000 { 424 compatible = "brcm,mdio-mux-iproc"; 425 reg = <0x00020000 0x250>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 mdio@0 { /* PCIe serdes */ 430 reg = <0x0>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 }; 434 435 mdio@3 { /* USB */ 436 reg = <0x3>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 }; 440 441 mdio@10 { /* RGMII */ 442 reg = <0x10>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 }; 446 }; 447 448 pwm: pwm@10000 { 449 compatible = "brcm,iproc-pwm"; 450 reg = <0x00010000 0x1000>; 451 clocks = <&crmu_ref25m>; 452 #pwm-cells = <3>; 453 status = "disabled"; 454 }; 455 456 timer0: timer@30000 { 457 compatible = "arm,sp804", "arm,primecell"; 458 reg = <0x00030000 0x1000>; 459 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&hsls_25m_div2_clk>, 461 <&hsls_25m_div2_clk>, 462 <&hsls_div4_clk>; 463 clock-names = "timer1", "timer2", "apb_pclk"; 464 status = "disabled"; 465 }; 466 467 timer1: timer@40000 { 468 compatible = "arm,sp804", "arm,primecell"; 469 reg = <0x00040000 0x1000>; 470 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&hsls_25m_div2_clk>, 472 <&hsls_25m_div2_clk>, 473 <&hsls_div4_clk>; 474 clock-names = "timer1", "timer2", "apb_pclk"; 475 }; 476 477 timer2: timer@50000 { 478 compatible = "arm,sp804", "arm,primecell"; 479 reg = <0x00050000 0x1000>; 480 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&hsls_25m_div2_clk>, 482 <&hsls_25m_div2_clk>, 483 <&hsls_div4_clk>; 484 clock-names = "timer1", "timer2", "apb_pclk"; 485 status = "disabled"; 486 }; 487 488 timer3: timer@60000 { 489 compatible = "arm,sp804", "arm,primecell"; 490 reg = <0x00060000 0x1000>; 491 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&hsls_25m_div2_clk>, 493 <&hsls_25m_div2_clk>, 494 <&hsls_div4_clk>; 495 clock-names = "timer1", "timer2", "apb_pclk"; 496 status = "disabled"; 497 }; 498 499 timer4: timer@70000 { 500 compatible = "arm,sp804", "arm,primecell"; 501 reg = <0x00070000 0x1000>; 502 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&hsls_25m_div2_clk>, 504 <&hsls_25m_div2_clk>, 505 <&hsls_div4_clk>; 506 clock-names = "timer1", "timer2", "apb_pclk"; 507 status = "disabled"; 508 }; 509 510 timer5: timer@80000 { 511 compatible = "arm,sp804", "arm,primecell"; 512 reg = <0x00080000 0x1000>; 513 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&hsls_25m_div2_clk>, 515 <&hsls_25m_div2_clk>, 516 <&hsls_div4_clk>; 517 clock-names = "timer1", "timer2", "apb_pclk"; 518 status = "disabled"; 519 }; 520 521 timer6: timer@90000 { 522 compatible = "arm,sp804", "arm,primecell"; 523 reg = <0x00090000 0x1000>; 524 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&hsls_25m_div2_clk>, 526 <&hsls_25m_div2_clk>, 527 <&hsls_div4_clk>; 528 clock-names = "timer1", "timer2", "apb_pclk"; 529 status = "disabled"; 530 }; 531 532 timer7: timer@a0000 { 533 compatible = "arm,sp804", "arm,primecell"; 534 reg = <0x000a0000 0x1000>; 535 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&hsls_25m_div2_clk>, 537 <&hsls_25m_div2_clk>, 538 <&hsls_div4_clk>; 539 clock-names = "timer1", "timer2", "apb_pclk"; 540 status = "disabled"; 541 }; 542 543 i2c0: i2c@b0000 { 544 compatible = "brcm,iproc-i2c"; 545 reg = <0x000b0000 0x100>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 549 clock-frequency = <100000>; 550 status = "disabled"; 551 }; 552 553 wdt0: watchdog@c0000 { 554 compatible = "arm,sp805", "arm,primecell"; 555 reg = <0x000c0000 0x1000>; 556 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; 558 clock-names = "wdog_clk", "apb_pclk"; 559 timeout-sec = <60>; 560 }; 561 562 gpio_hsls: gpio@d0000 { 563 compatible = "brcm,iproc-gpio"; 564 reg = <0x000d0000 0x864>; 565 ngpios = <151>; 566 #gpio-cells = <2>; 567 gpio-controller; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 571 gpio-ranges = <&pinmux 0 0 16>, 572 <&pinmux 16 71 2>, 573 <&pinmux 18 131 8>, 574 <&pinmux 26 83 6>, 575 <&pinmux 32 123 4>, 576 <&pinmux 36 43 24>, 577 <&pinmux 60 89 2>, 578 <&pinmux 62 73 4>, 579 <&pinmux 66 95 28>, 580 <&pinmux 94 127 4>, 581 <&pinmux 98 139 10>, 582 <&pinmux 108 16 27>, 583 <&pinmux 135 77 6>, 584 <&pinmux 141 67 4>, 585 <&pinmux 145 149 6>; 586 }; 587 588 i2c1: i2c@e0000 { 589 compatible = "brcm,iproc-i2c"; 590 reg = <0x000e0000 0x100>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 594 clock-frequency = <100000>; 595 status = "disabled"; 596 }; 597 598 uart0: serial@100000 { 599 compatible = "snps,dw-apb-uart"; 600 reg = <0x00100000 0x1000>; 601 reg-shift = <2>; 602 clock-frequency = <25000000>; 603 interrupt-parent = <&gic>; 604 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 605 status = "disabled"; 606 }; 607 608 uart1: serial@110000 { 609 compatible = "snps,dw-apb-uart"; 610 reg = <0x00110000 0x1000>; 611 reg-shift = <2>; 612 clock-frequency = <25000000>; 613 interrupt-parent = <&gic>; 614 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 615 status = "disabled"; 616 }; 617 618 uart2: serial@120000 { 619 compatible = "snps,dw-apb-uart"; 620 reg = <0x00120000 0x1000>; 621 reg-shift = <2>; 622 clock-frequency = <25000000>; 623 interrupt-parent = <&gic>; 624 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 625 status = "disabled"; 626 }; 627 628 uart3: serial@130000 { 629 compatible = "snps,dw-apb-uart"; 630 reg = <0x00130000 0x1000>; 631 reg-shift = <2>; 632 clock-frequency = <25000000>; 633 interrupt-parent = <&gic>; 634 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 635 status = "disabled"; 636 }; 637 638 ssp0: spi@180000 { 639 compatible = "arm,pl022", "arm,primecell"; 640 reg = <0x00180000 0x1000>; 641 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 643 clock-names = "sspclk", "apb_pclk"; 644 num-cs = <1>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 status = "disabled"; 648 }; 649 650 ssp1: spi@190000 { 651 compatible = "arm,pl022", "arm,primecell"; 652 reg = <0x00190000 0x1000>; 653 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 655 clock-names = "sspclk", "apb_pclk"; 656 num-cs = <1>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 hwrng: hwrng@220000 { 663 compatible = "brcm,iproc-rng200"; 664 reg = <0x00220000 0x28>; 665 }; 666 667 dma0: dma-controller@310000 { 668 compatible = "arm,pl330", "arm,primecell"; 669 reg = <0x00310000 0x1000>; 670 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 679 #dma-cells = <1>; 680 clocks = <&hsls_div2_clk>; 681 clock-names = "apb_pclk"; 682 iommus = <&smmu 0x6000 0x0000>; 683 }; 684 685 enet: ethernet@340000 { 686 compatible = "brcm,amac"; 687 reg = <0x00340000 0x1000>; 688 reg-names = "amac_base"; 689 dma-coherent; 690 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 691 status = "disabled"; 692 }; 693 694 nand: nand-controller@360000 { 695 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 696 reg = <0x00360000 0x600>, 697 <0x0050a408 0x600>, 698 <0x00360f00 0x20>; 699 reg-names = "nand", "iproc-idm", "iproc-ext"; 700 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 brcm,nand-has-wp; 704 status = "disabled"; 705 }; 706 707 sdio0: mmc@3f1000 { 708 compatible = "brcm,sdhci-iproc"; 709 reg = <0x003f1000 0x100>; 710 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 711 bus-width = <8>; 712 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; 713 iommus = <&smmu 0x6002 0x0000>; 714 status = "disabled"; 715 }; 716 717 sdio1: mmc@3f2000 { 718 compatible = "brcm,sdhci-iproc"; 719 reg = <0x003f2000 0x100>; 720 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 721 bus-width = <8>; 722 clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; 723 iommus = <&smmu 0x6003 0x0000>; 724 status = "disabled"; 725 }; 726 }; 727 728 tmons-bus@8f100000 { 729 compatible = "simple-bus"; 730 #address-cells = <1>; 731 #size-cells = <1>; 732 ranges = <0x0 0x0 0x8f100000 0x100>; 733 734 tmon: tmon@0 { 735 compatible = "brcm,sr-thermal"; 736 reg = <0x0 0x40>; 737 brcm,tmon-mask = <0x3f>; 738 #thermal-sensor-cells = <1>; 739 }; 740 }; 741 742 thermal-zones { 743 ihost0_thermal: ihost0-thermal { 744 polling-delay-passive = <0>; 745 polling-delay = <1000>; 746 thermal-sensors = <&tmon 0>; 747 trips { 748 cpu-crit { 749 temperature = <105000>; 750 hysteresis = <0>; 751 type = "critical"; 752 }; 753 }; 754 }; 755 ihost1_thermal: ihost1-thermal { 756 polling-delay-passive = <0>; 757 polling-delay = <1000>; 758 thermal-sensors = <&tmon 1>; 759 trips { 760 cpu-crit { 761 temperature = <105000>; 762 hysteresis = <0>; 763 type = "critical"; 764 }; 765 }; 766 }; 767 ihost2_thermal: ihost2-thermal { 768 polling-delay-passive = <0>; 769 polling-delay = <1000>; 770 thermal-sensors = <&tmon 2>; 771 trips { 772 cpu-crit { 773 temperature = <105000>; 774 hysteresis = <0>; 775 type = "critical"; 776 }; 777 }; 778 }; 779 ihost3_thermal: ihost3-thermal { 780 polling-delay-passive = <0>; 781 polling-delay = <1000>; 782 thermal-sensors = <&tmon 3>; 783 trips { 784 cpu-crit { 785 temperature = <105000>; 786 hysteresis = <0>; 787 type = "critical"; 788 }; 789 }; 790 }; 791 crmu_thermal: crmu-thermal { 792 polling-delay-passive = <0>; 793 polling-delay = <1000>; 794 thermal-sensors = <&tmon 4>; 795 trips { 796 cpu-crit { 797 temperature = <105000>; 798 hysteresis = <0>; 799 type = "critical"; 800 }; 801 }; 802 }; 803 nitro_thermal: nitro-thermal { 804 polling-delay-passive = <0>; 805 polling-delay = <1000>; 806 thermal-sensors = <&tmon 5>; 807 trips { 808 cpu-crit { 809 temperature = <105000>; 810 hysteresis = <0>; 811 type = "critical"; 812 }; 813 }; 814 }; 815 }; 816 817 nic-hsls-bus@60800000 { 818 compatible = "simple-bus"; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 ranges = <0x0 0x0 0x60800000 0x6fffff>; 822 823 nic_i2c0: i2c@26100 { 824 compatible = "brcm,iproc-nic-i2c"; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 reg = <0x026100 0x100>, 828 <0x600408 0x1000>; 829 brcm,ape-hsls-addr-mask = <0x03400000>; 830 clock-frequency = <100000>; 831 status = "disabled"; 832 }; 833 }; 834}; 835