1*ded8f229SWilliam Zhang// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*ded8f229SWilliam Zhang 3*ded8f229SWilliam Zhang#include "bcm4908.dtsi" 4*ded8f229SWilliam Zhang 5*ded8f229SWilliam Zhang/ { 6*ded8f229SWilliam Zhang cpus { 7*ded8f229SWilliam Zhang /delete-node/ cpu@2; 8*ded8f229SWilliam Zhang 9*ded8f229SWilliam Zhang /delete-node/ cpu@3; 10*ded8f229SWilliam Zhang }; 11*ded8f229SWilliam Zhang 12*ded8f229SWilliam Zhang timer { 13*ded8f229SWilliam Zhang compatible = "arm,armv8-timer"; 14*ded8f229SWilliam Zhang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 15*ded8f229SWilliam Zhang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 16*ded8f229SWilliam Zhang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 17*ded8f229SWilliam Zhang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 18*ded8f229SWilliam Zhang }; 19*ded8f229SWilliam Zhang 20*ded8f229SWilliam Zhang pmu { 21*ded8f229SWilliam Zhang compatible = "arm,cortex-a53-pmu"; 22*ded8f229SWilliam Zhang interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 23*ded8f229SWilliam Zhang <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 24*ded8f229SWilliam Zhang interrupt-affinity = <&cpu0>, <&cpu1>; 25*ded8f229SWilliam Zhang }; 26*ded8f229SWilliam Zhang}; 27