1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/soc/bcm2835-pm.h> 4 5/ { 6 compatible = "brcm,bcm2712"; 7 8 #address-cells = <2>; 9 #size-cells = <2>; 10 11 interrupt-parent = <&gicv2>; 12 13 clocks { 14 /* The oscillator is the root of the clock tree. */ 15 clk_osc: clk-osc { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 clock-output-names = "osc"; 19 clock-frequency = <54000000>; 20 }; 21 22 clk_vpu: clk-vpu { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <750000000>; 26 clock-output-names = "vpu-clock"; 27 }; 28 29 clk_uart: clk-uart { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <9216000>; 33 clock-output-names = "uart-clock"; 34 }; 35 36 clk_emmc2: clk-emmc2 { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <200000000>; 40 clock-output-names = "emmc2-clock"; 41 }; 42 43 clk_sw_baud: clk-sw-baud { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <96000000>; 47 clock-output-names = "sw-baud"; 48 }; 49 }; 50 51 cpus: cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 /* Source for L1 d/i cache-line-size, cache-sets, cache-size 56 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en 57 * Source for L2 cache-line-size and cache-sets: 58 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en 59 * and for cache-size: 60 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 61 */ 62 cpu0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a76"; 65 reg = <0x000>; 66 enable-method = "psci"; 67 d-cache-size = <0x10000>; 68 d-cache-line-size = <64>; 69 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 70 i-cache-size = <0x10000>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 73 next-level-cache = <&l2_cache_l0>; 74 75 l2_cache_l0: l2-cache { 76 compatible = "cache"; 77 cache-size = <0x80000>; 78 cache-line-size = <64>; 79 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 80 cache-level = <2>; 81 cache-unified; 82 next-level-cache = <&l3_cache>; 83 }; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a76"; 89 reg = <0x100>; 90 enable-method = "psci"; 91 d-cache-size = <0x10000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 94 i-cache-size = <0x10000>; 95 i-cache-line-size = <64>; 96 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 97 next-level-cache = <&l2_cache_l1>; 98 99 l2_cache_l1: l2-cache { 100 compatible = "cache"; 101 cache-size = <0x80000>; 102 cache-line-size = <64>; 103 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 104 cache-level = <2>; 105 cache-unified; 106 next-level-cache = <&l3_cache>; 107 }; 108 }; 109 110 cpu2: cpu@2 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a76"; 113 reg = <0x200>; 114 enable-method = "psci"; 115 d-cache-size = <0x10000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 118 i-cache-size = <0x10000>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 121 next-level-cache = <&l2_cache_l2>; 122 123 l2_cache_l2: l2-cache { 124 compatible = "cache"; 125 cache-size = <0x80000>; 126 cache-line-size = <64>; 127 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&l3_cache>; 131 }; 132 }; 133 134 cpu3: cpu@3 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a76"; 137 reg = <0x300>; 138 enable-method = "psci"; 139 d-cache-size = <0x10000>; 140 d-cache-line-size = <64>; 141 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 142 i-cache-size = <0x10000>; 143 i-cache-line-size = <64>; 144 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 145 next-level-cache = <&l2_cache_l3>; 146 147 l2_cache_l3: l2-cache { 148 compatible = "cache"; 149 cache-size = <0x80000>; 150 cache-line-size = <64>; 151 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_cache>; 155 }; 156 }; 157 158 /* Source for cache-line-size and cache-sets: 159 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en 160 * Source for cache-size: 161 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 162 */ 163 l3_cache: l3-cache { 164 compatible = "cache"; 165 cache-size = <0x200000>; 166 cache-line-size = <64>; 167 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set 168 cache-level = <3>; 169 cache-unified; 170 }; 171 }; 172 173 psci { 174 method = "smc"; 175 compatible = "arm,psci-1.0", "arm,psci-0.2"; 176 }; 177 178 rmem: reserved-memory { 179 ranges; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 183 atf@0 { 184 reg = <0x0 0x0 0x0 0x80000>; 185 no-map; 186 }; 187 188 cma: linux,cma { 189 compatible = "shared-dma-pool"; 190 size = <0x0 0x4000000>; /* 64MB */ 191 reusable; 192 linux,cma-default; 193 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; 194 }; 195 }; 196 197 soc: soc@107c000000 { 198 compatible = "simple-bus"; 199 ranges = <0x00000000 0x10 0x00000000 0x80000000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 203 pcie_rescal: reset-controller@119500 { 204 compatible = "brcm,bcm7216-pcie-sata-rescal"; 205 reg = <0x00119500 0x10>; 206 #reset-cells = <0>; 207 }; 208 209 sdio1: mmc@fff000 { 210 compatible = "brcm,bcm2712-sdhci", 211 "brcm,sdhci-brcmstb"; 212 reg = <0x00fff000 0x260>, 213 <0x00fff400 0x200>; 214 reg-names = "host", "cfg"; 215 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clk_emmc2>; 217 clock-names = "sw_sdio"; 218 mmc-ddr-3_3v; 219 }; 220 221 bcm_reset: reset-controller@1504318 { 222 compatible = "brcm,brcmstb-reset"; 223 reg = <0x01504318 0x30>; 224 #reset-cells = <1>; 225 }; 226 227 system_timer: timer@7c003000 { 228 compatible = "brcm,bcm2835-system-timer"; 229 reg = <0x7c003000 0x1000>; 230 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 234 clock-frequency = <1000000>; 235 }; 236 237 mailbox: mailbox@7c013880 { 238 compatible = "brcm,bcm2835-mbox"; 239 reg = <0x7c013880 0x40>; 240 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 241 #mbox-cells = <0>; 242 }; 243 244 uart10: serial@7d001000 { 245 compatible = "arm,pl011", "arm,primecell"; 246 reg = <0x7d001000 0x200>; 247 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clk_uart>, <&clk_vpu>; 249 clock-names = "uartclk", "apb_pclk"; 250 arm,primecell-periphid = <0x00341011>; 251 status = "disabled"; 252 }; 253 254 pm: watchdog@7d200000 { 255 compatible = "brcm,bcm2712-pm", "brcm,bcm2835-pm-wdt"; 256 reg = <0x7d200000 0x604>; 257 reg-names = "pm"; 258 #power-domain-cells = <1>; 259 #reset-cells = <1>; 260 system-power-controller; 261 }; 262 263 pinctrl: pinctrl@7d504100 { 264 compatible = "brcm,bcm2712c0-pinctrl"; 265 reg = <0x7d504100 0x30>; 266 }; 267 268 gio: gpio@7d508500 { 269 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 270 reg = <0x7d508500 0x40>; 271 interrupt-parent = <&main_irq>; 272 interrupts = <0>; 273 gpio-controller; 274 #gpio-cells = <2>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 brcm,gpio-bank-widths = <32 22>; 278 }; 279 280 uarta: serial@7d50c000 { 281 compatible = "brcm,bcm7271-uart"; 282 reg = <0x7d50c000 0x20>; 283 reg-names = "uart"; 284 clocks = <&clk_sw_baud>; 285 clock-names = "sw_baud"; 286 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-names = "uart"; 288 status = "disabled"; 289 }; 290 291 pinctrl_aon: pinctrl@7d510700 { 292 compatible = "brcm,bcm2712c0-aon-pinctrl"; 293 reg = <0x7d510700 0x20>; 294 }; 295 296 random: rng@7d208000 { 297 compatible = "brcm,bcm2711-rng200"; 298 reg = <0x7d208000 0x28>; 299 status = "okay"; 300 }; 301 302 interrupt-controller@7d517000 { 303 compatible = "brcm,bcm7271-l2-intc"; 304 reg = <0x7d517000 0x10>; 305 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-controller; 307 #interrupt-cells = <1>; 308 }; 309 310 gio_aon: gpio@7d517c00 { 311 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 312 reg = <0x7d517c00 0x40>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 brcm,gpio-bank-widths = <17 6>; 316 /* The lack of 'interrupt-controller' property here is intended: 317 * don't use GIO_AON as an interrupt controller because it will 318 * clash with the firmware monitoring the PMIC interrupt via the VPU. 319 */ 320 }; 321 322 sdio2: mmc@1100000 { 323 compatible = "brcm,bcm2712-sdhci", 324 "brcm,sdhci-brcmstb"; 325 reg = <0x01100000 0x260>, 326 <0x01100400 0x200>; 327 reg-names = "host", "cfg"; 328 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&clk_emmc2>; 330 clock-names = "sw_sdio"; 331 sdhci-caps-mask = <0x0000C000 0x0>; 332 sdhci-caps = <0x0 0x0>; 333 mmc-ddr-3_3v; 334 status = "disabled"; 335 }; 336 337 gicv2: interrupt-controller@7fff9000 { 338 compatible = "arm,gic-400"; 339 reg = <0x7fff9000 0x1000>, 340 <0x7fffa000 0x2000>, 341 <0x7fffc000 0x2000>, 342 <0x7fffe000 0x2000>; 343 interrupt-controller; 344 #address-cells = <0>; 345 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 346 IRQ_TYPE_LEVEL_HIGH)>; 347 #interrupt-cells = <3>; 348 }; 349 350 aon_intr: interrupt-controller@7d510600 { 351 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 352 reg = <0x7d510600 0x30>; 353 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 354 interrupt-controller; 355 #interrupt-cells = <1>; 356 }; 357 358 pixelvalve0: pixelvalve@7c410000 { 359 compatible = "brcm,bcm2712-pixelvalve0"; 360 reg = <0x7c410000 0x100>; 361 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 362 }; 363 364 pixelvalve1: pixelvalve@7c411000 { 365 compatible = "brcm,bcm2712-pixelvalve1"; 366 reg = <0x7c411000 0x100>; 367 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 368 }; 369 370 mop: mop@7c500000 { 371 compatible = "brcm,bcm2712-mop"; 372 reg = <0x7c500000 0x28>; 373 interrupt-parent = <&disp_intr>; 374 interrupts = <1>; 375 }; 376 377 moplet: moplet@7c501000 { 378 compatible = "brcm,bcm2712-moplet"; 379 reg = <0x7c501000 0x20>; 380 interrupt-parent = <&disp_intr>; 381 interrupts = <0>; 382 }; 383 384 disp_intr: interrupt-controller@7c502000 { 385 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 386 reg = <0x7c502000 0x30>; 387 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-controller; 389 #interrupt-cells = <1>; 390 }; 391 392 dvp: clock@7c700000 { 393 compatible = "brcm,brcm2711-dvp"; 394 reg = <0x7c700000 0x10>; 395 clocks = <&clk_108MHz>; 396 #clock-cells = <1>; 397 #reset-cells = <1>; 398 }; 399 400 ddc0: i2c@7d508200 { 401 compatible = "brcm,brcmstb-i2c"; 402 reg = <0x7d508200 0x58>; 403 interrupt-parent = <&bsc_irq>; 404 interrupts = <1>; 405 clock-frequency = <97500>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 }; 409 410 ddc1: i2c@7d508280 { 411 compatible = "brcm,brcmstb-i2c"; 412 reg = <0x7d508280 0x58>; 413 interrupt-parent = <&bsc_irq>; 414 interrupts = <2>; 415 clock-frequency = <97500>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 }; 419 420 bsc_irq: interrupt-controller@7d508380 { 421 compatible = "brcm,bcm7271-l2-intc"; 422 reg = <0x7d508380 0x10>; 423 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 424 interrupt-controller; 425 #interrupt-cells = <1>; 426 }; 427 428 main_irq: interrupt-controller@7d508400 { 429 compatible = "brcm,bcm7271-l2-intc"; 430 reg = <0x7d508400 0x10>; 431 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 432 interrupt-controller; 433 #interrupt-cells = <1>; 434 }; 435 436 hdmi0: hdmi@7c701400 { 437 compatible = "brcm,bcm2712-hdmi0"; 438 reg = <0x7c701400 0x300>, 439 <0x7c701000 0x200>, 440 <0x7c701d00 0x300>, 441 <0x7c702000 0x80>, 442 <0x7c703800 0x200>, 443 <0x7c704000 0x800>, 444 <0x7c700100 0x80>, 445 <0x7d510800 0x100>, 446 <0x7c720000 0x100>; 447 reg-names = "hdmi", 448 "dvp", 449 "phy", 450 "rm", 451 "packet", 452 "metadata", 453 "csc", 454 "cec", 455 "hd"; 456 resets = <&dvp 1>; 457 interrupt-parent = <&aon_intr>; 458 interrupts = <1>, <2>, <3>, 459 <7>, <8>; 460 interrupt-names = "cec-tx", "cec-rx", "cec-low", 461 "hpd-connected", "hpd-removed"; 462 ddc = <&ddc0>; 463 }; 464 465 hdmi1: hdmi@7c706400 { 466 compatible = "brcm,bcm2712-hdmi1"; 467 reg = <0x7c706400 0x300>, 468 <0x7c706000 0x200>, 469 <0x7c706d00 0x300>, 470 <0x7c707000 0x80>, 471 <0x7c708800 0x200>, 472 <0x7c709000 0x800>, 473 <0x7c700180 0x80>, 474 <0x7d511000 0x100>, 475 <0x7c720000 0x100>; 476 reg-names = "hdmi", 477 "dvp", 478 "phy", 479 "rm", 480 "packet", 481 "metadata", 482 "csc", 483 "cec", 484 "hd"; 485 resets = <&dvp 2>; 486 interrupt-parent = <&aon_intr>; 487 interrupts = <11>, <12>, <13>, 488 <14>, <15>; 489 interrupt-names = "cec-tx", "cec-rx", "cec-low", 490 "hpd-connected", "hpd-removed"; 491 ddc = <&ddc1>; 492 }; 493 }; 494 495 axi: axi { 496 compatible = "simple-bus"; 497 #address-cells = <2>; 498 #size-cells = <2>; 499 500 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 501 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 502 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 503 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 504 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 505 506 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 507 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 508 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 509 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 510 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 511 512 pcie0: pcie@1000100000 { 513 compatible = "brcm,bcm2712-pcie"; 514 reg = <0x10 0x00100000 0x00 0x9310>; 515 device_type = "pci"; 516 linux,pci-domain = <0>; 517 max-link-speed = <2>; 518 num-lanes = <1>; 519 #address-cells = <3>; 520 #interrupt-cells = <1>; 521 #size-cells = <2>; 522 interrupt-parent = <&gicv2>; 523 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "pcie", "msi"; 526 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 527 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 528 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 529 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 530 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 531 resets = <&pcie_rescal>, <&bcm_reset 42>; 532 reset-names = "rescal", "bridge"; 533 msi-controller; 534 msi-parent = <&pcie0>; 535 536 ranges = 537 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 538 <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>, 539 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 540 <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>; 541 542 dma-ranges = 543 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 544 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; 545 546 status = "disabled"; 547 }; 548 549 pcie1: pcie@1000110000 { 550 compatible = "brcm,bcm2712-pcie"; 551 reg = <0x10 0x00110000 0x00 0x9310>; 552 device_type = "pci"; 553 linux,pci-domain = <1>; 554 max-link-speed = <2>; 555 num-lanes = <1>; 556 #address-cells = <3>; 557 #interrupt-cells = <1>; 558 #size-cells = <2>; 559 interrupt-parent = <&gicv2>; 560 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "pcie", "msi"; 563 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 565 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 566 <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 567 <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 568 resets = <&pcie_rescal>, <&bcm_reset 43>; 569 reset-names = "rescal", "bridge"; 570 msi-controller; 571 msi-parent = <&mip1>; 572 573 ranges = 574 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 575 <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>, 576 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 577 <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>; 578 579 dma-ranges = 580 /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */ 581 <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 582 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */ 583 <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>; 584 585 status = "disabled"; 586 }; 587 588 pcie2: pcie@1000120000 { 589 compatible = "brcm,bcm2712-pcie"; 590 reg = <0x10 0x00120000 0x00 0x9310>; 591 device_type = "pci"; 592 linux,pci-domain = <2>; 593 max-link-speed = <2>; 594 num-lanes = <4>; 595 #address-cells = <3>; 596 #interrupt-cells = <1>; 597 #size-cells = <2>; 598 interrupt-parent = <&gicv2>; 599 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-names = "pcie", "msi"; 602 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 603 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 604 <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 605 <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 606 <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 607 resets = <&pcie_rescal>, <&bcm_reset 44>; 608 reset-names = "rescal", "bridge"; 609 msi-controller; 610 msi-parent = <&mip0>; 611 612 ranges = 613 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 614 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>, 615 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 616 <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>; 617 618 dma-ranges = 619 /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 620 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>, 621 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 622 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 623 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */ 624 <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>; 625 626 status = "disabled"; 627 }; 628 629 mip0: msi-controller@1000130000 { 630 compatible = "brcm,bcm2712-mip"; 631 reg = <0x10 0x00130000 0x00 0xc0>, 632 <0xff 0xfffff000 0x00 0x1000>; 633 msi-controller; 634 msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; 635 brcm,msi-offset = <0>; 636 }; 637 638 mip1: msi-controller@1000131000 { 639 compatible = "brcm,bcm2712-mip"; 640 reg = <0x10 0x00131000 0x00 0xc0>, 641 <0xff 0xfffff000 0x00 0x1000>; 642 msi-controller; 643 msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; 644 brcm,msi-offset = <8>; 645 }; 646 647 isp: isp@1000880000 { 648 compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe"; 649 reg = <0x10 0x00880000 0x0 0x4000>; 650 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&firmware_clocks 7>; 652 }; 653 654 v3d: gpu@1002000000 { 655 compatible = "brcm,2712-v3d"; 656 reg = <0x10 0x02000000 0x00 0x4000>, 657 <0x10 0x02008000 0x00 0x6000>, 658 <0x10 0x02030800 0x00 0x0700>; 659 reg-names = "hub", "core0", "sms"; 660 661 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 662 resets = <&pm BCM2835_RESET_V3D>; 663 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 665 }; 666 }; 667 668 vc4: gpu { 669 compatible = "brcm,bcm2712-vc6"; 670 }; 671 672 timer { 673 compatible = "arm,armv8-timer"; 674 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 675 IRQ_TYPE_LEVEL_LOW)>, 676 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 677 IRQ_TYPE_LEVEL_LOW)>, 678 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 679 IRQ_TYPE_LEVEL_LOW)>, 680 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 681 IRQ_TYPE_LEVEL_LOW)>, 682 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | 683 IRQ_TYPE_LEVEL_LOW)>; 684 }; 685 686 clk_27MHz: clk-27M { 687 #clock-cells = <0>; 688 compatible = "fixed-clock"; 689 clock-frequency = <27000000>; 690 clock-output-names = "27MHz-clock"; 691 }; 692 693 clk_108MHz: clk-108M { 694 #clock-cells = <0>; 695 compatible = "fixed-clock"; 696 clock-frequency = <108000000>; 697 clock-output-names = "108MHz-clock"; 698 }; 699 700 hvs: hvs@107c580000 { 701 compatible = "brcm,bcm2712-hvs"; 702 reg = <0x10 0x7c580000 0x0 0x1a000>; 703 interrupt-parent = <&disp_intr>; 704 interrupts = <2>, <9>, <16>; 705 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; 706 }; 707}; 708