1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3 4/ { 5 compatible = "brcm,bcm2712"; 6 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 interrupt-parent = <&gicv2>; 11 12 clocks { 13 /* The oscillator is the root of the clock tree. */ 14 clk_osc: clk-osc { 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-output-names = "osc"; 18 clock-frequency = <54000000>; 19 }; 20 21 clk_vpu: clk-vpu { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <750000000>; 25 clock-output-names = "vpu-clock"; 26 }; 27 28 clk_uart: clk-uart { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <9216000>; 32 clock-output-names = "uart-clock"; 33 }; 34 35 clk_emmc2: clk-emmc2 { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <200000000>; 39 clock-output-names = "emmc2-clock"; 40 }; 41 42 clk_sw_baud: clk-sw-baud { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <96000000>; 46 clock-output-names = "sw-baud"; 47 }; 48 }; 49 50 cpus: cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 /* Source for L1 d/i cache-line-size, cache-sets, cache-size 55 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en 56 * Source for L2 cache-line-size and cache-sets: 57 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en 58 * and for cache-size: 59 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 60 */ 61 cpu0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a76"; 64 reg = <0x000>; 65 enable-method = "psci"; 66 d-cache-size = <0x10000>; 67 d-cache-line-size = <64>; 68 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 69 i-cache-size = <0x10000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 72 next-level-cache = <&l2_cache_l0>; 73 74 l2_cache_l0: l2-cache { 75 compatible = "cache"; 76 cache-size = <0x80000>; 77 cache-line-size = <64>; 78 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 79 cache-level = <2>; 80 cache-unified; 81 next-level-cache = <&l3_cache>; 82 }; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a76"; 88 reg = <0x100>; 89 enable-method = "psci"; 90 d-cache-size = <0x10000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 93 i-cache-size = <0x10000>; 94 i-cache-line-size = <64>; 95 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 96 next-level-cache = <&l2_cache_l1>; 97 98 l2_cache_l1: l2-cache { 99 compatible = "cache"; 100 cache-size = <0x80000>; 101 cache-line-size = <64>; 102 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&l3_cache>; 106 }; 107 }; 108 109 cpu2: cpu@2 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a76"; 112 reg = <0x200>; 113 enable-method = "psci"; 114 d-cache-size = <0x10000>; 115 d-cache-line-size = <64>; 116 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 117 i-cache-size = <0x10000>; 118 i-cache-line-size = <64>; 119 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 120 next-level-cache = <&l2_cache_l2>; 121 122 l2_cache_l2: l2-cache { 123 compatible = "cache"; 124 cache-size = <0x80000>; 125 cache-line-size = <64>; 126 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 127 cache-level = <2>; 128 cache-unified; 129 next-level-cache = <&l3_cache>; 130 }; 131 }; 132 133 cpu3: cpu@3 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a76"; 136 reg = <0x300>; 137 enable-method = "psci"; 138 d-cache-size = <0x10000>; 139 d-cache-line-size = <64>; 140 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 141 i-cache-size = <0x10000>; 142 i-cache-line-size = <64>; 143 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 144 next-level-cache = <&l2_cache_l3>; 145 146 l2_cache_l3: l2-cache { 147 compatible = "cache"; 148 cache-size = <0x80000>; 149 cache-line-size = <64>; 150 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_cache>; 154 }; 155 }; 156 157 /* Source for cache-line-size and cache-sets: 158 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en 159 * Source for cache-size: 160 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 161 */ 162 l3_cache: l3-cache { 163 compatible = "cache"; 164 cache-size = <0x200000>; 165 cache-line-size = <64>; 166 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set 167 cache-level = <3>; 168 cache-unified; 169 }; 170 }; 171 172 psci { 173 method = "smc"; 174 compatible = "arm,psci-1.0", "arm,psci-0.2"; 175 }; 176 177 rmem: reserved-memory { 178 ranges; 179 #address-cells = <2>; 180 #size-cells = <2>; 181 182 atf@0 { 183 reg = <0x0 0x0 0x0 0x80000>; 184 no-map; 185 }; 186 187 cma: linux,cma { 188 compatible = "shared-dma-pool"; 189 size = <0x0 0x4000000>; /* 64MB */ 190 reusable; 191 linux,cma-default; 192 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; 193 }; 194 }; 195 196 soc: soc@107c000000 { 197 compatible = "simple-bus"; 198 ranges = <0x00000000 0x10 0x00000000 0x80000000>; 199 #address-cells = <1>; 200 #size-cells = <1>; 201 202 pcie_rescal: reset-controller@119500 { 203 compatible = "brcm,bcm7216-pcie-sata-rescal"; 204 reg = <0x00119500 0x10>; 205 #reset-cells = <0>; 206 }; 207 208 sdio1: mmc@fff000 { 209 compatible = "brcm,bcm2712-sdhci", 210 "brcm,sdhci-brcmstb"; 211 reg = <0x00fff000 0x260>, 212 <0x00fff400 0x200>; 213 reg-names = "host", "cfg"; 214 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&clk_emmc2>; 216 clock-names = "sw_sdio"; 217 mmc-ddr-3_3v; 218 }; 219 220 bcm_reset: reset-controller@1504318 { 221 compatible = "brcm,brcmstb-reset"; 222 reg = <0x01504318 0x30>; 223 #reset-cells = <1>; 224 }; 225 226 system_timer: timer@7c003000 { 227 compatible = "brcm,bcm2835-system-timer"; 228 reg = <0x7c003000 0x1000>; 229 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 233 clock-frequency = <1000000>; 234 }; 235 236 mailbox: mailbox@7c013880 { 237 compatible = "brcm,bcm2835-mbox"; 238 reg = <0x7c013880 0x40>; 239 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 240 #mbox-cells = <0>; 241 }; 242 243 uart10: serial@7d001000 { 244 compatible = "arm,pl011", "arm,primecell"; 245 reg = <0x7d001000 0x200>; 246 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clk_uart>, <&clk_vpu>; 248 clock-names = "uartclk", "apb_pclk"; 249 arm,primecell-periphid = <0x00341011>; 250 status = "disabled"; 251 }; 252 253 pinctrl: pinctrl@7d504100 { 254 compatible = "brcm,bcm2712c0-pinctrl"; 255 reg = <0x7d504100 0x30>; 256 }; 257 258 gio: gpio@7d508500 { 259 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 260 reg = <0x7d508500 0x40>; 261 interrupt-parent = <&main_irq>; 262 interrupts = <0>; 263 gpio-controller; 264 #gpio-cells = <2>; 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 brcm,gpio-bank-widths = <32 22>; 268 }; 269 270 uarta: serial@7d50c000 { 271 compatible = "brcm,bcm7271-uart"; 272 reg = <0x7d50c000 0x20>; 273 reg-names = "uart"; 274 clocks = <&clk_sw_baud>; 275 clock-names = "sw_baud"; 276 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "uart"; 278 status = "disabled"; 279 }; 280 281 pinctrl_aon: pinctrl@7d510700 { 282 compatible = "brcm,bcm2712c0-aon-pinctrl"; 283 reg = <0x7d510700 0x20>; 284 }; 285 286 interrupt-controller@7d517000 { 287 compatible = "brcm,bcm7271-l2-intc"; 288 reg = <0x7d517000 0x10>; 289 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-controller; 291 #interrupt-cells = <1>; 292 }; 293 294 gio_aon: gpio@7d517c00 { 295 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 296 reg = <0x7d517c00 0x40>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 brcm,gpio-bank-widths = <17 6>; 300 /* The lack of 'interrupt-controller' property here is intended: 301 * don't use GIO_AON as an interrupt controller because it will 302 * clash with the firmware monitoring the PMIC interrupt via the VPU. 303 */ 304 }; 305 306 sdio2: mmc@1100000 { 307 compatible = "brcm,bcm2712-sdhci", 308 "brcm,sdhci-brcmstb"; 309 reg = <0x01100000 0x260>, 310 <0x01100400 0x200>; 311 reg-names = "host", "cfg"; 312 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&clk_emmc2>; 314 clock-names = "sw_sdio"; 315 sdhci-caps-mask = <0x0000C000 0x0>; 316 sdhci-caps = <0x0 0x0>; 317 mmc-ddr-3_3v; 318 status = "disabled"; 319 }; 320 321 gicv2: interrupt-controller@7fff9000 { 322 compatible = "arm,gic-400"; 323 reg = <0x7fff9000 0x1000>, 324 <0x7fffa000 0x2000>, 325 <0x7fffc000 0x2000>, 326 <0x7fffe000 0x2000>; 327 interrupt-controller; 328 #address-cells = <0>; 329 #interrupt-cells = <3>; 330 }; 331 332 aon_intr: interrupt-controller@7d510600 { 333 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 334 reg = <0x7d510600 0x30>; 335 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 336 interrupt-controller; 337 #interrupt-cells = <1>; 338 }; 339 340 pixelvalve0: pixelvalve@7c410000 { 341 compatible = "brcm,bcm2712-pixelvalve0"; 342 reg = <0x7c410000 0x100>; 343 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 344 }; 345 346 pixelvalve1: pixelvalve@7c411000 { 347 compatible = "brcm,bcm2712-pixelvalve1"; 348 reg = <0x7c411000 0x100>; 349 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 350 }; 351 352 mop: mop@7c500000 { 353 compatible = "brcm,bcm2712-mop"; 354 reg = <0x7c500000 0x28>; 355 interrupt-parent = <&disp_intr>; 356 interrupts = <1>; 357 }; 358 359 moplet: moplet@7c501000 { 360 compatible = "brcm,bcm2712-moplet"; 361 reg = <0x7c501000 0x20>; 362 interrupt-parent = <&disp_intr>; 363 interrupts = <0>; 364 }; 365 366 disp_intr: interrupt-controller@7c502000 { 367 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 368 reg = <0x7c502000 0x30>; 369 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-controller; 371 #interrupt-cells = <1>; 372 }; 373 374 dvp: clock@7c700000 { 375 compatible = "brcm,brcm2711-dvp"; 376 reg = <0x7c700000 0x10>; 377 clocks = <&clk_108MHz>; 378 #clock-cells = <1>; 379 #reset-cells = <1>; 380 }; 381 382 ddc0: i2c@7d508200 { 383 compatible = "brcm,brcmstb-i2c"; 384 reg = <0x7d508200 0x58>; 385 interrupt-parent = <&bsc_irq>; 386 interrupts = <1>; 387 clock-frequency = <97500>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 }; 391 392 ddc1: i2c@7d508280 { 393 compatible = "brcm,brcmstb-i2c"; 394 reg = <0x7d508280 0x58>; 395 interrupt-parent = <&bsc_irq>; 396 interrupts = <2>; 397 clock-frequency = <97500>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 }; 401 402 bsc_irq: interrupt-controller@7d508380 { 403 compatible = "brcm,bcm7271-l2-intc"; 404 reg = <0x7d508380 0x10>; 405 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-controller; 407 #interrupt-cells = <1>; 408 }; 409 410 main_irq: interrupt-controller@7d508400 { 411 compatible = "brcm,bcm7271-l2-intc"; 412 reg = <0x7d508400 0x10>; 413 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-controller; 415 #interrupt-cells = <1>; 416 }; 417 418 hdmi0: hdmi@7c701400 { 419 compatible = "brcm,bcm2712-hdmi0"; 420 reg = <0x7c701400 0x300>, 421 <0x7c701000 0x200>, 422 <0x7c701d00 0x300>, 423 <0x7c702000 0x80>, 424 <0x7c703800 0x200>, 425 <0x7c704000 0x800>, 426 <0x7c700100 0x80>, 427 <0x7d510800 0x100>, 428 <0x7c720000 0x100>; 429 reg-names = "hdmi", 430 "dvp", 431 "phy", 432 "rm", 433 "packet", 434 "metadata", 435 "csc", 436 "cec", 437 "hd"; 438 resets = <&dvp 1>; 439 interrupt-parent = <&aon_intr>; 440 interrupts = <1>, <2>, <3>, 441 <7>, <8>; 442 interrupt-names = "cec-tx", "cec-rx", "cec-low", 443 "hpd-connected", "hpd-removed"; 444 ddc = <&ddc0>; 445 }; 446 447 hdmi1: hdmi@7c706400 { 448 compatible = "brcm,bcm2712-hdmi1"; 449 reg = <0x7c706400 0x300>, 450 <0x7c706000 0x200>, 451 <0x7c706d00 0x300>, 452 <0x7c707000 0x80>, 453 <0x7c708800 0x200>, 454 <0x7c709000 0x800>, 455 <0x7c700180 0x80>, 456 <0x7d511000 0x100>, 457 <0x7c720000 0x100>; 458 reg-names = "hdmi", 459 "dvp", 460 "phy", 461 "rm", 462 "packet", 463 "metadata", 464 "csc", 465 "cec", 466 "hd"; 467 resets = <&dvp 2>; 468 interrupt-parent = <&aon_intr>; 469 interrupts = <11>, <12>, <13>, 470 <14>, <15>; 471 interrupt-names = "cec-tx", "cec-rx", "cec-low", 472 "hpd-connected", "hpd-removed"; 473 ddc = <&ddc1>; 474 }; 475 }; 476 477 axi: axi { 478 compatible = "simple-bus"; 479 #address-cells = <2>; 480 #size-cells = <2>; 481 482 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 483 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 484 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 485 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 486 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 487 488 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 489 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 490 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 491 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 492 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 493 494 vc4: gpu { 495 compatible = "brcm,bcm2712-vc6"; 496 }; 497 498 pcie0: pcie@1000100000 { 499 compatible = "brcm,bcm2712-pcie"; 500 reg = <0x10 0x00100000 0x00 0x9310>; 501 device_type = "pci"; 502 linux,pci-domain = <0>; 503 max-link-speed = <2>; 504 num-lanes = <1>; 505 #address-cells = <3>; 506 #interrupt-cells = <1>; 507 #size-cells = <2>; 508 interrupt-parent = <&gicv2>; 509 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 511 interrupt-names = "pcie", "msi"; 512 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 513 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 514 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 515 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 516 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 517 resets = <&pcie_rescal>, <&bcm_reset 42>; 518 reset-names = "rescal", "bridge"; 519 msi-controller; 520 msi-parent = <&pcie0>; 521 522 ranges = 523 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 524 <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>, 525 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 526 <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>; 527 528 dma-ranges = 529 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 530 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; 531 532 status = "disabled"; 533 }; 534 535 pcie1: pcie@1000110000 { 536 compatible = "brcm,bcm2712-pcie"; 537 reg = <0x10 0x00110000 0x00 0x9310>; 538 device_type = "pci"; 539 linux,pci-domain = <1>; 540 max-link-speed = <2>; 541 num-lanes = <1>; 542 #address-cells = <3>; 543 #interrupt-cells = <1>; 544 #size-cells = <2>; 545 interrupt-parent = <&gicv2>; 546 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "pcie", "msi"; 549 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 550 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 551 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 552 <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 553 <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 554 resets = <&pcie_rescal>, <&bcm_reset 43>; 555 reset-names = "rescal", "bridge"; 556 msi-controller; 557 msi-parent = <&mip1>; 558 559 ranges = 560 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 561 <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>, 562 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 563 <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>; 564 565 dma-ranges = 566 /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */ 567 <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 568 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */ 569 <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>; 570 571 status = "disabled"; 572 }; 573 574 pcie2: pcie@1000120000 { 575 compatible = "brcm,bcm2712-pcie"; 576 reg = <0x10 0x00120000 0x00 0x9310>; 577 device_type = "pci"; 578 linux,pci-domain = <2>; 579 max-link-speed = <2>; 580 num-lanes = <4>; 581 #address-cells = <3>; 582 #interrupt-cells = <1>; 583 #size-cells = <2>; 584 interrupt-parent = <&gicv2>; 585 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "pcie", "msi"; 588 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 589 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 590 <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 591 <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 592 <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 593 resets = <&pcie_rescal>, <&bcm_reset 44>; 594 reset-names = "rescal", "bridge"; 595 msi-controller; 596 msi-parent = <&mip0>; 597 598 ranges = 599 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 600 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>, 601 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 602 <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>; 603 604 dma-ranges = 605 /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 606 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>, 607 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 608 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 609 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */ 610 <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>; 611 612 status = "disabled"; 613 }; 614 615 mip0: msi-controller@1000130000 { 616 compatible = "brcm,bcm2712-mip"; 617 reg = <0x10 0x00130000 0x00 0xc0>, 618 <0xff 0xfffff000 0x00 0x1000>; 619 msi-controller; 620 msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; 621 brcm,msi-offset = <0>; 622 }; 623 624 mip1: msi-controller@1000131000 { 625 compatible = "brcm,bcm2712-mip"; 626 reg = <0x10 0x00131000 0x00 0xc0>, 627 <0xff 0xfffff000 0x00 0x1000>; 628 msi-controller; 629 msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; 630 brcm,msi-offset = <8>; 631 }; 632 }; 633 634 timer { 635 compatible = "arm,armv8-timer"; 636 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 637 IRQ_TYPE_LEVEL_LOW)>, 638 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 639 IRQ_TYPE_LEVEL_LOW)>, 640 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 641 IRQ_TYPE_LEVEL_LOW)>, 642 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 643 IRQ_TYPE_LEVEL_LOW)>, 644 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | 645 IRQ_TYPE_LEVEL_LOW)>; 646 }; 647 648 clk_27MHz: clk-27M { 649 #clock-cells = <0>; 650 compatible = "fixed-clock"; 651 clock-frequency = <27000000>; 652 clock-output-names = "27MHz-clock"; 653 }; 654 655 clk_108MHz: clk-108M { 656 #clock-cells = <0>; 657 compatible = "fixed-clock"; 658 clock-frequency = <108000000>; 659 clock-output-names = "108MHz-clock"; 660 }; 661 662 hvs: hvs@107c580000 { 663 compatible = "brcm,bcm2712-hvs"; 664 reg = <0x10 0x7c580000 0x0 0x1a000>; 665 interrupt-parent = <&disp_intr>; 666 interrupts = <2>, <9>, <16>; 667 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; 668 }; 669}; 670