1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Versatile Express 4 * 5 * LogicTile Express 20MG 6 * V2F-1XV7 7 * 8 * Cortex-A53 (2 cores) Soft Macrocell Model 9 * 10 * HBI-0247C 11 */ 12 13/dts-v1/; 14 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include "vexpress-v2m-rs1.dtsi" 17 18/ { 19 model = "V2F-1XV7 Cortex-A53x2 SMM"; 20 arm,hbi = <0x247>; 21 arm,vexpress,site = <0xf>; 22 compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress"; 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { 28 stdout-path = "serial0:38400n8"; 29 }; 30 31 aliases { 32 serial0 = &v2m_serial0; 33 serial1 = &v2m_serial1; 34 serial2 = &v2m_serial2; 35 serial3 = &v2m_serial3; 36 i2c0 = &v2m_i2c_dvi; 37 i2c1 = &v2m_i2c_pcie; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0 0>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0 1>; 55 next-level-cache = <&L2_0>; 56 }; 57 58 L2_0: l2-cache0 { 59 compatible = "cache"; 60 }; 61 }; 62 63 memory@80000000 { 64 device_type = "memory"; 65 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */ 66 }; 67 68 reserved-memory { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 ranges; 72 73 /* Chipselect 2 is physically at 0x18000000 */ 74 vram: vram@18000000 { 75 /* 8 MB of designated video RAM */ 76 compatible = "shared-dma-pool"; 77 reg = <0 0x18000000 0 0x00800000>; 78 no-map; 79 }; 80 }; 81 82 gic: interrupt-controller@2c001000 { 83 compatible = "arm,gic-400"; 84 #interrupt-cells = <3>; 85 #address-cells = <0>; 86 interrupt-controller; 87 reg = <0 0x2c001000 0 0x1000>, 88 <0 0x2c002000 0 0x2000>, 89 <0 0x2c004000 0 0x2000>, 90 <0 0x2c006000 0 0x2000>; 91 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 92 }; 93 94 timer { 95 compatible = "arm,armv8-timer"; 96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 100 }; 101 102 pmu { 103 compatible = "arm,armv8-pmuv3"; 104 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 106 }; 107 108 dcc { 109 compatible = "arm,vexpress,config-bus"; 110 arm,vexpress,config-bridge = <&v2m_sysreg>; 111 112 smbclk: smclk { 113 /* SMC clock */ 114 compatible = "arm,vexpress-osc"; 115 arm,vexpress-sysreg,func = <1 4>; 116 freq-range = <40000000 40000000>; 117 #clock-cells = <0>; 118 clock-output-names = "smclk"; 119 }; 120 121 volt-vio { 122 /* VIO to expansion board above */ 123 compatible = "arm,vexpress-volt"; 124 arm,vexpress-sysreg,func = <2 0>; 125 regulator-name = "VIO_UP"; 126 regulator-min-microvolt = <800000>; 127 regulator-max-microvolt = <1800000>; 128 regulator-always-on; 129 }; 130 131 volt-12v { 132 /* 12V from power connector J6 */ 133 compatible = "arm,vexpress-volt"; 134 arm,vexpress-sysreg,func = <2 1>; 135 regulator-name = "12"; 136 regulator-always-on; 137 }; 138 139 temp-fpga { 140 /* FPGA temperature */ 141 compatible = "arm,vexpress-temp"; 142 arm,vexpress-sysreg,func = <4 0>; 143 label = "FPGA"; 144 }; 145 }; 146 147 smb: bus@8000000 { 148 compatible = "simple-bus"; 149 150 #address-cells = <2>; 151 #size-cells = <1>; 152 ranges = <0 0 0 0x08000000 0x04000000>, 153 <1 0 0 0x14000000 0x04000000>, 154 <2 0 0 0x18000000 0x04000000>, 155 <3 0 0 0x1c000000 0x04000000>, 156 <4 0 0 0x0c000000 0x04000000>, 157 <5 0 0 0x10000000 0x04000000>; 158 159 #interrupt-cells = <1>; 160 interrupt-map-mask = <0 0 63>; 161 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 162 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 163 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 164 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 165 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 166 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 167 <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 168 <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 169 <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 170 <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 171 <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 172 <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 173 <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 174 <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 175 <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 176 <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 177 <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 178 <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 179 <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 180 <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 181 <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 182 <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 183 <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 184 <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 185 <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 186 <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 187 <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 188 <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 189 <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 190 <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 191 <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 192 <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 193 <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 194 <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 195 <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 196 <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 197 <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 198 <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 199 <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 200 <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 201 <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 202 <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 203 <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 204 }; 205}; 206