1/* 2 * ARM Ltd. Fast Models 3 * 4 * Architecture Envelope Model (AEM) ARMv8-A 5 * ARMAEMv8AMPCT 6 * 7 * RTSM_VE_AEMv8A.lisa 8 */ 9 10/dts-v1/; 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 model = "RTSM_VE_AEMv8A"; 16 compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 aliases { 24 serial0 = &v2m_serial0; 25 serial1 = &v2m_serial1; 26 serial2 = &v2m_serial2; 27 serial3 = &v2m_serial3; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,armv8"; 37 reg = <0x0 0x0>; 38 enable-method = "spin-table"; 39 cpu-release-addr = <0x0 0x8000fff8>; 40 }; 41 cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,armv8"; 44 reg = <0x0 0x1>; 45 enable-method = "spin-table"; 46 cpu-release-addr = <0x0 0x8000fff8>; 47 }; 48 cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,armv8"; 51 reg = <0x0 0x2>; 52 enable-method = "spin-table"; 53 cpu-release-addr = <0x0 0x8000fff8>; 54 }; 55 cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x8000fff8>; 61 }; 62 }; 63 64 memory@80000000 { 65 device_type = "memory"; 66 reg = <0x00000000 0x80000000 0 0x80000000>, 67 <0x00000008 0x80000000 0 0x80000000>; 68 }; 69 70 gic: interrupt-controller@2c001000 { 71 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 72 #interrupt-cells = <3>; 73 #address-cells = <0>; 74 interrupt-controller; 75 reg = <0x0 0x2c001000 0 0x1000>, 76 <0x0 0x2c002000 0 0x1000>, 77 <0x0 0x2c004000 0 0x2000>, 78 <0x0 0x2c006000 0 0x2000>; 79 interrupts = <1 9 0xf04>; 80 }; 81 82 timer { 83 compatible = "arm,armv8-timer"; 84 interrupts = <1 13 0xf08>, 85 <1 14 0xf08>, 86 <1 11 0xf08>, 87 <1 10 0xf08>; 88 clock-frequency = <100000000>; 89 }; 90 91 pmu { 92 compatible = "arm,armv8-pmuv3"; 93 interrupts = <0 60 4>, 94 <0 61 4>, 95 <0 62 4>, 96 <0 63 4>; 97 }; 98 99 smb { 100 compatible = "simple-bus"; 101 102 #address-cells = <2>; 103 #size-cells = <1>; 104 ranges = <0 0 0 0x08000000 0x04000000>, 105 <1 0 0 0x14000000 0x04000000>, 106 <2 0 0 0x18000000 0x04000000>, 107 <3 0 0 0x1c000000 0x04000000>, 108 <4 0 0 0x0c000000 0x04000000>, 109 <5 0 0 0x10000000 0x04000000>; 110 111 #interrupt-cells = <1>; 112 interrupt-map-mask = <0 0 63>; 113 interrupt-map = <0 0 0 &gic 0 0 4>, 114 <0 0 1 &gic 0 1 4>, 115 <0 0 2 &gic 0 2 4>, 116 <0 0 3 &gic 0 3 4>, 117 <0 0 4 &gic 0 4 4>, 118 <0 0 5 &gic 0 5 4>, 119 <0 0 6 &gic 0 6 4>, 120 <0 0 7 &gic 0 7 4>, 121 <0 0 8 &gic 0 8 4>, 122 <0 0 9 &gic 0 9 4>, 123 <0 0 10 &gic 0 10 4>, 124 <0 0 11 &gic 0 11 4>, 125 <0 0 12 &gic 0 12 4>, 126 <0 0 13 &gic 0 13 4>, 127 <0 0 14 &gic 0 14 4>, 128 <0 0 15 &gic 0 15 4>, 129 <0 0 16 &gic 0 16 4>, 130 <0 0 17 &gic 0 17 4>, 131 <0 0 18 &gic 0 18 4>, 132 <0 0 19 &gic 0 19 4>, 133 <0 0 20 &gic 0 20 4>, 134 <0 0 21 &gic 0 21 4>, 135 <0 0 22 &gic 0 22 4>, 136 <0 0 23 &gic 0 23 4>, 137 <0 0 24 &gic 0 24 4>, 138 <0 0 25 &gic 0 25 4>, 139 <0 0 26 &gic 0 26 4>, 140 <0 0 27 &gic 0 27 4>, 141 <0 0 28 &gic 0 28 4>, 142 <0 0 29 &gic 0 29 4>, 143 <0 0 30 &gic 0 30 4>, 144 <0 0 31 &gic 0 31 4>, 145 <0 0 32 &gic 0 32 4>, 146 <0 0 33 &gic 0 33 4>, 147 <0 0 34 &gic 0 34 4>, 148 <0 0 35 &gic 0 35 4>, 149 <0 0 36 &gic 0 36 4>, 150 <0 0 37 &gic 0 37 4>, 151 <0 0 38 &gic 0 38 4>, 152 <0 0 39 &gic 0 39 4>, 153 <0 0 40 &gic 0 40 4>, 154 <0 0 41 &gic 0 41 4>, 155 <0 0 42 &gic 0 42 4>; 156 157 /include/ "rtsm_ve-motherboard.dtsi" 158 }; 159}; 160