1/* 2 * ARM Juno Platform motherboard peripherals 3 * 4 * Copyright (c) 2013-2014 ARM Ltd 5 * 6 * This file is licensed under a dual GPLv2 or BSD license. 7 * 8 */ 9 10/ { 11 mb_clk24mhz: clk24mhz { 12 compatible = "fixed-clock"; 13 #clock-cells = <0>; 14 clock-frequency = <24000000>; 15 clock-output-names = "juno_mb:clk24mhz"; 16 }; 17 18 mb_clk25mhz: clk25mhz { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <25000000>; 22 clock-output-names = "juno_mb:clk25mhz"; 23 }; 24 25 v2m_refclk1mhz: refclk1mhz { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <1000000>; 29 clock-output-names = "juno_mb:refclk1mhz"; 30 }; 31 32 v2m_refclk32khz: refclk32khz { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32768>; 36 clock-output-names = "juno_mb:refclk32khz"; 37 }; 38 39 mb_fixed_3v3: mcc-sb-3v3 { 40 compatible = "regulator-fixed"; 41 regulator-name = "MCC_SB_3V3"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 regulator-always-on; 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 50 power-button { 51 debounce-interval = <50>; 52 wakeup-source; 53 linux,code = <116>; 54 label = "POWER"; 55 gpios = <&iofpga_gpio0 0 0x4>; 56 }; 57 home-button { 58 debounce-interval = <50>; 59 wakeup-source; 60 linux,code = <102>; 61 label = "HOME"; 62 gpios = <&iofpga_gpio0 1 0x4>; 63 }; 64 rlock-button { 65 debounce-interval = <50>; 66 wakeup-source; 67 linux,code = <152>; 68 label = "RLOCK"; 69 gpios = <&iofpga_gpio0 2 0x4>; 70 }; 71 vol-up-button { 72 debounce-interval = <50>; 73 wakeup-source; 74 linux,code = <115>; 75 label = "VOL+"; 76 gpios = <&iofpga_gpio0 3 0x4>; 77 }; 78 vol-down-button { 79 debounce-interval = <50>; 80 wakeup-source; 81 linux,code = <114>; 82 label = "VOL-"; 83 gpios = <&iofpga_gpio0 4 0x4>; 84 }; 85 nmi-button { 86 debounce-interval = <50>; 87 wakeup-source; 88 linux,code = <99>; 89 label = "NMI"; 90 gpios = <&iofpga_gpio0 5 0x4>; 91 }; 92 }; 93 94 bus@8000000 { 95 motherboard-bus { 96 compatible = "arm,vexpress,v2p-p1", "simple-bus"; 97 #address-cells = <2>; /* SMB chipselect number and offset */ 98 #size-cells = <1>; 99 #interrupt-cells = <1>; 100 ranges; 101 model = "V2M-Juno"; 102 arm,hbi = <0x252>; 103 arm,vexpress,site = <0>; 104 arm,v2m-memory-map = "rs1"; 105 106 flash@0 { 107 /* 2 * 32MiB NOR Flash memory mounted on CS0 */ 108 compatible = "arm,vexpress-flash", "cfi-flash"; 109 reg = <0 0x00000000 0x04000000>; 110 bank-width = <4>; 111 /* 112 * Unfortunately, accessing the flash disturbs 113 * the CPU idle states (suspend) and CPU 114 * hotplug of the platform. For this reason, 115 * flash hardware access is disabled by default. 116 */ 117 status = "disabled"; 118 partitions { 119 compatible = "arm,arm-firmware-suite"; 120 }; 121 }; 122 123 ethernet@200000000 { 124 compatible = "smsc,lan9118", "smsc,lan9115"; 125 reg = <2 0x00000000 0x10000>; 126 interrupts = <3>; 127 phy-mode = "mii"; 128 reg-io-width = <4>; 129 smsc,irq-active-high; 130 smsc,irq-push-pull; 131 clocks = <&mb_clk25mhz>; 132 vdd33a-supply = <&mb_fixed_3v3>; 133 vddvario-supply = <&mb_fixed_3v3>; 134 }; 135 136 iofpga-bus@300000000 { 137 compatible = "simple-bus"; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges = <0 3 0 0x200000>; 141 142 v2m_sysctl: sysctl@20000 { 143 compatible = "arm,sp810", "arm,primecell"; 144 reg = <0x020000 0x1000>; 145 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; 146 clock-names = "refclk", "timclk", "apb_pclk"; 147 #clock-cells = <1>; 148 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 149 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; 150 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; 151 }; 152 153 apbregs@10000 { 154 compatible = "syscon", "simple-mfd"; 155 reg = <0x010000 0x1000>; 156 157 led0 { 158 compatible = "register-bit-led"; 159 offset = <0x08>; 160 mask = <0x01>; 161 label = "vexpress:0"; 162 linux,default-trigger = "heartbeat"; 163 default-state = "on"; 164 }; 165 led1 { 166 compatible = "register-bit-led"; 167 offset = <0x08>; 168 mask = <0x02>; 169 label = "vexpress:1"; 170 linux,default-trigger = "mmc0"; 171 default-state = "off"; 172 }; 173 led2 { 174 compatible = "register-bit-led"; 175 offset = <0x08>; 176 mask = <0x04>; 177 label = "vexpress:2"; 178 linux,default-trigger = "cpu0"; 179 default-state = "off"; 180 }; 181 led3 { 182 compatible = "register-bit-led"; 183 offset = <0x08>; 184 mask = <0x08>; 185 label = "vexpress:3"; 186 linux,default-trigger = "cpu1"; 187 default-state = "off"; 188 }; 189 led4 { 190 compatible = "register-bit-led"; 191 offset = <0x08>; 192 mask = <0x10>; 193 label = "vexpress:4"; 194 linux,default-trigger = "cpu2"; 195 default-state = "off"; 196 }; 197 led5 { 198 compatible = "register-bit-led"; 199 offset = <0x08>; 200 mask = <0x20>; 201 label = "vexpress:5"; 202 linux,default-trigger = "cpu3"; 203 default-state = "off"; 204 }; 205 led6 { 206 compatible = "register-bit-led"; 207 offset = <0x08>; 208 mask = <0x40>; 209 label = "vexpress:6"; 210 default-state = "off"; 211 }; 212 led7 { 213 compatible = "register-bit-led"; 214 offset = <0x08>; 215 mask = <0x80>; 216 label = "vexpress:7"; 217 default-state = "off"; 218 }; 219 }; 220 221 mmci@50000 { 222 compatible = "arm,pl180", "arm,primecell"; 223 reg = <0x050000 0x1000>; 224 interrupts = <5>; 225 /* cd-gpios = <&v2m_mmc_gpios 0 0>; 226 wp-gpios = <&v2m_mmc_gpios 1 0>; */ 227 max-frequency = <12000000>; 228 vmmc-supply = <&mb_fixed_3v3>; 229 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 230 clock-names = "mclk", "apb_pclk"; 231 }; 232 233 kmi@60000 { 234 compatible = "arm,pl050", "arm,primecell"; 235 reg = <0x060000 0x1000>; 236 interrupts = <8>; 237 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 238 clock-names = "KMIREFCLK", "apb_pclk"; 239 }; 240 241 kmi@70000 { 242 compatible = "arm,pl050", "arm,primecell"; 243 reg = <0x070000 0x1000>; 244 interrupts = <8>; 245 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 246 clock-names = "KMIREFCLK", "apb_pclk"; 247 }; 248 249 wdt@f0000 { 250 compatible = "arm,sp805", "arm,primecell"; 251 reg = <0x0f0000 0x10000>; 252 interrupts = <7>; 253 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 254 clock-names = "wdog_clk", "apb_pclk"; 255 }; 256 257 v2m_timer01: timer@110000 { 258 compatible = "arm,sp804", "arm,primecell"; 259 reg = <0x110000 0x10000>; 260 interrupts = <9>; 261 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; 262 clock-names = "timclken1", "timclken2", "apb_pclk"; 263 }; 264 265 v2m_timer23: timer@120000 { 266 compatible = "arm,sp804", "arm,primecell"; 267 reg = <0x120000 0x10000>; 268 interrupts = <9>; 269 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; 270 clock-names = "timclken1", "timclken2", "apb_pclk"; 271 }; 272 273 rtc@170000 { 274 compatible = "arm,pl031", "arm,primecell"; 275 reg = <0x170000 0x10000>; 276 interrupts = <0>; 277 clocks = <&soc_smc50mhz>; 278 clock-names = "apb_pclk"; 279 }; 280 281 iofpga_gpio0: gpio@1d0000 { 282 compatible = "arm,pl061", "arm,primecell"; 283 reg = <0x1d0000 0x1000>; 284 interrupts = <6>; 285 clocks = <&soc_smc50mhz>; 286 clock-names = "apb_pclk"; 287 gpio-controller; 288 #gpio-cells = <2>; 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 }; 293 }; 294 }; 295}; 296