1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. 4 * 5 * ARMv8 Foundation model DTS 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 model = "Foundation-v8A"; 16 compatible = "arm,foundation-aarch64", "arm,vexpress"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 aliases { 26 serial0 = &v2m_serial0; 27 serial1 = &v2m_serial1; 28 serial2 = &v2m_serial2; 29 serial3 = &v2m_serial3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,armv8"; 39 reg = <0x0 0x0>; 40 next-level-cache = <&L2_0>; 41 }; 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,armv8"; 45 reg = <0x0 0x1>; 46 next-level-cache = <&L2_0>; 47 }; 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,armv8"; 51 reg = <0x0 0x2>; 52 next-level-cache = <&L2_0>; 53 }; 54 cpu3: cpu@3 { 55 device_type = "cpu"; 56 compatible = "arm,armv8"; 57 reg = <0x0 0x3>; 58 next-level-cache = <&L2_0>; 59 }; 60 61 L2_0: l2-cache0 { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 }; 66 }; 67 68 memory@80000000 { 69 device_type = "memory"; 70 reg = <0x00000000 0x80000000 0 0x80000000>, 71 <0x00000008 0x80000000 0 0x80000000>; 72 }; 73 74 timer { 75 compatible = "arm,armv8-timer"; 76 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 78 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 80 clock-frequency = <100000000>; 81 }; 82 83 pmu { 84 compatible = "arm,armv8-pmuv3"; 85 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 89 }; 90 91 spe-pmu { 92 compatible = "arm,statistical-profiling-extension-v1"; 93 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 94 }; 95 96 watchdog@2a440000 { 97 compatible = "arm,sbsa-gwdt"; 98 reg = <0x0 0x2a440000 0 0x1000>, 99 <0x0 0x2a450000 0 0x1000>; 100 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 101 timeout-sec = <30>; 102 }; 103 104 v2m_clk24mhz: clock-24000000 { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <24000000>; 108 clock-output-names = "v2m:clk24mhz"; 109 }; 110 111 v2m_refclk1mhz: clock-1000000 { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <1000000>; 115 clock-output-names = "v2m:refclk1mhz"; 116 }; 117 118 v2m_refclk32khz: clock-32768 { 119 compatible = "fixed-clock"; 120 #clock-cells = <0>; 121 clock-frequency = <32768>; 122 clock-output-names = "v2m:refclk32khz"; 123 }; 124 125 bus@8000000 { 126 compatible = "arm,vexpress,v2m-p1", "simple-bus"; 127 #address-cells = <2>; /* SMB chipselect number and offset */ 128 #size-cells = <1>; 129 130 ranges = <0 0 0 0x08000000 0x04000000>, 131 <1 0 0 0x14000000 0x04000000>, 132 <2 0 0 0x18000000 0x04000000>, 133 <3 0 0 0x1c000000 0x04000000>, 134 <4 0 0 0x0c000000 0x04000000>, 135 <5 0 0 0x10000000 0x04000000>; 136 137 #interrupt-cells = <1>; 138 interrupt-map-mask = <0 0 63>; 139 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 140 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 141 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 142 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 143 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 144 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 145 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 146 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 147 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 148 <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 149 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 150 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 151 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 152 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 153 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 154 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 155 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 156 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 157 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 158 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 159 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 160 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 161 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 162 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 163 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 164 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 165 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 166 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 167 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 168 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 169 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 170 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 171 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 172 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 173 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 174 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 175 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 176 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 177 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 178 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 179 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 180 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 181 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 182 183 ethernet@202000000 { 184 compatible = "smsc,lan91c111"; 185 reg = <2 0x02000000 0x10000>; 186 interrupts = <15>; 187 }; 188 189 iofpga-bus@300000000 { 190 compatible = "simple-bus"; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0 3 0 0x200000>; 194 195 v2m_sysreg: sysreg@10000 { 196 compatible = "arm,vexpress-sysreg"; 197 reg = <0x010000 0x1000>; 198 }; 199 200 v2m_serial0: serial@90000 { 201 compatible = "arm,pl011", "arm,primecell"; 202 reg = <0x090000 0x1000>; 203 interrupts = <5>; 204 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 205 clock-names = "uartclk", "apb_pclk"; 206 }; 207 208 v2m_serial1: serial@a0000 { 209 compatible = "arm,pl011", "arm,primecell"; 210 reg = <0x0a0000 0x1000>; 211 interrupts = <6>; 212 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 213 clock-names = "uartclk", "apb_pclk"; 214 }; 215 216 v2m_serial2: serial@b0000 { 217 compatible = "arm,pl011", "arm,primecell"; 218 reg = <0x0b0000 0x1000>; 219 interrupts = <7>; 220 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 221 clock-names = "uartclk", "apb_pclk"; 222 }; 223 224 v2m_serial3: serial@c0000 { 225 compatible = "arm,pl011", "arm,primecell"; 226 reg = <0x0c0000 0x1000>; 227 interrupts = <8>; 228 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 229 clock-names = "uartclk", "apb_pclk"; 230 }; 231 232 virtio@130000 { 233 compatible = "virtio,mmio"; 234 reg = <0x130000 0x200>; 235 interrupts = <42>; 236 }; 237 }; 238 }; 239}; 240