1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (c) 2022, Arm Limited. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited. All rights reserved. 5 * 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 aliases { 16 serial0 = &uart0; 17 serial1 = &uart1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 memory@88200000 { 25 device_type = "memory"; 26 reg = <0x88200000 0x77e00000>; 27 }; 28 29 gic: interrupt-controller@1c000000 { 30 compatible = "arm,gic-400"; 31 #interrupt-cells = <3>; 32 #address-cells = <0>; 33 interrupt-controller; 34 reg = <0x1c010000 0x1000>, 35 <0x1c02f000 0x2000>, 36 <0x1c04f000 0x1000>, 37 <0x1c06f000 0x2000>; 38 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 39 IRQ_TYPE_LEVEL_LOW)>; 40 }; 41 42 L2_0: l2-cache0 { 43 compatible = "cache"; 44 cache-unified; 45 cache-level = <2>; 46 cache-size = <0x80000>; 47 cache-line-size = <64>; 48 cache-sets = <1024>; 49 }; 50 51 refclk100mhz: clock-100000000 { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <100000000>; 55 clock-output-names = "apb_pclk"; 56 }; 57 58 smbclk: clock-48000000 { 59 /* Reference 24MHz clock x 2 */ 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <48000000>; 63 clock-output-names = "smclk"; 64 }; 65 66 timer { 67 compatible = "arm,armv8-timer"; 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 72 }; 73 74 uartclk: clock-50000000 { 75 /* UART clock - 50MHz */ 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <50000000>; 79 clock-output-names = "uartclk"; 80 }; 81 82 psci { 83 compatible = "arm,psci-1.0", "arm,psci-0.2"; 84 method = "smc"; 85 }; 86 87 soc { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&gic>; 92 ranges; 93 94 timer@1a220000 { 95 compatible = "arm,armv7-timer-mem"; 96 reg = <0x1a220000 0x1000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges; 100 101 frame@1a230000 { 102 frame-number = <0>; 103 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 104 reg = <0x1a230000 0x1000>; 105 }; 106 }; 107 108 uart0: serial@1a510000 { 109 compatible = "arm,pl011", "arm,primecell"; 110 reg = <0x1a510000 0x1000>; 111 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 112 clocks = <&uartclk>, <&refclk100mhz>; 113 clock-names = "uartclk", "apb_pclk"; 114 }; 115 116 uart1: serial@1a520000 { 117 compatible = "arm,pl011", "arm,primecell"; 118 reg = <0x1a520000 0x1000>; 119 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&uartclk>, <&refclk100mhz>; 121 clock-names = "uartclk", "apb_pclk"; 122 }; 123 124 mhu_hse1: mailbox@1b820000 { 125 compatible = "arm,mhuv2-tx", "arm,primecell"; 126 reg = <0x1b820000 0x1000>; 127 clocks = <&refclk100mhz>; 128 clock-names = "apb_pclk"; 129 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 130 #mbox-cells = <2>; 131 arm,mhuv2-protocols = <0 0>; 132 secure-status = "okay"; /* secure-world-only */ 133 status = "disabled"; 134 }; 135 136 mhu_seh1: mailbox@1b830000 { 137 compatible = "arm,mhuv2-rx", "arm,primecell"; 138 reg = <0x1b830000 0x1000>; 139 clocks = <&refclk100mhz>; 140 clock-names = "apb_pclk"; 141 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 142 #mbox-cells = <2>; 143 arm,mhuv2-protocols = <0 0>; 144 secure-status = "okay"; /* secure-world-only */ 145 status = "disabled"; 146 }; 147 }; 148}; 149