1// SPDX-License-Identifier: GPL-2.0 or MIT 2/* 3 * Copyright (c) 2022, Arm Limited. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited. All rights reserved. 5 * 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 aliases { 16 serial0 = &uart0; 17 serial1 = &uart1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a35"; 31 reg = <0>; 32 next-level-cache = <&L2_0>; 33 }; 34 }; 35 36 memory@88200000 { 37 device_type = "memory"; 38 reg = <0x88200000 0x77e00000>; 39 }; 40 41 gic: interrupt-controller@1c000000 { 42 compatible = "arm,gic-400"; 43 #interrupt-cells = <3>; 44 #address-cells = <0>; 45 interrupt-controller; 46 reg = <0x1c010000 0x1000>, 47 <0x1c02f000 0x2000>, 48 <0x1c04f000 0x1000>, 49 <0x1c06f000 0x2000>; 50 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 51 IRQ_TYPE_LEVEL_LOW)>; 52 }; 53 54 L2_0: l2-cache0 { 55 compatible = "cache"; 56 cache-unified; 57 cache-level = <2>; 58 cache-size = <0x80000>; 59 cache-line-size = <64>; 60 cache-sets = <1024>; 61 }; 62 63 refclk100mhz: refclk100mhz { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <100000000>; 67 clock-output-names = "apb_pclk"; 68 }; 69 70 smbclk: refclk24mhzx2 { 71 /* Reference 24MHz clock x 2 */ 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <48000000>; 75 clock-output-names = "smclk"; 76 }; 77 78 timer { 79 compatible = "arm,armv8-timer"; 80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 81 IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 83 IRQ_TYPE_LEVEL_LOW)>, 84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 85 IRQ_TYPE_LEVEL_LOW)>, 86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 87 IRQ_TYPE_LEVEL_LOW)>; 88 }; 89 90 uartclk: uartclk { 91 /* UART clock - 50MHz */ 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <50000000>; 95 clock-output-names = "uartclk"; 96 }; 97 98 psci { 99 compatible = "arm,psci-1.0", "arm,psci-0.2"; 100 method = "smc"; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 interrupt-parent = <&gic>; 108 ranges; 109 110 timer@1a220000 { 111 compatible = "arm,armv7-timer-mem"; 112 reg = <0x1a220000 0x1000>; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 clock-frequency = <50000000>; 116 ranges; 117 118 frame@1a230000 { 119 frame-number = <0>; 120 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 121 reg = <0x1a230000 0x1000>; 122 }; 123 }; 124 125 uart0: serial@1a510000 { 126 compatible = "arm,pl011", "arm,primecell"; 127 reg = <0x1a510000 0x1000>; 128 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&uartclk>, <&refclk100mhz>; 130 clock-names = "uartclk", "apb_pclk"; 131 }; 132 133 uart1: serial@1a520000 { 134 compatible = "arm,pl011", "arm,primecell"; 135 reg = <0x1a520000 0x1000>; 136 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&uartclk>, <&refclk100mhz>; 138 clock-names = "uartclk", "apb_pclk"; 139 }; 140 141 mhu_hse1: mailbox@1b820000 { 142 compatible = "arm,mhuv2-tx", "arm,primecell"; 143 reg = <0x1b820000 0x1000>; 144 clocks = <&refclk100mhz>; 145 clock-names = "apb_pclk"; 146 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 147 #mbox-cells = <2>; 148 arm,mhuv2-protocols = <0 0>; 149 secure-status = "okay"; /* secure-world-only */ 150 status = "disabled"; 151 }; 152 153 mhu_seh1: mailbox@1b830000 { 154 compatible = "arm,mhuv2-rx", "arm,primecell"; 155 reg = <0x1b830000 0x1000>; 156 clocks = <&refclk100mhz>; 157 clock-names = "apb_pclk"; 158 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 159 #mbox-cells = <2>; 160 arm,mhuv2-protocols = <0 0>; 161 secure-status = "okay"; /* secure-world-only */ 162 status = "disabled"; 163 }; 164 }; 165}; 166