xref: /linux/arch/arm64/boot/dts/apple/t8122.dtsi (revision be150d35864ccd8d1005a12953da145013219d35)

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple T8122 "M3" SoC
 *
 * Other names: H15G
 *
 * Copyright The Asahi Linux Contributors
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/spmi/spmi.h>

/ {
	compatible = "apple,t8122", "apple,arm-platform";

	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu_e0>;
				};
				core1 {
					cpu = <&cpu_e1>;
				};
				core2 {
					cpu = <&cpu_e2>;
				};
				core3 {
					cpu = <&cpu_e3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu_p0>;
				};
				core1 {
					cpu = <&cpu_p1>;
				};
				core2 {
					cpu = <&cpu_p2>;
				};
				core3 {
					cpu = <&cpu_p3>;
				};
			};
		};

		cpu_e0: cpu@0 {
			compatible = "apple,sawtooth";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_e1: cpu@1 {
			compatible = "apple,sawtooth";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_e2: cpu@2 {
			compatible = "apple,sawtooth";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_e3: cpu@3 {
			compatible = "apple,sawtooth";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_p0: cpu@10100 {
			compatible = "apple,everest";
			device_type = "cpu";
			reg = <0x0 0x10100>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		cpu_p1: cpu@10101 {
			compatible = "apple,everest";
			device_type = "cpu";
			reg = <0x0 0x10101>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		cpu_p2: cpu@10102 {
			compatible = "apple,everest";
			device_type = "cpu";
			reg = <0x0 0x10102>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		cpu_p3: cpu@10103 {
			compatible = "apple,everest";
			device_type = "cpu";
			reg = <0x0 0x10103>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		l2_cache_0: l2-cache-0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x400000>;
		};

		l2_cache_1: l2-cache-1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x1000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&aic>;
		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
	};

	clkref: clock-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clkref";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges;
		nonposted-mmio;
		/* Required to get >32-bit DMA via DARTs */
		dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>;

		i2c0: i2c@2a1010000 {
			compatible = "apple,t8122-i2c", "apple,t8103-i2c";
			reg = <0x2 0xa1010000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 780 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c0_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c0>;
			status = "disabled";
		};

		i2c1: i2c@2a1014000 {
			compatible = "apple,t8122-i2c", "apple,t8103-i2c";
			reg = <0x2 0xa1014000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c1_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c1>;
			status = "disabled";
		};

		i2c2: i2c@2a1018000 {
			compatible = "apple,t8122-i2c", "apple,t8103-i2c";
			reg = <0x2 0xa1018000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c2_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c2>;
			status = "disabled";
		};

		i2c3: i2c@2a101c000 {
			compatible = "apple,t8122-i2c", "apple,t8103-i2c";
			reg = <0x2 0xa101c000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 783 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c3_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c3>;
			status = "disabled";
		};

		i2c4: i2c@2a1020000 {
			compatible = "apple,t8122-i2c", "apple,t8103-i2c";
			reg = <0x2 0xa1020000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c4_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c4>;
			status = "disabled";
		};

		fpwm1: pwm@2a1044000 {
			compatible = "apple,t8122-fpwm", "apple,s5l-fpwm";
			reg = <0x2 0xa1044000 0x0 0x4000>;
			power-domains = <&ps_fpwm1>;
			clocks = <&clkref>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		serial0: serial@2a1200000 {
			compatible = "apple,s5l-uart";
			reg = <0x2 0xa1200000 0x0 0x1000>;
			reg-io-width = <4>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>;
			/*
			 * TODO: figure out the clocking properly, there may
			 * be a third selectable clock.
			 */
			clocks = <&clkref>, <&clkref>;
			clock-names = "uart", "clk_uart_baud0";
			power-domains = <&ps_uart0>;
			status = "disabled";
		};

		aic: interrupt-controller@2d1000000 {
			compatible = "apple,t8122-aic3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x2 0xd1000000 0x0 0x184000>,
				<0x2 0xd1040000 0x0 0x4>;
			reg-names = "core", "event";
			power-domains = <&ps_aic>;

			affinities {
				e-core-pmu-affinity {
					apple,fiq-index = <AIC_CPU_PMU_E>;
					cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
				};

				p-core-pmu-affinity {
					apple,fiq-index = <AIC_CPU_PMU_P>;
					cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
				};
			};
		};

		pmgr: power-management@2d0700000 {
			compatible = "apple,t8122-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2 0xd0700000 0 0x14000>;
			/* child nodes are added in t8122-pmgr.dtsi */
		};

		pinctrl_ap: pinctrl@2c7100000 {
			compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl";
			reg = <0x2 0xc7100000 0x0 0x100000>;
			power-domains = <&ps_gpio>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_ap 0 0 224>;
			apple,npins = <224>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 241 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 242 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 243 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 244 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 245 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 246 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 247 IRQ_TYPE_LEVEL_HIGH>;

			i2c0_pins: i2c0-pins {
				pinmux = <APPLE_PINMUX(145, 1)>,
					 <APPLE_PINMUX(144, 1)>;
			};

			i2c1_pins: i2c1-pins {
				pinmux = <APPLE_PINMUX(147, 1)>,
					 <APPLE_PINMUX(146, 1)>;
			};

			i2c2_pins: i2c2-pins {
				pinmux = <APPLE_PINMUX(56, 1)>,
					 <APPLE_PINMUX(55, 1)>;
			};

			i2c3_pins: i2c3-pins {
				pinmux = <APPLE_PINMUX(54, 1)>,
					 <APPLE_PINMUX(53, 1)>;
			};

			i2c4_pins: i2c4-pins {
				pinmux = <APPLE_PINMUX(149, 1)>,
					 <APPLE_PINMUX(148, 1)>;
			};

		};

		pinctrl_nub: pinctrl@2e41f0000 {
			compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl";
			reg = <0x2 0xe41f0000 0x0 0x4000>;
			power-domains = <&ps_nub_gpio>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_nub 0 0 32>;
			apple,npins = <32>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 424 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 425 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 426 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 427 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 428 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 429 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 430 IRQ_TYPE_LEVEL_HIGH>;
		};

		pmgr_mini: power-management@2e4280000 {
			compatible = "apple,t8122-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2 0xe4280000 0 0x4000>;
			/* child nodes are added in t8122-pmgr.dtsi */
		};

		wdt: watchdog@2e42b0000 {
			compatible = "apple,t8122-wdt", "apple,t8103-wdt";
			reg = <0x2 0xe42b0000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 432 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_smc: pinctrl@2ec820000 {
			compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl";
			reg = <0x2 0xec820000 0x0 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_smc 0 0 18>;
			apple,npins = <18>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 497 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 498 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 499 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_aop: pinctrl@2f4824000 {
			compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl";
			reg = <0x2 0xf4824000 0x0 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aop 0 0 54>;
			apple,npins = <54>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 346 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 347 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 348 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 349 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 350 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 351 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 352 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};

#include "t8122-pmgr.dtsi"