1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8112 "M2" SoC 4 * 5 * Other names: H14G 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/spmi/spmi.h> 15 16/ { 17 compatible = "apple,t8112", "apple,arm-platform"; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu_e0>; 30 }; 31 core1 { 32 cpu = <&cpu_e1>; 33 }; 34 core2 { 35 cpu = <&cpu_e2>; 36 }; 37 core3 { 38 cpu = <&cpu_e3>; 39 }; 40 }; 41 42 cluster1 { 43 core0 { 44 cpu = <&cpu_p0>; 45 }; 46 core1 { 47 cpu = <&cpu_p1>; 48 }; 49 core2 { 50 cpu = <&cpu_p2>; 51 }; 52 core3 { 53 cpu = <&cpu_p3>; 54 }; 55 }; 56 }; 57 58 cpu_e0: cpu@0 { 59 compatible = "apple,blizzard"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "spin-table"; 63 cpu-release-addr = <0 0>; /* To be filled by loader */ 64 operating-points-v2 = <&ecluster_opp>; 65 capacity-dmips-mhz = <756>; 66 performance-domains = <&cpufreq_e>; 67 next-level-cache = <&l2_cache_0>; 68 i-cache-size = <0x20000>; 69 d-cache-size = <0x10000>; 70 }; 71 72 cpu_e1: cpu@1 { 73 compatible = "apple,blizzard"; 74 device_type = "cpu"; 75 reg = <0x0 0x1>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 78 operating-points-v2 = <&ecluster_opp>; 79 capacity-dmips-mhz = <756>; 80 performance-domains = <&cpufreq_e>; 81 next-level-cache = <&l2_cache_0>; 82 i-cache-size = <0x20000>; 83 d-cache-size = <0x10000>; 84 }; 85 86 cpu_e2: cpu@2 { 87 compatible = "apple,blizzard"; 88 device_type = "cpu"; 89 reg = <0x0 0x2>; 90 enable-method = "spin-table"; 91 cpu-release-addr = <0 0>; /* To be filled by loader */ 92 operating-points-v2 = <&ecluster_opp>; 93 capacity-dmips-mhz = <756>; 94 performance-domains = <&cpufreq_e>; 95 next-level-cache = <&l2_cache_0>; 96 i-cache-size = <0x20000>; 97 d-cache-size = <0x10000>; 98 }; 99 100 cpu_e3: cpu@3 { 101 compatible = "apple,blizzard"; 102 device_type = "cpu"; 103 reg = <0x0 0x3>; 104 enable-method = "spin-table"; 105 cpu-release-addr = <0 0>; /* To be filled by loader */ 106 operating-points-v2 = <&ecluster_opp>; 107 capacity-dmips-mhz = <756>; 108 performance-domains = <&cpufreq_e>; 109 next-level-cache = <&l2_cache_0>; 110 i-cache-size = <0x20000>; 111 d-cache-size = <0x10000>; 112 }; 113 114 cpu_p0: cpu@10100 { 115 compatible = "apple,avalanche"; 116 device_type = "cpu"; 117 reg = <0x0 0x10100>; 118 enable-method = "spin-table"; 119 cpu-release-addr = <0 0>; /* To be filled by loader */ 120 operating-points-v2 = <&pcluster_opp>; 121 capacity-dmips-mhz = <1024>; 122 performance-domains = <&cpufreq_p>; 123 next-level-cache = <&l2_cache_1>; 124 i-cache-size = <0x30000>; 125 d-cache-size = <0x20000>; 126 }; 127 128 cpu_p1: cpu@10101 { 129 compatible = "apple,avalanche"; 130 device_type = "cpu"; 131 reg = <0x0 0x10101>; 132 enable-method = "spin-table"; 133 cpu-release-addr = <0 0>; /* To be filled by loader */ 134 operating-points-v2 = <&pcluster_opp>; 135 capacity-dmips-mhz = <1024>; 136 performance-domains = <&cpufreq_p>; 137 next-level-cache = <&l2_cache_1>; 138 i-cache-size = <0x30000>; 139 d-cache-size = <0x20000>; 140 }; 141 142 cpu_p2: cpu@10102 { 143 compatible = "apple,avalanche"; 144 device_type = "cpu"; 145 reg = <0x0 0x10102>; 146 enable-method = "spin-table"; 147 cpu-release-addr = <0 0>; /* To be filled by loader */ 148 operating-points-v2 = <&pcluster_opp>; 149 capacity-dmips-mhz = <1024>; 150 performance-domains = <&cpufreq_p>; 151 next-level-cache = <&l2_cache_1>; 152 i-cache-size = <0x30000>; 153 d-cache-size = <0x20000>; 154 }; 155 156 cpu_p3: cpu@10103 { 157 compatible = "apple,avalanche"; 158 device_type = "cpu"; 159 reg = <0x0 0x10103>; 160 enable-method = "spin-table"; 161 cpu-release-addr = <0 0>; /* To be filled by loader */ 162 operating-points-v2 = <&pcluster_opp>; 163 capacity-dmips-mhz = <1024>; 164 performance-domains = <&cpufreq_p>; 165 next-level-cache = <&l2_cache_1>; 166 i-cache-size = <0x30000>; 167 d-cache-size = <0x20000>; 168 }; 169 170 l2_cache_0: l2-cache-0 { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 cache-size = <0x400000>; 175 }; 176 177 l2_cache_1: l2-cache-1 { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 cache-size = <0x1000000>; 182 }; 183 }; 184 185 ecluster_opp: opp-table-0 { 186 compatible = "operating-points-v2"; 187 opp-shared; 188 189 opp01 { 190 opp-hz = /bits/ 64 <600000000>; 191 opp-level = <1>; 192 clock-latency-ns = <7500>; 193 }; 194 opp02 { 195 opp-hz = /bits/ 64 <912000000>; 196 opp-level = <2>; 197 clock-latency-ns = <20000>; 198 }; 199 opp03 { 200 opp-hz = /bits/ 64 <1284000000>; 201 opp-level = <3>; 202 clock-latency-ns = <22000>; 203 }; 204 opp04 { 205 opp-hz = /bits/ 64 <1752000000>; 206 opp-level = <4>; 207 clock-latency-ns = <30000>; 208 }; 209 opp05 { 210 opp-hz = /bits/ 64 <2004000000>; 211 opp-level = <5>; 212 clock-latency-ns = <35000>; 213 }; 214 opp06 { 215 opp-hz = /bits/ 64 <2256000000>; 216 opp-level = <6>; 217 clock-latency-ns = <39000>; 218 }; 219 opp07 { 220 opp-hz = /bits/ 64 <2424000000>; 221 opp-level = <7>; 222 clock-latency-ns = <53000>; 223 }; 224 }; 225 226 pcluster_opp: opp-table-1 { 227 compatible = "operating-points-v2"; 228 opp-shared; 229 230 opp01 { 231 opp-hz = /bits/ 64 <660000000>; 232 opp-level = <1>; 233 clock-latency-ns = <9000>; 234 }; 235 opp02 { 236 opp-hz = /bits/ 64 <924000000>; 237 opp-level = <2>; 238 clock-latency-ns = <19000>; 239 }; 240 opp03 { 241 opp-hz = /bits/ 64 <1188000000>; 242 opp-level = <3>; 243 clock-latency-ns = <22000>; 244 }; 245 opp04 { 246 opp-hz = /bits/ 64 <1452000000>; 247 opp-level = <4>; 248 clock-latency-ns = <24000>; 249 }; 250 opp05 { 251 opp-hz = /bits/ 64 <1704000000>; 252 opp-level = <5>; 253 clock-latency-ns = <26000>; 254 }; 255 opp06 { 256 opp-hz = /bits/ 64 <1968000000>; 257 opp-level = <6>; 258 clock-latency-ns = <28000>; 259 }; 260 opp07 { 261 opp-hz = /bits/ 64 <2208000000>; 262 opp-level = <7>; 263 clock-latency-ns = <30000>; 264 }; 265 opp08 { 266 opp-hz = /bits/ 64 <2400000000>; 267 opp-level = <8>; 268 clock-latency-ns = <33000>; 269 }; 270 opp09 { 271 opp-hz = /bits/ 64 <2568000000>; 272 opp-level = <9>; 273 clock-latency-ns = <34000>; 274 }; 275 opp10 { 276 opp-hz = /bits/ 64 <2724000000>; 277 opp-level = <10>; 278 clock-latency-ns = <36000>; 279 }; 280 opp11 { 281 opp-hz = /bits/ 64 <2868000000>; 282 opp-level = <11>; 283 clock-latency-ns = <41000>; 284 }; 285 opp12 { 286 opp-hz = /bits/ 64 <2988000000>; 287 opp-level = <12>; 288 clock-latency-ns = <42000>; 289 }; 290 opp13 { 291 opp-hz = /bits/ 64 <3096000000>; 292 opp-level = <13>; 293 clock-latency-ns = <44000>; 294 }; 295 opp14 { 296 opp-hz = /bits/ 64 <3204000000>; 297 opp-level = <14>; 298 clock-latency-ns = <46000>; 299 }; 300 /* Not available until CPU deep sleep is implemented */ 301#if 0 302 opp15 { 303 opp-hz = /bits/ 64 <3324000000>; 304 opp-level = <15>; 305 clock-latency-ns = <62000>; 306 turbo-mode; 307 }; 308 opp16 { 309 opp-hz = /bits/ 64 <3408000000>; 310 opp-level = <16>; 311 clock-latency-ns = <62000>; 312 turbo-mode; 313 }; 314 opp17 { 315 opp-hz = /bits/ 64 <3504000000>; 316 opp-level = <17>; 317 clock-latency-ns = <62000>; 318 turbo-mode; 319 }; 320#endif 321 }; 322 323 timer { 324 compatible = "arm,armv8-timer"; 325 interrupt-parent = <&aic>; 326 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 327 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 328 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 329 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 330 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 331 }; 332 333 pmu-e { 334 compatible = "apple,blizzard-pmu"; 335 interrupt-parent = <&aic>; 336 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 337 }; 338 339 pmu-p { 340 compatible = "apple,avalanche-pmu"; 341 interrupt-parent = <&aic>; 342 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 343 }; 344 345 clkref: clock-ref { 346 compatible = "fixed-clock"; 347 #clock-cells = <0>; 348 clock-frequency = <24000000>; 349 clock-output-names = "clkref"; 350 }; 351 352 clk_200m: clock-200m { 353 compatible = "fixed-clock"; 354 #clock-cells = <0>; 355 clock-frequency = <200000000>; 356 clock-output-names = "clk_200m"; 357 }; 358 359 /* 360 * This is a fabulated representation of the input clock 361 * to NCO since we don't know the true clock tree. 362 */ 363 nco_clkref: clock-ref-nco { 364 compatible = "fixed-clock"; 365 #clock-cells = <0>; 366 clock-output-names = "nco_ref"; 367 }; 368 369 soc { 370 compatible = "simple-bus"; 371 #address-cells = <2>; 372 #size-cells = <2>; 373 374 ranges; 375 nonposted-mmio; 376 377 cpufreq_e: cpufreq@210e20000 { 378 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 379 reg = <0x2 0x10e20000 0 0x1000>; 380 #performance-domain-cells = <0>; 381 }; 382 383 cpufreq_p: cpufreq@211e20000 { 384 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 385 reg = <0x2 0x11e20000 0 0x1000>; 386 #performance-domain-cells = <0>; 387 }; 388 389 display_dfr: display-pipe@228200000 { 390 compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe"; 391 reg = <0x2 0x28200000 0x0 0xc000>, 392 <0x2 0x28400000 0x0 0x4000>; 393 reg-names = "be", "fe"; 394 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; 395 interrupt-parent = <&aic>; 396 interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>, 397 <AIC_IRQ 618 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "be", "fe"; 399 iommus = <&displaydfr_dart 0>; 400 status = "disabled"; 401 402 port { 403 dfr_adp_out_mipi: endpoint { 404 remote-endpoint = <&dfr_mipi_in_adp>; 405 }; 406 }; 407 }; 408 409 displaydfr_dart: iommu@228304000 { 410 compatible = "apple,t8110-dart"; 411 reg = <0x2 0x28304000 0x0 0x4000>; 412 interrupt-parent = <&aic>; 413 interrupts = <AIC_IRQ 616 IRQ_TYPE_LEVEL_HIGH>; 414 #iommu-cells = <1>; 415 power-domains = <&ps_dispdfr_fe>; 416 status = "disabled"; 417 }; 418 419 displaydfr_mipi: dsi@228600000 { 420 compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi"; 421 reg = <0x2 0x28600000 0x0 0x100000>; 422 power-domains = <&ps_mipi_dsi>; 423 status = "disabled"; 424 425 ports { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 dfr_mipi_in: port@0 { 430 reg = <0>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 dfr_mipi_in_adp: endpoint@0 { 435 reg = <0>; 436 remote-endpoint = <&dfr_adp_out_mipi>; 437 }; 438 }; 439 440 dfr_mipi_out: port@1 { 441 reg = <1>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 }; 445 }; 446 }; 447 448 sio_dart: iommu@235004000 { 449 compatible = "apple,t8110-dart"; 450 reg = <0x2 0x35004000 0x0 0x4000>; 451 interrupt-parent = <&aic>; 452 interrupts = <AIC_IRQ 769 IRQ_TYPE_LEVEL_HIGH>; 453 #iommu-cells = <1>; 454 power-domains = <&ps_sio_cpu>; 455 }; 456 457 i2c0: i2c@235010000 { 458 compatible = "apple,t8112-i2c", "apple,i2c"; 459 reg = <0x2 0x35010000 0x0 0x4000>; 460 clocks = <&clkref>; 461 interrupt-parent = <&aic>; 462 interrupts = <AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH>; 463 pinctrl-0 = <&i2c0_pins>; 464 pinctrl-names = "default"; 465 #address-cells = <0x1>; 466 #size-cells = <0x0>; 467 power-domains = <&ps_i2c0>; 468 status = "disabled"; 469 }; 470 471 i2c1: i2c@235014000 { 472 compatible = "apple,t8112-i2c", "apple,i2c"; 473 reg = <0x2 0x35014000 0x0 0x4000>; 474 clocks = <&clkref>; 475 interrupt-parent = <&aic>; 476 interrupts = <AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH>; 477 pinctrl-0 = <&i2c1_pins>; 478 pinctrl-names = "default"; 479 #address-cells = <0x1>; 480 #size-cells = <0x0>; 481 power-domains = <&ps_i2c1>; 482 status = "disabled"; 483 }; 484 485 i2c2: i2c@235018000 { 486 compatible = "apple,t8112-i2c", "apple,i2c"; 487 reg = <0x2 0x35018000 0x0 0x4000>; 488 clocks = <&clkref>; 489 interrupt-parent = <&aic>; 490 interrupts = <AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH>; 491 pinctrl-0 = <&i2c2_pins>; 492 pinctrl-names = "default"; 493 #address-cells = <0x1>; 494 #size-cells = <0x0>; 495 power-domains = <&ps_i2c2>; 496 status = "disabled"; 497 }; 498 499 i2c3: i2c@23501c000 { 500 compatible = "apple,t8112-i2c", "apple,i2c"; 501 reg = <0x2 0x3501c000 0x0 0x4000>; 502 clocks = <&clkref>; 503 interrupt-parent = <&aic>; 504 interrupts = <AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH>; 505 pinctrl-0 = <&i2c3_pins>; 506 pinctrl-names = "default"; 507 #address-cells = <0x1>; 508 #size-cells = <0x0>; 509 power-domains = <&ps_i2c3>; 510 status = "disabled"; 511 }; 512 513 i2c4: i2c@235020000 { 514 compatible = "apple,t8112-i2c", "apple,i2c"; 515 reg = <0x2 0x35020000 0x0 0x4000>; 516 clocks = <&clkref>; 517 interrupt-parent = <&aic>; 518 interrupts = <AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH>; 519 pinctrl-0 = <&i2c4_pins>; 520 pinctrl-names = "default"; 521 #address-cells = <0x1>; 522 #size-cells = <0x0>; 523 power-domains = <&ps_i2c4>; 524 status = "disabled"; 525 }; 526 527 fpwm1: pwm@235044000 { 528 compatible = "apple,t8112-fpwm", "apple,s5l-fpwm"; 529 reg = <0x2 0x35044000 0x0 0x4000>; 530 power-domains = <&ps_fpwm1>; 531 clocks = <&clkref>; 532 #pwm-cells = <2>; 533 status = "disabled"; 534 }; 535 536 spi1: spi@235104000 { 537 compatible = "apple,t8112-spi", "apple,spi"; 538 reg = <0x2 0x35104000 0x0 0x4000>; 539 interrupt-parent = <&aic>; 540 interrupts = <AIC_IRQ 749 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clk_200m>; 542 pinctrl-0 = <&spi1_pins>; 543 pinctrl-names = "default"; 544 power-domains = <&ps_spi1>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 status = "disabled"; 548 }; 549 550 spi3: spi@23510c000 { 551 compatible = "apple,t8112-spi", "apple,spi"; 552 reg = <0x2 0x3510c000 0x0 0x4000>; 553 interrupt-parent = <&aic>; 554 interrupts = <AIC_IRQ 751 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&clkref>; 556 pinctrl-0 = <&spi3_pins>; 557 pinctrl-names = "default"; 558 power-domains = <&ps_spi3>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; /* only used in J493 */ 562 }; 563 564 serial0: serial@235200000 { 565 compatible = "apple,s5l-uart"; 566 reg = <0x2 0x35200000 0x0 0x1000>; 567 reg-io-width = <4>; 568 interrupt-parent = <&aic>; 569 interrupts = <AIC_IRQ 739 IRQ_TYPE_LEVEL_HIGH>; 570 /* 571 * TODO: figure out the clocking properly, there may 572 * be a third selectable clock. 573 */ 574 clocks = <&clkref>, <&clkref>; 575 clock-names = "uart", "clk_uart_baud0"; 576 power-domains = <&ps_uart0>; 577 status = "disabled"; 578 }; 579 580 serial2: serial@235208000 { 581 compatible = "apple,s5l-uart"; 582 reg = <0x2 0x35208000 0x0 0x1000>; 583 reg-io-width = <4>; 584 interrupt-parent = <&aic>; 585 interrupts = <AIC_IRQ 741 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&clkref>, <&clkref>; 587 clock-names = "uart", "clk_uart_baud0"; 588 power-domains = <&ps_uart2>; 589 status = "disabled"; 590 }; 591 592 admac: dma-controller@238200000 { 593 compatible = "apple,t8112-admac", "apple,admac"; 594 reg = <0x2 0x38200000 0x0 0x34000>; 595 dma-channels = <24>; 596 interrupts-extended = <0>, 597 <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>, 598 <0>, 599 <0>; 600 #dma-cells = <1>; 601 iommus = <&sio_dart 2>; 602 power-domains = <&ps_sio_adma>; 603 resets = <&ps_audio_p>; 604 }; 605 606 mca: i2s@238400000 { 607 compatible = "apple,t8112-mca", "apple,mca"; 608 reg = <0x2 0x38400000 0x0 0x18000>, 609 <0x2 0x38300000 0x0 0x30000>; 610 611 interrupt-parent = <&aic>; 612 interrupts = <AIC_IRQ 753 IRQ_TYPE_LEVEL_HIGH>, 613 <AIC_IRQ 754 IRQ_TYPE_LEVEL_HIGH>, 614 <AIC_IRQ 755 IRQ_TYPE_LEVEL_HIGH>, 615 <AIC_IRQ 756 IRQ_TYPE_LEVEL_HIGH>, 616 <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>, 617 <AIC_IRQ 758 IRQ_TYPE_LEVEL_HIGH>; 618 619 resets = <&ps_audio_p>; 620 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 621 <&nco 3>, <&nco 4>, <&nco 4>; 622 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 623 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 624 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 625 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 626 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 627 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 628 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 629 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 630 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 631 "tx1a", "rx1a", "tx1b", "rx1b", 632 "tx2a", "rx2a", "tx2b", "rx2b", 633 "tx3a", "rx3a", "tx3b", "rx3b", 634 "tx4a", "rx4a", "tx4b", "rx4b", 635 "tx5a", "rx5a", "tx5b", "rx5b"; 636 637 #sound-dai-cells = <1>; 638 }; 639 640 nco: clock-controller@23b044000 { 641 compatible = "apple,t8112-nco", "apple,nco"; 642 reg = <0x2 0x3b044000 0x0 0x14000>; 643 clocks = <&nco_clkref>; 644 #clock-cells = <1>; 645 }; 646 647 aic: interrupt-controller@23b0c0000 { 648 compatible = "apple,t8112-aic", "apple,aic2"; 649 #interrupt-cells = <3>; 650 interrupt-controller; 651 reg = <0x2 0x3b0c0000 0x0 0x8000>, 652 <0x2 0x3b0c8000 0x0 0x4>; 653 reg-names = "core", "event"; 654 power-domains = <&ps_aic>; 655 656 affinities { 657 e-core-pmu-affinity { 658 apple,fiq-index = <AIC_CPU_PMU_E>; 659 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 660 }; 661 662 p-core-pmu-affinity { 663 apple,fiq-index = <AIC_CPU_PMU_P>; 664 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 665 }; 666 }; 667 }; 668 669 pmgr: power-management@23b700000 { 670 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 reg = <0x2 0x3b700000 0 0x14000>; 674 /* child nodes are added in t8103-pmgr.dtsi */ 675 }; 676 677 pinctrl_ap: pinctrl@23c100000 { 678 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 679 reg = <0x2 0x3c100000 0x0 0x100000>; 680 power-domains = <&ps_gpio>; 681 682 gpio-controller; 683 #gpio-cells = <2>; 684 gpio-ranges = <&pinctrl_ap 0 0 213>; 685 apple,npins = <213>; 686 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 interrupt-parent = <&aic>; 690 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 691 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 692 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 693 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 694 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 695 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 696 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 697 698 i2c0_pins: i2c0-pins { 699 pinmux = <APPLE_PINMUX(111, 1)>, 700 <APPLE_PINMUX(110, 1)>; 701 }; 702 703 i2c1_pins: i2c1-pins { 704 pinmux = <APPLE_PINMUX(113, 1)>, 705 <APPLE_PINMUX(112, 1)>; 706 }; 707 708 i2c2_pins: i2c2-pins { 709 pinmux = <APPLE_PINMUX(87, 1)>, 710 <APPLE_PINMUX(86, 1)>; 711 }; 712 713 i2c3_pins: i2c3-pins { 714 pinmux = <APPLE_PINMUX(54, 1)>, 715 <APPLE_PINMUX(53, 1)>; 716 }; 717 718 i2c4_pins: i2c4-pins { 719 pinmux = <APPLE_PINMUX(131, 1)>, 720 <APPLE_PINMUX(130, 1)>; 721 }; 722 723 spi1_pins: spi1-pins { 724 pinmux = <APPLE_PINMUX(46, 1)>, 725 <APPLE_PINMUX(47, 1)>, 726 <APPLE_PINMUX(48, 1)>, 727 <APPLE_PINMUX(49, 1)>; 728 }; 729 730 spi3_pins: spi3-pins { 731 pinmux = <APPLE_PINMUX(93, 1)>, 732 <APPLE_PINMUX(94, 1)>, 733 <APPLE_PINMUX(95, 1)>, 734 <APPLE_PINMUX(96, 1)>; 735 }; 736 737 pcie_pins: pcie-pins { 738 pinmux = <APPLE_PINMUX(162, 1)>, 739 <APPLE_PINMUX(163, 1)>, 740 <APPLE_PINMUX(164, 1)>; 741 // TODO: 1 more CLKREQs 742 }; 743 }; 744 745 pinctrl_nub: pinctrl@23d1f0000 { 746 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 747 reg = <0x2 0x3d1f0000 0x0 0x4000>; 748 power-domains = <&ps_nub_gpio>; 749 750 gpio-controller; 751 #gpio-cells = <2>; 752 gpio-ranges = <&pinctrl_nub 0 0 24>; 753 apple,npins = <24>; 754 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 interrupt-parent = <&aic>; 758 interrupts = <AIC_IRQ 371 IRQ_TYPE_LEVEL_HIGH>, 759 <AIC_IRQ 372 IRQ_TYPE_LEVEL_HIGH>, 760 <AIC_IRQ 373 IRQ_TYPE_LEVEL_HIGH>, 761 <AIC_IRQ 374 IRQ_TYPE_LEVEL_HIGH>, 762 <AIC_IRQ 375 IRQ_TYPE_LEVEL_HIGH>, 763 <AIC_IRQ 376 IRQ_TYPE_LEVEL_HIGH>, 764 <AIC_IRQ 377 IRQ_TYPE_LEVEL_HIGH>; 765 }; 766 767 pmgr_mini: power-management@23d280000 { 768 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 769 #address-cells = <1>; 770 #size-cells = <1>; 771 reg = <0x2 0x3d280000 0 0x4000>; 772 /* child nodes are added in t8103-pmgr.dtsi */ 773 }; 774 775 wdt: watchdog@23d2b0000 { 776 compatible = "apple,t8112-wdt", "apple,wdt"; 777 reg = <0x2 0x3d2b0000 0x0 0x4000>; 778 clocks = <&clkref>; 779 interrupt-parent = <&aic>; 780 interrupts = <AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH>; 781 }; 782 783 nub_spmi: spmi@23d714000 { 784 compatible = "apple,t8112-spmi", "apple,spmi"; 785 reg = <0x2 0x3d714000 0x0 0x100>; 786 #address-cells = <2>; 787 #size-cells = <0>; 788 789 pmic1: pmic@e { 790 compatible = "apple,stowe-pmic", "apple,spmi-nvmem"; 791 reg = <0xe SPMI_USID>; 792 793 nvmem-layout { 794 compatible = "fixed-layout"; 795 #address-cells = <1>; 796 #size-cells = <1>; 797 798 fault_shadow: fault-shadow@867b { 799 reg = <0x867b 0x10>; 800 }; 801 802 socd: socd@8b00 { 803 reg = <0x8b00 0x400>; 804 }; 805 806 boot_stage: boot-stage@f701 { 807 reg = <0xf701 0x1>; 808 }; 809 810 boot_error_count: boot-error-count@f702 { 811 reg = <0xf702 0x1>; 812 bits = <0 4>; 813 }; 814 815 panic_count: panic-count@f702 { 816 reg = <0xf702 0x1>; 817 bits = <4 4>; 818 }; 819 820 boot_error_stage: boot-error-stage@f703 { 821 reg = <0xf703 0x1>; 822 }; 823 824 shutdown_flag: shutdown-flag@f70f { 825 reg = <0xf70f 0x1>; 826 bits = <3 1>; 827 }; 828 829 pm_setting: pm-setting@f801 { 830 reg = <0xf801 0x1>; 831 }; 832 833 rtc_offset: rtc-offset@f900 { 834 reg = <0xf900 0x6>; 835 }; 836 }; 837 }; 838 }; 839 840 pinctrl_smc: pinctrl@23e820000 { 841 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 842 reg = <0x2 0x3e820000 0x0 0x4000>; 843 844 gpio-controller; 845 #gpio-cells = <2>; 846 gpio-ranges = <&pinctrl_smc 0 0 18>; 847 apple,npins = <18>; 848 849 interrupt-controller; 850 #interrupt-cells = <2>; 851 interrupt-parent = <&aic>; 852 interrupts = <AIC_IRQ 490 IRQ_TYPE_LEVEL_HIGH>, 853 <AIC_IRQ 491 IRQ_TYPE_LEVEL_HIGH>, 854 <AIC_IRQ 492 IRQ_TYPE_LEVEL_HIGH>, 855 <AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>, 856 <AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>, 857 <AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>, 858 <AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>; 859 }; 860 861 pinctrl_aop: pinctrl@24a820000 { 862 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 863 reg = <0x2 0x4a820000 0x0 0x4000>; 864 865 gpio-controller; 866 #gpio-cells = <2>; 867 gpio-ranges = <&pinctrl_aop 0 0 54>; 868 apple,npins = <54>; 869 870 interrupt-controller; 871 #interrupt-cells = <2>; 872 interrupt-parent = <&aic>; 873 interrupts = <AIC_IRQ 301 IRQ_TYPE_LEVEL_HIGH>, 874 <AIC_IRQ 302 IRQ_TYPE_LEVEL_HIGH>, 875 <AIC_IRQ 303 IRQ_TYPE_LEVEL_HIGH>, 876 <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>, 877 <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>, 878 <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>, 879 <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>; 880 }; 881 882 ans_mbox: mbox@277408000 { 883 compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; 884 reg = <0x2 0x77408000 0x0 0x4000>; 885 interrupt-parent = <&aic>; 886 interrupts = <AIC_IRQ 717 IRQ_TYPE_LEVEL_HIGH>, 887 <AIC_IRQ 718 IRQ_TYPE_LEVEL_HIGH>, 888 <AIC_IRQ 719 IRQ_TYPE_LEVEL_HIGH>, 889 <AIC_IRQ 720 IRQ_TYPE_LEVEL_HIGH>; 890 interrupt-names = "send-empty", "send-not-empty", 891 "recv-empty", "recv-not-empty"; 892 #mbox-cells = <0>; 893 power-domains = <&ps_ans>; 894 }; 895 896 sart: sart@27bc50000 { 897 compatible = "apple,t8112-sart", "apple,t6000-sart"; 898 reg = <0x2 0x7bc50000 0x0 0x10000>; 899 power-domains = <&ps_ans>; 900 }; 901 902 nvme@27bcc0000 { 903 compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2"; 904 reg = <0x2 0x7bcc0000 0x0 0x40000>, 905 <0x2 0x77400000 0x0 0x4000>; 906 reg-names = "nvme", "ans"; 907 interrupt-parent = <&aic>; 908 interrupts = <AIC_IRQ 724 IRQ_TYPE_LEVEL_HIGH>; 909 mboxes = <&ans_mbox>; 910 apple,sart = <&sart>; 911 power-domains = <&ps_ans>, <&ps_apcie_st>; 912 power-domain-names = "ans", "apcie0"; 913 resets = <&ps_ans>; 914 }; 915 916 pcie0_dart: iommu@681008000 { 917 compatible = "apple,t8110-dart"; 918 reg = <0x6 0x81008000 0x0 0x4000>; 919 #iommu-cells = <1>; 920 interrupt-parent = <&aic>; 921 interrupts = <AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH>; 922 power-domains = <&ps_apcie_gp>; 923 }; 924 925 pcie1_dart: iommu@682008000 { 926 compatible = "apple,t8110-dart"; 927 reg = <0x6 0x82008000 0x0 0x4000>; 928 #iommu-cells = <1>; 929 interrupt-parent = <&aic>; 930 interrupts = <AIC_IRQ 785 IRQ_TYPE_LEVEL_HIGH>; 931 power-domains = <&ps_apcie_gp>; 932 status = "disabled"; 933 }; 934 935 pcie2_dart: iommu@683008000 { 936 compatible = "apple,t8110-dart"; 937 reg = <0x6 0x83008000 0x0 0x4000>; 938 #iommu-cells = <1>; 939 interrupt-parent = <&aic>; 940 interrupts = <AIC_IRQ 788 IRQ_TYPE_LEVEL_HIGH>; 941 power-domains = <&ps_apcie_gp>; 942 status = "disabled"; 943 }; 944 945 pcie3_dart: iommu@684008000 { 946 compatible = "apple,t8110-dart"; 947 reg = <0x6 0x84008000 0x0 0x4000>; 948 #iommu-cells = <1>; 949 interrupt-parent = <&aic>; 950 interrupts = <AIC_IRQ 791 IRQ_TYPE_LEVEL_HIGH>; 951 power-domains = <&ps_apcie_gp>; 952 status = "disabled"; 953 }; 954 955 pcie0: pcie@690000000 { 956 compatible = "apple,t8112-pcie", "apple,pcie"; 957 device_type = "pci"; 958 959 reg = <0x6 0x90000000 0x0 0x1000000>, 960 <0x6 0x80000000 0x0 0x100000>, 961 <0x6 0x81000000 0x0 0x4000>, 962 <0x6 0x82000000 0x0 0x4000>, 963 <0x6 0x83000000 0x0 0x4000>, 964 <0x6 0x84000000 0x0 0x4000>; 965 reg-names = "config", "rc", "port0", "port1", "port2", "port3"; 966 967 interrupt-parent = <&aic>; 968 interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>, 969 <AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH>, 970 <AIC_IRQ 787 IRQ_TYPE_LEVEL_HIGH>, 971 <AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH>; 972 973 msi-controller; 974 msi-parent = <&pcie0>; 975 msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>; 976 977 iommu-map = <0x100 &pcie0_dart 0 1>, 978 <0x200 &pcie1_dart 1 1>, 979 <0x300 &pcie2_dart 2 1>, 980 <0x400 &pcie3_dart 3 1>; 981 iommu-map-mask = <0xff00>; 982 983 bus-range = <0 4>; 984 #address-cells = <3>; 985 #size-cells = <2>; 986 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 987 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 988 989 power-domains = <&ps_apcie_gp>; 990 pinctrl-0 = <&pcie_pins>; 991 pinctrl-names = "default"; 992 993 port00: pci@0,0 { 994 device_type = "pci"; 995 reg = <0x0 0x0 0x0 0x0 0x0>; 996 reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>; 997 998 #address-cells = <3>; 999 #size-cells = <2>; 1000 ranges; 1001 1002 interrupt-controller; 1003 #interrupt-cells = <1>; 1004 1005 interrupt-map-mask = <0 0 0 7>; 1006 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 1007 <0 0 0 2 &port00 0 0 0 1>, 1008 <0 0 0 3 &port00 0 0 0 2>, 1009 <0 0 0 4 &port00 0 0 0 3>; 1010 }; 1011 1012 port01: pci@1,0 { 1013 device_type = "pci"; 1014 reg = <0x800 0x0 0x0 0x0 0x0>; 1015 reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>; 1016 1017 #address-cells = <3>; 1018 #size-cells = <2>; 1019 ranges; 1020 1021 interrupt-controller; 1022 #interrupt-cells = <1>; 1023 1024 interrupt-map-mask = <0 0 0 7>; 1025 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 1026 <0 0 0 2 &port01 0 0 0 1>, 1027 <0 0 0 3 &port01 0 0 0 2>, 1028 <0 0 0 4 &port01 0 0 0 3>; 1029 1030 status = "disabled"; 1031 }; 1032 1033 port02: pci@2,0 { 1034 device_type = "pci"; 1035 reg = <0x1000 0x0 0x0 0x0 0x0>; 1036 reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>; 1037 1038 #address-cells = <3>; 1039 #size-cells = <2>; 1040 ranges; 1041 1042 interrupt-controller; 1043 #interrupt-cells = <1>; 1044 1045 interrupt-map-mask = <0 0 0 7>; 1046 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 1047 <0 0 0 2 &port02 0 0 0 1>, 1048 <0 0 0 3 &port02 0 0 0 2>, 1049 <0 0 0 4 &port02 0 0 0 3>; 1050 1051 status = "disabled"; 1052 }; 1053 1054 /* TODO: GPIO unknown */ 1055 port03: pci@3,0 { 1056 device_type = "pci"; 1057 reg = <0x1800 0x0 0x0 0x0 0x0>; 1058 //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 1059 1060 #address-cells = <3>; 1061 #size-cells = <2>; 1062 ranges; 1063 1064 interrupt-controller; 1065 #interrupt-cells = <1>; 1066 1067 interrupt-map-mask = <0 0 0 7>; 1068 interrupt-map = <0 0 0 1 &port03 0 0 0 0>, 1069 <0 0 0 2 &port03 0 0 0 1>, 1070 <0 0 0 3 &port03 0 0 0 2>, 1071 <0 0 0 4 &port03 0 0 0 3>; 1072 1073 status = "disabled"; 1074 }; 1075 }; 1076 }; 1077}; 1078 1079#include "t8112-pmgr.dtsi" 1080