1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/spmi/spmi.h> 15 16/ { 17 compatible = "apple,t8103", "apple,arm-platform"; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu_e0>; 30 }; 31 core1 { 32 cpu = <&cpu_e1>; 33 }; 34 core2 { 35 cpu = <&cpu_e2>; 36 }; 37 core3 { 38 cpu = <&cpu_e3>; 39 }; 40 }; 41 42 cluster1 { 43 core0 { 44 cpu = <&cpu_p0>; 45 }; 46 core1 { 47 cpu = <&cpu_p1>; 48 }; 49 core2 { 50 cpu = <&cpu_p2>; 51 }; 52 core3 { 53 cpu = <&cpu_p3>; 54 }; 55 }; 56 }; 57 58 cpu_e0: cpu@0 { 59 compatible = "apple,icestorm"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "spin-table"; 63 cpu-release-addr = <0 0>; /* To be filled by loader */ 64 operating-points-v2 = <&ecluster_opp>; 65 capacity-dmips-mhz = <714>; 66 performance-domains = <&cpufreq_e>; 67 next-level-cache = <&l2_cache_0>; 68 i-cache-size = <0x20000>; 69 d-cache-size = <0x10000>; 70 }; 71 72 cpu_e1: cpu@1 { 73 compatible = "apple,icestorm"; 74 device_type = "cpu"; 75 reg = <0x0 0x1>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 78 operating-points-v2 = <&ecluster_opp>; 79 capacity-dmips-mhz = <714>; 80 performance-domains = <&cpufreq_e>; 81 next-level-cache = <&l2_cache_0>; 82 i-cache-size = <0x20000>; 83 d-cache-size = <0x10000>; 84 }; 85 86 cpu_e2: cpu@2 { 87 compatible = "apple,icestorm"; 88 device_type = "cpu"; 89 reg = <0x0 0x2>; 90 enable-method = "spin-table"; 91 cpu-release-addr = <0 0>; /* To be filled by loader */ 92 operating-points-v2 = <&ecluster_opp>; 93 capacity-dmips-mhz = <714>; 94 performance-domains = <&cpufreq_e>; 95 next-level-cache = <&l2_cache_0>; 96 i-cache-size = <0x20000>; 97 d-cache-size = <0x10000>; 98 }; 99 100 cpu_e3: cpu@3 { 101 compatible = "apple,icestorm"; 102 device_type = "cpu"; 103 reg = <0x0 0x3>; 104 enable-method = "spin-table"; 105 cpu-release-addr = <0 0>; /* To be filled by loader */ 106 operating-points-v2 = <&ecluster_opp>; 107 capacity-dmips-mhz = <714>; 108 performance-domains = <&cpufreq_e>; 109 next-level-cache = <&l2_cache_0>; 110 i-cache-size = <0x20000>; 111 d-cache-size = <0x10000>; 112 }; 113 114 cpu_p0: cpu@10100 { 115 compatible = "apple,firestorm"; 116 device_type = "cpu"; 117 reg = <0x0 0x10100>; 118 enable-method = "spin-table"; 119 cpu-release-addr = <0 0>; /* To be filled by loader */ 120 operating-points-v2 = <&pcluster_opp>; 121 capacity-dmips-mhz = <1024>; 122 performance-domains = <&cpufreq_p>; 123 next-level-cache = <&l2_cache_1>; 124 i-cache-size = <0x30000>; 125 d-cache-size = <0x20000>; 126 }; 127 128 cpu_p1: cpu@10101 { 129 compatible = "apple,firestorm"; 130 device_type = "cpu"; 131 reg = <0x0 0x10101>; 132 enable-method = "spin-table"; 133 cpu-release-addr = <0 0>; /* To be filled by loader */ 134 operating-points-v2 = <&pcluster_opp>; 135 capacity-dmips-mhz = <1024>; 136 performance-domains = <&cpufreq_p>; 137 next-level-cache = <&l2_cache_1>; 138 i-cache-size = <0x30000>; 139 d-cache-size = <0x20000>; 140 }; 141 142 cpu_p2: cpu@10102 { 143 compatible = "apple,firestorm"; 144 device_type = "cpu"; 145 reg = <0x0 0x10102>; 146 enable-method = "spin-table"; 147 cpu-release-addr = <0 0>; /* To be filled by loader */ 148 operating-points-v2 = <&pcluster_opp>; 149 capacity-dmips-mhz = <1024>; 150 performance-domains = <&cpufreq_p>; 151 next-level-cache = <&l2_cache_1>; 152 i-cache-size = <0x30000>; 153 d-cache-size = <0x20000>; 154 }; 155 156 cpu_p3: cpu@10103 { 157 compatible = "apple,firestorm"; 158 device_type = "cpu"; 159 reg = <0x0 0x10103>; 160 enable-method = "spin-table"; 161 cpu-release-addr = <0 0>; /* To be filled by loader */ 162 operating-points-v2 = <&pcluster_opp>; 163 capacity-dmips-mhz = <1024>; 164 performance-domains = <&cpufreq_p>; 165 next-level-cache = <&l2_cache_1>; 166 i-cache-size = <0x30000>; 167 d-cache-size = <0x20000>; 168 }; 169 170 l2_cache_0: l2-cache-0 { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 cache-size = <0x400000>; 175 }; 176 177 l2_cache_1: l2-cache-1 { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 cache-size = <0xc00000>; 182 }; 183 }; 184 185 ecluster_opp: opp-table-0 { 186 compatible = "operating-points-v2"; 187 188 opp01 { 189 opp-hz = /bits/ 64 <600000000>; 190 opp-level = <1>; 191 clock-latency-ns = <7500>; 192 }; 193 opp02 { 194 opp-hz = /bits/ 64 <972000000>; 195 opp-level = <2>; 196 clock-latency-ns = <22000>; 197 }; 198 opp03 { 199 opp-hz = /bits/ 64 <1332000000>; 200 opp-level = <3>; 201 clock-latency-ns = <27000>; 202 }; 203 opp04 { 204 opp-hz = /bits/ 64 <1704000000>; 205 opp-level = <4>; 206 clock-latency-ns = <33000>; 207 }; 208 opp05 { 209 opp-hz = /bits/ 64 <2064000000>; 210 opp-level = <5>; 211 clock-latency-ns = <50000>; 212 }; 213 }; 214 215 pcluster_opp: opp-table-1 { 216 compatible = "operating-points-v2"; 217 218 opp01 { 219 opp-hz = /bits/ 64 <600000000>; 220 opp-level = <1>; 221 clock-latency-ns = <8000>; 222 }; 223 opp02 { 224 opp-hz = /bits/ 64 <828000000>; 225 opp-level = <2>; 226 clock-latency-ns = <19000>; 227 }; 228 opp03 { 229 opp-hz = /bits/ 64 <1056000000>; 230 opp-level = <3>; 231 clock-latency-ns = <21000>; 232 }; 233 opp04 { 234 opp-hz = /bits/ 64 <1284000000>; 235 opp-level = <4>; 236 clock-latency-ns = <23000>; 237 }; 238 opp05 { 239 opp-hz = /bits/ 64 <1500000000>; 240 opp-level = <5>; 241 clock-latency-ns = <24000>; 242 }; 243 opp06 { 244 opp-hz = /bits/ 64 <1728000000>; 245 opp-level = <6>; 246 clock-latency-ns = <29000>; 247 }; 248 opp07 { 249 opp-hz = /bits/ 64 <1956000000>; 250 opp-level = <7>; 251 clock-latency-ns = <31000>; 252 }; 253 opp08 { 254 opp-hz = /bits/ 64 <2184000000>; 255 opp-level = <8>; 256 clock-latency-ns = <34000>; 257 }; 258 opp09 { 259 opp-hz = /bits/ 64 <2388000000>; 260 opp-level = <9>; 261 clock-latency-ns = <36000>; 262 }; 263 opp10 { 264 opp-hz = /bits/ 64 <2592000000>; 265 opp-level = <10>; 266 clock-latency-ns = <51000>; 267 }; 268 opp11 { 269 opp-hz = /bits/ 64 <2772000000>; 270 opp-level = <11>; 271 clock-latency-ns = <54000>; 272 }; 273 opp12 { 274 opp-hz = /bits/ 64 <2988000000>; 275 opp-level = <12>; 276 clock-latency-ns = <55000>; 277 }; 278#if 0 279 /* Not available until CPU deep sleep is implemented */ 280 opp13 { 281 opp-hz = /bits/ 64 <3096000000>; 282 opp-level = <13>; 283 clock-latency-ns = <55000>; 284 turbo-mode; 285 }; 286 opp14 { 287 opp-hz = /bits/ 64 <3144000000>; 288 opp-level = <14>; 289 clock-latency-ns = <56000>; 290 turbo-mode; 291 }; 292 opp15 { 293 opp-hz = /bits/ 64 <3204000000>; 294 opp-level = <15>; 295 clock-latency-ns = <56000>; 296 turbo-mode; 297 }; 298#endif 299 }; 300 301 timer { 302 compatible = "arm,armv8-timer"; 303 interrupt-parent = <&aic>; 304 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 305 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 306 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 307 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 308 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 309 }; 310 311 pmu-e { 312 compatible = "apple,icestorm-pmu"; 313 interrupt-parent = <&aic>; 314 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 315 }; 316 317 pmu-p { 318 compatible = "apple,firestorm-pmu"; 319 interrupt-parent = <&aic>; 320 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 321 }; 322 323 clkref: clock-ref { 324 compatible = "fixed-clock"; 325 #clock-cells = <0>; 326 clock-frequency = <24000000>; 327 clock-output-names = "clkref"; 328 }; 329 330 clk_120m: clock-120m { 331 compatible = "fixed-clock"; 332 #clock-cells = <0>; 333 clock-frequency = <120000000>; 334 clock-output-names = "clk_120m"; 335 }; 336 337 clk_200m: clock-200m { 338 compatible = "fixed-clock"; 339 #clock-cells = <0>; 340 clock-frequency = <200000000>; 341 clock-output-names = "clk_200m"; 342 }; 343 344 /* 345 * This is a fabulated representation of the input clock 346 * to NCO since we don't know the true clock tree. 347 */ 348 nco_clkref: clock-ref-nco { 349 compatible = "fixed-clock"; 350 #clock-cells = <0>; 351 clock-output-names = "nco_ref"; 352 }; 353 354 soc { 355 compatible = "simple-bus"; 356 #address-cells = <2>; 357 #size-cells = <2>; 358 359 ranges; 360 nonposted-mmio; 361 362 cpufreq_e: performance-controller@210e20000 { 363 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 364 reg = <0x2 0x10e20000 0 0x1000>; 365 #performance-domain-cells = <0>; 366 }; 367 368 cpufreq_p: performance-controller@211e20000 { 369 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 370 reg = <0x2 0x11e20000 0 0x1000>; 371 #performance-domain-cells = <0>; 372 }; 373 374 display_dfr: display-pipe@228200000 { 375 compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe"; 376 reg = <0x2 0x28200000 0x0 0xc000>, 377 <0x2 0x28400000 0x0 0x4000>; 378 reg-names = "be", "fe"; 379 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; 380 interrupt-parent = <&aic>; 381 interrupts = <AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH>, 382 <AIC_IRQ 506 IRQ_TYPE_LEVEL_HIGH>; 383 interrupt-names = "be", "fe"; 384 iommus = <&displaydfr_dart 0>; 385 status = "disabled"; 386 387 port { 388 dfr_adp_out_mipi: endpoint { 389 remote-endpoint = <&dfr_mipi_in_adp>; 390 }; 391 }; 392 }; 393 394 displaydfr_dart: iommu@228304000 { 395 compatible = "apple,t8103-dart"; 396 reg = <0x2 0x28304000 0x0 0x4000>; 397 interrupt-parent = <&aic>; 398 interrupts = <AIC_IRQ 504 IRQ_TYPE_LEVEL_HIGH>; 399 #iommu-cells = <1>; 400 power-domains = <&ps_dispdfr_fe>; 401 status = "disabled"; 402 }; 403 404 displaydfr_mipi: dsi@228600000 { 405 compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi"; 406 reg = <0x2 0x28600000 0x0 0x100000>; 407 power-domains = <&ps_mipi_dsi>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 412 ports { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 416 dfr_mipi_in: port@0 { 417 reg = <0>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 421 dfr_mipi_in_adp: endpoint@0 { 422 reg = <0>; 423 remote-endpoint = <&dfr_adp_out_mipi>; 424 }; 425 }; 426 427 dfr_mipi_out: port@1 { 428 reg = <1>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 }; 432 }; 433 }; 434 435 sio_dart: iommu@235004000 { 436 compatible = "apple,t8103-dart"; 437 reg = <0x2 0x35004000 0x0 0x4000>; 438 interrupt-parent = <&aic>; 439 interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; 440 #iommu-cells = <1>; 441 power-domains = <&ps_sio_cpu>; 442 }; 443 444 i2c0: i2c@235010000 { 445 compatible = "apple,t8103-i2c", "apple,i2c"; 446 reg = <0x2 0x35010000 0x0 0x4000>; 447 clocks = <&clkref>; 448 interrupt-parent = <&aic>; 449 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 450 pinctrl-0 = <&i2c0_pins>; 451 pinctrl-names = "default"; 452 #address-cells = <0x1>; 453 #size-cells = <0x0>; 454 power-domains = <&ps_i2c0>; 455 }; 456 457 i2c1: i2c@235014000 { 458 compatible = "apple,t8103-i2c", "apple,i2c"; 459 reg = <0x2 0x35014000 0x0 0x4000>; 460 clocks = <&clkref>; 461 interrupt-parent = <&aic>; 462 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 463 pinctrl-0 = <&i2c1_pins>; 464 pinctrl-names = "default"; 465 #address-cells = <0x1>; 466 #size-cells = <0x0>; 467 power-domains = <&ps_i2c1>; 468 }; 469 470 i2c2: i2c@235018000 { 471 compatible = "apple,t8103-i2c", "apple,i2c"; 472 reg = <0x2 0x35018000 0x0 0x4000>; 473 clocks = <&clkref>; 474 interrupt-parent = <&aic>; 475 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 476 pinctrl-0 = <&i2c2_pins>; 477 pinctrl-names = "default"; 478 #address-cells = <0x1>; 479 #size-cells = <0x0>; 480 status = "disabled"; /* not used in all devices */ 481 power-domains = <&ps_i2c2>; 482 }; 483 484 i2c3: i2c@23501c000 { 485 compatible = "apple,t8103-i2c", "apple,i2c"; 486 reg = <0x2 0x3501c000 0x0 0x4000>; 487 clocks = <&clkref>; 488 interrupt-parent = <&aic>; 489 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 490 pinctrl-0 = <&i2c3_pins>; 491 pinctrl-names = "default"; 492 #address-cells = <0x1>; 493 #size-cells = <0x0>; 494 power-domains = <&ps_i2c3>; 495 }; 496 497 i2c4: i2c@235020000 { 498 compatible = "apple,t8103-i2c", "apple,i2c"; 499 reg = <0x2 0x35020000 0x0 0x4000>; 500 clocks = <&clkref>; 501 interrupt-parent = <&aic>; 502 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 503 pinctrl-0 = <&i2c4_pins>; 504 pinctrl-names = "default"; 505 #address-cells = <0x1>; 506 #size-cells = <0x0>; 507 power-domains = <&ps_i2c4>; 508 status = "disabled"; /* only used in J293 */ 509 }; 510 511 fpwm1: pwm@235044000 { 512 compatible = "apple,t8103-fpwm", "apple,s5l-fpwm"; 513 reg = <0x2 0x35044000 0x0 0x4000>; 514 power-domains = <&ps_fpwm1>; 515 clocks = <&clkref>; 516 #pwm-cells = <2>; 517 status = "disabled"; 518 }; 519 520 spi0: spi@235100000 { 521 compatible = "apple,t8103-spi", "apple,spi"; 522 reg = <0x2 0x35100000 0x0 0x4000>; 523 interrupt-parent = <&aic>; 524 interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clk_200m>; 526 pinctrl-0 = <&spi0_pins>; 527 pinctrl-names = "default"; 528 power-domains = <&ps_spi0>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 status = "disabled"; 532 }; 533 534 spi1: spi@235104000 { 535 compatible = "apple,t8103-spi", "apple,spi"; 536 reg = <0x2 0x35104000 0x0 0x4000>; 537 interrupt-parent = <&aic>; 538 interrupts = <AIC_IRQ 615 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clk_200m>; 540 pinctrl-0 = <&spi1_pins>; 541 pinctrl-names = "default"; 542 power-domains = <&ps_spi1>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 status = "disabled"; 546 }; 547 548 spi3: spi@23510c000 { 549 compatible = "apple,t8103-spi", "apple,spi"; 550 reg = <0x2 0x3510c000 0x0 0x4000>; 551 interrupt-parent = <&aic>; 552 interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clk_120m>; 554 pinctrl-0 = <&spi3_pins>; 555 pinctrl-names = "default"; 556 power-domains = <&ps_spi3>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 status = "disabled"; 560 }; 561 562 serial0: serial@235200000 { 563 compatible = "apple,s5l-uart"; 564 reg = <0x2 0x35200000 0x0 0x1000>; 565 reg-io-width = <4>; 566 interrupt-parent = <&aic>; 567 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 568 /* 569 * TODO: figure out the clocking properly, there may 570 * be a third selectable clock. 571 */ 572 clocks = <&clkref>, <&clkref>; 573 clock-names = "uart", "clk_uart_baud0"; 574 power-domains = <&ps_uart0>; 575 status = "disabled"; 576 }; 577 578 serial2: serial@235208000 { 579 compatible = "apple,s5l-uart"; 580 reg = <0x2 0x35208000 0x0 0x1000>; 581 reg-io-width = <4>; 582 interrupt-parent = <&aic>; 583 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&clkref>, <&clkref>; 585 clock-names = "uart", "clk_uart_baud0"; 586 power-domains = <&ps_uart2>; 587 status = "disabled"; 588 }; 589 590 admac: dma-controller@238200000 { 591 compatible = "apple,t8103-admac", "apple,admac"; 592 reg = <0x2 0x38200000 0x0 0x34000>; 593 dma-channels = <24>; 594 interrupts-extended = <0>, 595 <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, 596 <0>, 597 <0>; 598 #dma-cells = <1>; 599 iommus = <&sio_dart 2>; 600 power-domains = <&ps_sio_adma>; 601 resets = <&ps_audio_p>; 602 }; 603 604 mca: i2s@238400000 { 605 compatible = "apple,t8103-mca", "apple,mca"; 606 reg = <0x2 0x38400000 0x0 0x18000>, 607 <0x2 0x38300000 0x0 0x30000>; 608 609 interrupt-parent = <&aic>; 610 interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>, 611 <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>, 612 <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>, 613 <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>, 614 <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>, 615 <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>; 616 617 resets = <&ps_audio_p>; 618 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 619 <&nco 3>, <&nco 4>, <&nco 4>; 620 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 621 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 622 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 623 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 624 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 625 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 626 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 627 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 628 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 629 "tx1a", "rx1a", "tx1b", "rx1b", 630 "tx2a", "rx2a", "tx2b", "rx2b", 631 "tx3a", "rx3a", "tx3b", "rx3b", 632 "tx4a", "rx4a", "tx4b", "rx4b", 633 "tx5a", "rx5a", "tx5b", "rx5b"; 634 635 #sound-dai-cells = <1>; 636 }; 637 638 nco: clock-controller@23b044000 { 639 compatible = "apple,t8103-nco", "apple,nco"; 640 reg = <0x2 0x3b044000 0x0 0x14000>; 641 clocks = <&nco_clkref>; 642 #clock-cells = <1>; 643 }; 644 645 aic: interrupt-controller@23b100000 { 646 compatible = "apple,t8103-aic", "apple,aic"; 647 #interrupt-cells = <3>; 648 interrupt-controller; 649 reg = <0x2 0x3b100000 0x0 0x8000>; 650 power-domains = <&ps_aic>; 651 652 affinities { 653 e-core-pmu-affinity { 654 apple,fiq-index = <AIC_CPU_PMU_E>; 655 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 656 }; 657 658 p-core-pmu-affinity { 659 apple,fiq-index = <AIC_CPU_PMU_P>; 660 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 661 }; 662 }; 663 }; 664 665 pmgr: power-management@23b700000 { 666 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 reg = <0x2 0x3b700000 0 0x14000>; 670 }; 671 672 pinctrl_ap: pinctrl@23c100000 { 673 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 674 reg = <0x2 0x3c100000 0x0 0x100000>; 675 power-domains = <&ps_gpio>; 676 677 gpio-controller; 678 #gpio-cells = <2>; 679 gpio-ranges = <&pinctrl_ap 0 0 212>; 680 apple,npins = <212>; 681 682 interrupt-controller; 683 #interrupt-cells = <2>; 684 interrupt-parent = <&aic>; 685 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 686 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 687 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 688 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 689 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 690 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 691 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 692 693 i2c0_pins: i2c0-pins { 694 pinmux = <APPLE_PINMUX(192, 1)>, 695 <APPLE_PINMUX(188, 1)>; 696 }; 697 698 i2c1_pins: i2c1-pins { 699 pinmux = <APPLE_PINMUX(201, 1)>, 700 <APPLE_PINMUX(199, 1)>; 701 }; 702 703 i2c2_pins: i2c2-pins { 704 pinmux = <APPLE_PINMUX(163, 1)>, 705 <APPLE_PINMUX(162, 1)>; 706 }; 707 708 i2c3_pins: i2c3-pins { 709 pinmux = <APPLE_PINMUX(73, 1)>, 710 <APPLE_PINMUX(72, 1)>; 711 }; 712 713 i2c4_pins: i2c4-pins { 714 pinmux = <APPLE_PINMUX(135, 1)>, 715 <APPLE_PINMUX(134, 1)>; 716 }; 717 718 spi0_pins: spi0-pins { 719 pinmux = <APPLE_PINMUX(67, 1)>, /* CLK */ 720 <APPLE_PINMUX(68, 1)>, /* MOSI */ 721 <APPLE_PINMUX(69, 1)>; /* MISO */ 722 }; 723 724 spi1_pins: spi1-pins { 725 pinmux = <APPLE_PINMUX(42, 1)>, 726 <APPLE_PINMUX(43, 1)>, 727 <APPLE_PINMUX(44, 1)>, 728 <APPLE_PINMUX(45, 1)>; 729 }; 730 731 spi3_pins: spi3-pins { 732 pinmux = <APPLE_PINMUX(46, 1)>, 733 <APPLE_PINMUX(47, 1)>, 734 <APPLE_PINMUX(48, 1)>, 735 <APPLE_PINMUX(49, 1)>; 736 }; 737 738 pcie_pins: pcie-pins { 739 pinmux = <APPLE_PINMUX(150, 1)>, 740 <APPLE_PINMUX(151, 1)>, 741 <APPLE_PINMUX(32, 1)>; 742 }; 743 }; 744 745 nub_spmi: spmi@23d0d9300 { 746 compatible = "apple,t8103-spmi", "apple,spmi"; 747 reg = <0x2 0x3d0d9300 0x0 0x100>; 748 #address-cells = <2>; 749 #size-cells = <0>; 750 751 pmic1: pmic@f { 752 compatible = "apple,sera-pmic", "apple,spmi-nvmem"; 753 reg = <0xf SPMI_USID>; 754 755 nvmem-layout { 756 compatible = "fixed-layout"; 757 #address-cells = <1>; 758 #size-cells = <1>; 759 760 boot_stage: boot-stage@9f01 { 761 reg = <0x9f01 0x1>; 762 }; 763 764 boot_error_count: boot-error-count@9f02 { 765 reg = <0x9f02 0x1>; 766 bits = <0 4>; 767 }; 768 769 panic_count: panic-count@9f02 { 770 reg = <0x9f02 0x1>; 771 bits = <4 4>; 772 }; 773 774 boot_error_stage: boot-error-stage@9f03 { 775 reg = <0x9f03 0x1>; 776 }; 777 778 shutdown_flag: shutdown-flag@9f0f { 779 reg = <0x9f0f 0x1>; 780 bits = <3 1>; 781 }; 782 783 fault_shadow: fault-shadow@a67b { 784 reg = <0xa67b 0x10>; 785 }; 786 787 socd: socd@ab00 { 788 reg = <0xab00 0x400>; 789 }; 790 791 pm_setting: pm-setting@d001 { 792 reg = <0xd001 0x1>; 793 }; 794 795 rtc_offset: rtc-offset@d100 { 796 reg = <0xd100 0x6>; 797 }; 798 }; 799 }; 800 }; 801 802 pinctrl_nub: pinctrl@23d1f0000 { 803 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 804 reg = <0x2 0x3d1f0000 0x0 0x4000>; 805 power-domains = <&ps_nub_gpio>; 806 807 gpio-controller; 808 #gpio-cells = <2>; 809 gpio-ranges = <&pinctrl_nub 0 0 23>; 810 apple,npins = <23>; 811 812 interrupt-controller; 813 #interrupt-cells = <2>; 814 interrupt-parent = <&aic>; 815 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 816 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 817 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 818 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 819 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 820 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 821 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 822 }; 823 824 pmgr_mini: power-management@23d280000 { 825 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 826 #address-cells = <1>; 827 #size-cells = <1>; 828 reg = <0x2 0x3d280000 0 0x4000>; 829 }; 830 831 wdt: watchdog@23d2b0000 { 832 compatible = "apple,t8103-wdt", "apple,wdt"; 833 reg = <0x2 0x3d2b0000 0x0 0x4000>; 834 clocks = <&clkref>; 835 interrupt-parent = <&aic>; 836 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; 837 }; 838 839 pinctrl_smc: pinctrl@23e820000 { 840 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 841 reg = <0x2 0x3e820000 0x0 0x4000>; 842 843 gpio-controller; 844 #gpio-cells = <2>; 845 gpio-ranges = <&pinctrl_smc 0 0 16>; 846 apple,npins = <16>; 847 848 interrupt-controller; 849 #interrupt-cells = <2>; 850 interrupt-parent = <&aic>; 851 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 852 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 853 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 854 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 855 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 856 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 857 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 858 }; 859 860 pinctrl_aop: pinctrl@24a820000 { 861 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 862 reg = <0x2 0x4a820000 0x0 0x4000>; 863 864 gpio-controller; 865 #gpio-cells = <2>; 866 gpio-ranges = <&pinctrl_aop 0 0 42>; 867 apple,npins = <42>; 868 869 interrupt-controller; 870 #interrupt-cells = <2>; 871 interrupt-parent = <&aic>; 872 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 873 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 874 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 875 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 876 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 877 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 878 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 879 }; 880 881 ans_mbox: mbox@277408000 { 882 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 883 reg = <0x2 0x77408000 0x0 0x4000>; 884 interrupt-parent = <&aic>; 885 interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, 886 <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, 887 <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, 888 <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-names = "send-empty", "send-not-empty", 890 "recv-empty", "recv-not-empty"; 891 #mbox-cells = <0>; 892 power-domains = <&ps_ans2>; 893 }; 894 895 sart: iommu@27bc50000 { 896 compatible = "apple,t8103-sart"; 897 reg = <0x2 0x7bc50000 0x0 0x10000>; 898 power-domains = <&ps_ans2>; 899 }; 900 901 nvme@27bcc0000 { 902 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; 903 reg = <0x2 0x7bcc0000 0x0 0x40000>, 904 <0x2 0x77400000 0x0 0x4000>; 905 reg-names = "nvme", "ans"; 906 interrupt-parent = <&aic>; 907 interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; 908 mboxes = <&ans_mbox>; 909 apple,sart = <&sart>; 910 power-domains = <&ps_ans2>, <&ps_apcie_st>; 911 power-domain-names = "ans", "apcie0"; 912 resets = <&ps_ans2>; 913 }; 914 915 pcie0_dart_0: iommu@681008000 { 916 compatible = "apple,t8103-dart"; 917 reg = <0x6 0x81008000 0x0 0x4000>; 918 #iommu-cells = <1>; 919 interrupt-parent = <&aic>; 920 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 921 power-domains = <&ps_apcie_gp>; 922 }; 923 924 pcie0_dart_1: iommu@682008000 { 925 compatible = "apple,t8103-dart"; 926 reg = <0x6 0x82008000 0x0 0x4000>; 927 #iommu-cells = <1>; 928 interrupt-parent = <&aic>; 929 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 930 power-domains = <&ps_apcie_gp>; 931 status = "disabled"; 932 }; 933 934 pcie0_dart_2: iommu@683008000 { 935 compatible = "apple,t8103-dart"; 936 reg = <0x6 0x83008000 0x0 0x4000>; 937 #iommu-cells = <1>; 938 interrupt-parent = <&aic>; 939 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 940 power-domains = <&ps_apcie_gp>; 941 status = "disabled"; 942 }; 943 944 pcie0: pcie@690000000 { 945 compatible = "apple,t8103-pcie", "apple,pcie"; 946 device_type = "pci"; 947 948 reg = <0x6 0x90000000 0x0 0x1000000>, 949 <0x6 0x80000000 0x0 0x100000>, 950 <0x6 0x81000000 0x0 0x4000>, 951 <0x6 0x82000000 0x0 0x4000>, 952 <0x6 0x83000000 0x0 0x4000>; 953 reg-names = "config", "rc", "port0", "port1", "port2"; 954 955 interrupt-parent = <&aic>; 956 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 957 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 958 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 959 960 msi-controller; 961 msi-parent = <&pcie0>; 962 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 963 964 965 iommu-map = <0x100 &pcie0_dart_0 1 1>, 966 <0x200 &pcie0_dart_1 1 1>, 967 <0x300 &pcie0_dart_2 1 1>; 968 iommu-map-mask = <0xff00>; 969 970 bus-range = <0 3>; 971 #address-cells = <3>; 972 #size-cells = <2>; 973 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 974 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 975 976 power-domains = <&ps_apcie_gp>; 977 pinctrl-0 = <&pcie_pins>; 978 pinctrl-names = "default"; 979 980 port00: pci@0,0 { 981 device_type = "pci"; 982 reg = <0x0 0x0 0x0 0x0 0x0>; 983 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 984 985 #address-cells = <3>; 986 #size-cells = <2>; 987 ranges; 988 989 interrupt-controller; 990 #interrupt-cells = <1>; 991 992 interrupt-map-mask = <0 0 0 7>; 993 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 994 <0 0 0 2 &port00 0 0 0 1>, 995 <0 0 0 3 &port00 0 0 0 2>, 996 <0 0 0 4 &port00 0 0 0 3>; 997 }; 998 999 port01: pci@1,0 { 1000 device_type = "pci"; 1001 reg = <0x800 0x0 0x0 0x0 0x0>; 1002 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 1003 1004 #address-cells = <3>; 1005 #size-cells = <2>; 1006 ranges; 1007 1008 interrupt-controller; 1009 #interrupt-cells = <1>; 1010 1011 interrupt-map-mask = <0 0 0 7>; 1012 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 1013 <0 0 0 2 &port01 0 0 0 1>, 1014 <0 0 0 3 &port01 0 0 0 2>, 1015 <0 0 0 4 &port01 0 0 0 3>; 1016 status = "disabled"; 1017 }; 1018 1019 port02: pci@2,0 { 1020 device_type = "pci"; 1021 reg = <0x1000 0x0 0x0 0x0 0x0>; 1022 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 1023 1024 #address-cells = <3>; 1025 #size-cells = <2>; 1026 ranges; 1027 1028 interrupt-controller; 1029 #interrupt-cells = <1>; 1030 1031 interrupt-map-mask = <0 0 0 7>; 1032 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 1033 <0 0 0 2 &port02 0 0 0 1>, 1034 <0 0 0 3 &port02 0 0 0 2>, 1035 <0 0 0 4 &port02 0 0 0 3>; 1036 status = "disabled"; 1037 }; 1038 }; 1039 }; 1040}; 1041 1042#include "t8103-pmgr.dtsi" 1043