1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 compatible = "apple,t8103", "apple,arm-platform"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu_e0>; 29 }; 30 core1 { 31 cpu = <&cpu_e1>; 32 }; 33 core2 { 34 cpu = <&cpu_e2>; 35 }; 36 core3 { 37 cpu = <&cpu_e3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu_p0>; 44 }; 45 core1 { 46 cpu = <&cpu_p1>; 47 }; 48 core2 { 49 cpu = <&cpu_p2>; 50 }; 51 core3 { 52 cpu = <&cpu_p3>; 53 }; 54 }; 55 }; 56 57 cpu_e0: cpu@0 { 58 compatible = "apple,icestorm"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0 0>; /* To be filled by loader */ 63 operating-points-v2 = <&ecluster_opp>; 64 capacity-dmips-mhz = <714>; 65 performance-domains = <&cpufreq_e>; 66 next-level-cache = <&l2_cache_0>; 67 i-cache-size = <0x20000>; 68 d-cache-size = <0x10000>; 69 }; 70 71 cpu_e1: cpu@1 { 72 compatible = "apple,icestorm"; 73 device_type = "cpu"; 74 reg = <0x0 0x1>; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0 0>; /* To be filled by loader */ 77 operating-points-v2 = <&ecluster_opp>; 78 capacity-dmips-mhz = <714>; 79 performance-domains = <&cpufreq_e>; 80 next-level-cache = <&l2_cache_0>; 81 i-cache-size = <0x20000>; 82 d-cache-size = <0x10000>; 83 }; 84 85 cpu_e2: cpu@2 { 86 compatible = "apple,icestorm"; 87 device_type = "cpu"; 88 reg = <0x0 0x2>; 89 enable-method = "spin-table"; 90 cpu-release-addr = <0 0>; /* To be filled by loader */ 91 operating-points-v2 = <&ecluster_opp>; 92 capacity-dmips-mhz = <714>; 93 performance-domains = <&cpufreq_e>; 94 next-level-cache = <&l2_cache_0>; 95 i-cache-size = <0x20000>; 96 d-cache-size = <0x10000>; 97 }; 98 99 cpu_e3: cpu@3 { 100 compatible = "apple,icestorm"; 101 device_type = "cpu"; 102 reg = <0x0 0x3>; 103 enable-method = "spin-table"; 104 cpu-release-addr = <0 0>; /* To be filled by loader */ 105 operating-points-v2 = <&ecluster_opp>; 106 capacity-dmips-mhz = <714>; 107 performance-domains = <&cpufreq_e>; 108 next-level-cache = <&l2_cache_0>; 109 i-cache-size = <0x20000>; 110 d-cache-size = <0x10000>; 111 }; 112 113 cpu_p0: cpu@10100 { 114 compatible = "apple,firestorm"; 115 device_type = "cpu"; 116 reg = <0x0 0x10100>; 117 enable-method = "spin-table"; 118 cpu-release-addr = <0 0>; /* To be filled by loader */ 119 operating-points-v2 = <&pcluster_opp>; 120 capacity-dmips-mhz = <1024>; 121 performance-domains = <&cpufreq_p>; 122 next-level-cache = <&l2_cache_1>; 123 i-cache-size = <0x30000>; 124 d-cache-size = <0x20000>; 125 }; 126 127 cpu_p1: cpu@10101 { 128 compatible = "apple,firestorm"; 129 device_type = "cpu"; 130 reg = <0x0 0x10101>; 131 enable-method = "spin-table"; 132 cpu-release-addr = <0 0>; /* To be filled by loader */ 133 operating-points-v2 = <&pcluster_opp>; 134 capacity-dmips-mhz = <1024>; 135 performance-domains = <&cpufreq_p>; 136 next-level-cache = <&l2_cache_1>; 137 i-cache-size = <0x30000>; 138 d-cache-size = <0x20000>; 139 }; 140 141 cpu_p2: cpu@10102 { 142 compatible = "apple,firestorm"; 143 device_type = "cpu"; 144 reg = <0x0 0x10102>; 145 enable-method = "spin-table"; 146 cpu-release-addr = <0 0>; /* To be filled by loader */ 147 operating-points-v2 = <&pcluster_opp>; 148 capacity-dmips-mhz = <1024>; 149 performance-domains = <&cpufreq_p>; 150 next-level-cache = <&l2_cache_1>; 151 i-cache-size = <0x30000>; 152 d-cache-size = <0x20000>; 153 }; 154 155 cpu_p3: cpu@10103 { 156 compatible = "apple,firestorm"; 157 device_type = "cpu"; 158 reg = <0x0 0x10103>; 159 enable-method = "spin-table"; 160 cpu-release-addr = <0 0>; /* To be filled by loader */ 161 operating-points-v2 = <&pcluster_opp>; 162 capacity-dmips-mhz = <1024>; 163 performance-domains = <&cpufreq_p>; 164 next-level-cache = <&l2_cache_1>; 165 i-cache-size = <0x30000>; 166 d-cache-size = <0x20000>; 167 }; 168 169 l2_cache_0: l2-cache-0 { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 cache-size = <0x400000>; 174 }; 175 176 l2_cache_1: l2-cache-1 { 177 compatible = "cache"; 178 cache-level = <2>; 179 cache-unified; 180 cache-size = <0xc00000>; 181 }; 182 }; 183 184 ecluster_opp: opp-table-0 { 185 compatible = "operating-points-v2"; 186 187 opp01 { 188 opp-hz = /bits/ 64 <600000000>; 189 opp-level = <1>; 190 clock-latency-ns = <7500>; 191 }; 192 opp02 { 193 opp-hz = /bits/ 64 <972000000>; 194 opp-level = <2>; 195 clock-latency-ns = <22000>; 196 }; 197 opp03 { 198 opp-hz = /bits/ 64 <1332000000>; 199 opp-level = <3>; 200 clock-latency-ns = <27000>; 201 }; 202 opp04 { 203 opp-hz = /bits/ 64 <1704000000>; 204 opp-level = <4>; 205 clock-latency-ns = <33000>; 206 }; 207 opp05 { 208 opp-hz = /bits/ 64 <2064000000>; 209 opp-level = <5>; 210 clock-latency-ns = <50000>; 211 }; 212 }; 213 214 pcluster_opp: opp-table-1 { 215 compatible = "operating-points-v2"; 216 217 opp01 { 218 opp-hz = /bits/ 64 <600000000>; 219 opp-level = <1>; 220 clock-latency-ns = <8000>; 221 }; 222 opp02 { 223 opp-hz = /bits/ 64 <828000000>; 224 opp-level = <2>; 225 clock-latency-ns = <19000>; 226 }; 227 opp03 { 228 opp-hz = /bits/ 64 <1056000000>; 229 opp-level = <3>; 230 clock-latency-ns = <21000>; 231 }; 232 opp04 { 233 opp-hz = /bits/ 64 <1284000000>; 234 opp-level = <4>; 235 clock-latency-ns = <23000>; 236 }; 237 opp05 { 238 opp-hz = /bits/ 64 <1500000000>; 239 opp-level = <5>; 240 clock-latency-ns = <24000>; 241 }; 242 opp06 { 243 opp-hz = /bits/ 64 <1728000000>; 244 opp-level = <6>; 245 clock-latency-ns = <29000>; 246 }; 247 opp07 { 248 opp-hz = /bits/ 64 <1956000000>; 249 opp-level = <7>; 250 clock-latency-ns = <31000>; 251 }; 252 opp08 { 253 opp-hz = /bits/ 64 <2184000000>; 254 opp-level = <8>; 255 clock-latency-ns = <34000>; 256 }; 257 opp09 { 258 opp-hz = /bits/ 64 <2388000000>; 259 opp-level = <9>; 260 clock-latency-ns = <36000>; 261 }; 262 opp10 { 263 opp-hz = /bits/ 64 <2592000000>; 264 opp-level = <10>; 265 clock-latency-ns = <51000>; 266 }; 267 opp11 { 268 opp-hz = /bits/ 64 <2772000000>; 269 opp-level = <11>; 270 clock-latency-ns = <54000>; 271 }; 272 opp12 { 273 opp-hz = /bits/ 64 <2988000000>; 274 opp-level = <12>; 275 clock-latency-ns = <55000>; 276 }; 277#if 0 278 /* Not available until CPU deep sleep is implemented */ 279 opp13 { 280 opp-hz = /bits/ 64 <3096000000>; 281 opp-level = <13>; 282 clock-latency-ns = <55000>; 283 turbo-mode; 284 }; 285 opp14 { 286 opp-hz = /bits/ 64 <3144000000>; 287 opp-level = <14>; 288 clock-latency-ns = <56000>; 289 turbo-mode; 290 }; 291 opp15 { 292 opp-hz = /bits/ 64 <3204000000>; 293 opp-level = <15>; 294 clock-latency-ns = <56000>; 295 turbo-mode; 296 }; 297#endif 298 }; 299 300 timer { 301 compatible = "arm,armv8-timer"; 302 interrupt-parent = <&aic>; 303 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 304 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 305 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 306 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 307 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 308 }; 309 310 pmu-e { 311 compatible = "apple,icestorm-pmu"; 312 interrupt-parent = <&aic>; 313 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 pmu-p { 317 compatible = "apple,firestorm-pmu"; 318 interrupt-parent = <&aic>; 319 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 320 }; 321 322 clkref: clock-ref { 323 compatible = "fixed-clock"; 324 #clock-cells = <0>; 325 clock-frequency = <24000000>; 326 clock-output-names = "clkref"; 327 }; 328 329 /* 330 * This is a fabulated representation of the input clock 331 * to NCO since we don't know the true clock tree. 332 */ 333 nco_clkref: clock-ref-nco { 334 compatible = "fixed-clock"; 335 #clock-cells = <0>; 336 clock-output-names = "nco_ref"; 337 }; 338 339 soc { 340 compatible = "simple-bus"; 341 #address-cells = <2>; 342 #size-cells = <2>; 343 344 ranges; 345 nonposted-mmio; 346 347 cpufreq_e: performance-controller@210e20000 { 348 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 349 reg = <0x2 0x10e20000 0 0x1000>; 350 #performance-domain-cells = <0>; 351 }; 352 353 cpufreq_p: performance-controller@211e20000 { 354 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 355 reg = <0x2 0x11e20000 0 0x1000>; 356 #performance-domain-cells = <0>; 357 }; 358 359 sio_dart: iommu@235004000 { 360 compatible = "apple,t8103-dart"; 361 reg = <0x2 0x35004000 0x0 0x4000>; 362 interrupt-parent = <&aic>; 363 interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; 364 #iommu-cells = <1>; 365 power-domains = <&ps_sio_cpu>; 366 }; 367 368 i2c0: i2c@235010000 { 369 compatible = "apple,t8103-i2c", "apple,i2c"; 370 reg = <0x2 0x35010000 0x0 0x4000>; 371 clocks = <&clkref>; 372 interrupt-parent = <&aic>; 373 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 374 pinctrl-0 = <&i2c0_pins>; 375 pinctrl-names = "default"; 376 #address-cells = <0x1>; 377 #size-cells = <0x0>; 378 power-domains = <&ps_i2c0>; 379 }; 380 381 i2c1: i2c@235014000 { 382 compatible = "apple,t8103-i2c", "apple,i2c"; 383 reg = <0x2 0x35014000 0x0 0x4000>; 384 clocks = <&clkref>; 385 interrupt-parent = <&aic>; 386 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 387 pinctrl-0 = <&i2c1_pins>; 388 pinctrl-names = "default"; 389 #address-cells = <0x1>; 390 #size-cells = <0x0>; 391 power-domains = <&ps_i2c1>; 392 }; 393 394 i2c2: i2c@235018000 { 395 compatible = "apple,t8103-i2c", "apple,i2c"; 396 reg = <0x2 0x35018000 0x0 0x4000>; 397 clocks = <&clkref>; 398 interrupt-parent = <&aic>; 399 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 400 pinctrl-0 = <&i2c2_pins>; 401 pinctrl-names = "default"; 402 #address-cells = <0x1>; 403 #size-cells = <0x0>; 404 status = "disabled"; /* not used in all devices */ 405 power-domains = <&ps_i2c2>; 406 }; 407 408 i2c3: i2c@23501c000 { 409 compatible = "apple,t8103-i2c", "apple,i2c"; 410 reg = <0x2 0x3501c000 0x0 0x4000>; 411 clocks = <&clkref>; 412 interrupt-parent = <&aic>; 413 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 414 pinctrl-0 = <&i2c3_pins>; 415 pinctrl-names = "default"; 416 #address-cells = <0x1>; 417 #size-cells = <0x0>; 418 power-domains = <&ps_i2c3>; 419 }; 420 421 i2c4: i2c@235020000 { 422 compatible = "apple,t8103-i2c", "apple,i2c"; 423 reg = <0x2 0x35020000 0x0 0x4000>; 424 clocks = <&clkref>; 425 interrupt-parent = <&aic>; 426 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 427 pinctrl-0 = <&i2c4_pins>; 428 pinctrl-names = "default"; 429 #address-cells = <0x1>; 430 #size-cells = <0x0>; 431 power-domains = <&ps_i2c4>; 432 status = "disabled"; /* only used in J293 */ 433 }; 434 435 fpwm1: pwm@235044000 { 436 compatible = "apple,t8103-fpwm", "apple,s5l-fpwm"; 437 reg = <0x2 0x35044000 0x0 0x4000>; 438 power-domains = <&ps_fpwm1>; 439 clocks = <&clkref>; 440 #pwm-cells = <2>; 441 status = "disabled"; 442 }; 443 444 serial0: serial@235200000 { 445 compatible = "apple,s5l-uart"; 446 reg = <0x2 0x35200000 0x0 0x1000>; 447 reg-io-width = <4>; 448 interrupt-parent = <&aic>; 449 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 450 /* 451 * TODO: figure out the clocking properly, there may 452 * be a third selectable clock. 453 */ 454 clocks = <&clkref>, <&clkref>; 455 clock-names = "uart", "clk_uart_baud0"; 456 power-domains = <&ps_uart0>; 457 status = "disabled"; 458 }; 459 460 serial2: serial@235208000 { 461 compatible = "apple,s5l-uart"; 462 reg = <0x2 0x35208000 0x0 0x1000>; 463 reg-io-width = <4>; 464 interrupt-parent = <&aic>; 465 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&clkref>, <&clkref>; 467 clock-names = "uart", "clk_uart_baud0"; 468 power-domains = <&ps_uart2>; 469 status = "disabled"; 470 }; 471 472 admac: dma-controller@238200000 { 473 compatible = "apple,t8103-admac", "apple,admac"; 474 reg = <0x2 0x38200000 0x0 0x34000>; 475 dma-channels = <24>; 476 interrupts-extended = <0>, 477 <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, 478 <0>, 479 <0>; 480 #dma-cells = <1>; 481 iommus = <&sio_dart 2>; 482 power-domains = <&ps_sio_adma>; 483 resets = <&ps_audio_p>; 484 }; 485 486 mca: i2s@238400000 { 487 compatible = "apple,t8103-mca", "apple,mca"; 488 reg = <0x2 0x38400000 0x0 0x18000>, 489 <0x2 0x38300000 0x0 0x30000>; 490 491 interrupt-parent = <&aic>; 492 interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>, 493 <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>, 494 <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>, 495 <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>, 496 <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>, 497 <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>; 498 499 resets = <&ps_audio_p>; 500 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 501 <&nco 3>, <&nco 4>, <&nco 4>; 502 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 503 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 504 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 505 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 506 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 507 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 508 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 509 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 510 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 511 "tx1a", "rx1a", "tx1b", "rx1b", 512 "tx2a", "rx2a", "tx2b", "rx2b", 513 "tx3a", "rx3a", "tx3b", "rx3b", 514 "tx4a", "rx4a", "tx4b", "rx4b", 515 "tx5a", "rx5a", "tx5b", "rx5b"; 516 517 #sound-dai-cells = <1>; 518 }; 519 520 nco: clock-controller@23b044000 { 521 compatible = "apple,t8103-nco", "apple,nco"; 522 reg = <0x2 0x3b044000 0x0 0x14000>; 523 clocks = <&nco_clkref>; 524 #clock-cells = <1>; 525 }; 526 527 aic: interrupt-controller@23b100000 { 528 compatible = "apple,t8103-aic", "apple,aic"; 529 #interrupt-cells = <3>; 530 interrupt-controller; 531 reg = <0x2 0x3b100000 0x0 0x8000>; 532 power-domains = <&ps_aic>; 533 534 affinities { 535 e-core-pmu-affinity { 536 apple,fiq-index = <AIC_CPU_PMU_E>; 537 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 538 }; 539 540 p-core-pmu-affinity { 541 apple,fiq-index = <AIC_CPU_PMU_P>; 542 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 543 }; 544 }; 545 }; 546 547 pmgr: power-management@23b700000 { 548 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 549 #address-cells = <1>; 550 #size-cells = <1>; 551 reg = <0x2 0x3b700000 0 0x14000>; 552 }; 553 554 pinctrl_ap: pinctrl@23c100000 { 555 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 556 reg = <0x2 0x3c100000 0x0 0x100000>; 557 power-domains = <&ps_gpio>; 558 559 gpio-controller; 560 #gpio-cells = <2>; 561 gpio-ranges = <&pinctrl_ap 0 0 212>; 562 apple,npins = <212>; 563 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 interrupt-parent = <&aic>; 567 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 568 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 569 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 570 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 571 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 572 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 573 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 574 575 i2c0_pins: i2c0-pins { 576 pinmux = <APPLE_PINMUX(192, 1)>, 577 <APPLE_PINMUX(188, 1)>; 578 }; 579 580 i2c1_pins: i2c1-pins { 581 pinmux = <APPLE_PINMUX(201, 1)>, 582 <APPLE_PINMUX(199, 1)>; 583 }; 584 585 i2c2_pins: i2c2-pins { 586 pinmux = <APPLE_PINMUX(163, 1)>, 587 <APPLE_PINMUX(162, 1)>; 588 }; 589 590 i2c3_pins: i2c3-pins { 591 pinmux = <APPLE_PINMUX(73, 1)>, 592 <APPLE_PINMUX(72, 1)>; 593 }; 594 595 i2c4_pins: i2c4-pins { 596 pinmux = <APPLE_PINMUX(135, 1)>, 597 <APPLE_PINMUX(134, 1)>; 598 }; 599 600 pcie_pins: pcie-pins { 601 pinmux = <APPLE_PINMUX(150, 1)>, 602 <APPLE_PINMUX(151, 1)>, 603 <APPLE_PINMUX(32, 1)>; 604 }; 605 }; 606 607 pinctrl_nub: pinctrl@23d1f0000 { 608 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 609 reg = <0x2 0x3d1f0000 0x0 0x4000>; 610 power-domains = <&ps_nub_gpio>; 611 612 gpio-controller; 613 #gpio-cells = <2>; 614 gpio-ranges = <&pinctrl_nub 0 0 23>; 615 apple,npins = <23>; 616 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 interrupt-parent = <&aic>; 620 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 621 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 622 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 623 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 624 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 625 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 626 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 627 }; 628 629 pmgr_mini: power-management@23d280000 { 630 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 reg = <0x2 0x3d280000 0 0x4000>; 634 }; 635 636 wdt: watchdog@23d2b0000 { 637 compatible = "apple,t8103-wdt", "apple,wdt"; 638 reg = <0x2 0x3d2b0000 0x0 0x4000>; 639 clocks = <&clkref>; 640 interrupt-parent = <&aic>; 641 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; 642 }; 643 644 pinctrl_smc: pinctrl@23e820000 { 645 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 646 reg = <0x2 0x3e820000 0x0 0x4000>; 647 648 gpio-controller; 649 #gpio-cells = <2>; 650 gpio-ranges = <&pinctrl_smc 0 0 16>; 651 apple,npins = <16>; 652 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 interrupt-parent = <&aic>; 656 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 657 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 658 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 659 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 660 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 661 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 662 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 663 }; 664 665 pinctrl_aop: pinctrl@24a820000 { 666 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 667 reg = <0x2 0x4a820000 0x0 0x4000>; 668 669 gpio-controller; 670 #gpio-cells = <2>; 671 gpio-ranges = <&pinctrl_aop 0 0 42>; 672 apple,npins = <42>; 673 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 interrupt-parent = <&aic>; 677 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 678 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 679 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 680 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 681 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 682 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 683 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 684 }; 685 686 ans_mbox: mbox@277408000 { 687 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 688 reg = <0x2 0x77408000 0x0 0x4000>; 689 interrupt-parent = <&aic>; 690 interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, 691 <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, 692 <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, 693 <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-names = "send-empty", "send-not-empty", 695 "recv-empty", "recv-not-empty"; 696 #mbox-cells = <0>; 697 power-domains = <&ps_ans2>; 698 }; 699 700 sart: iommu@27bc50000 { 701 compatible = "apple,t8103-sart"; 702 reg = <0x2 0x7bc50000 0x0 0x10000>; 703 power-domains = <&ps_ans2>; 704 }; 705 706 nvme@27bcc0000 { 707 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; 708 reg = <0x2 0x7bcc0000 0x0 0x40000>, 709 <0x2 0x77400000 0x0 0x4000>; 710 reg-names = "nvme", "ans"; 711 interrupt-parent = <&aic>; 712 interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; 713 mboxes = <&ans_mbox>; 714 apple,sart = <&sart>; 715 power-domains = <&ps_ans2>, <&ps_apcie_st>; 716 power-domain-names = "ans", "apcie0"; 717 resets = <&ps_ans2>; 718 }; 719 720 pcie0_dart_0: iommu@681008000 { 721 compatible = "apple,t8103-dart"; 722 reg = <0x6 0x81008000 0x0 0x4000>; 723 #iommu-cells = <1>; 724 interrupt-parent = <&aic>; 725 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 726 power-domains = <&ps_apcie_gp>; 727 }; 728 729 pcie0_dart_1: iommu@682008000 { 730 compatible = "apple,t8103-dart"; 731 reg = <0x6 0x82008000 0x0 0x4000>; 732 #iommu-cells = <1>; 733 interrupt-parent = <&aic>; 734 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 735 power-domains = <&ps_apcie_gp>; 736 status = "disabled"; 737 }; 738 739 pcie0_dart_2: iommu@683008000 { 740 compatible = "apple,t8103-dart"; 741 reg = <0x6 0x83008000 0x0 0x4000>; 742 #iommu-cells = <1>; 743 interrupt-parent = <&aic>; 744 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 745 power-domains = <&ps_apcie_gp>; 746 status = "disabled"; 747 }; 748 749 pcie0: pcie@690000000 { 750 compatible = "apple,t8103-pcie", "apple,pcie"; 751 device_type = "pci"; 752 753 reg = <0x6 0x90000000 0x0 0x1000000>, 754 <0x6 0x80000000 0x0 0x100000>, 755 <0x6 0x81000000 0x0 0x4000>, 756 <0x6 0x82000000 0x0 0x4000>, 757 <0x6 0x83000000 0x0 0x4000>; 758 reg-names = "config", "rc", "port0", "port1", "port2"; 759 760 interrupt-parent = <&aic>; 761 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 762 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 763 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 764 765 msi-controller; 766 msi-parent = <&pcie0>; 767 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 768 769 770 iommu-map = <0x100 &pcie0_dart_0 1 1>, 771 <0x200 &pcie0_dart_1 1 1>, 772 <0x300 &pcie0_dart_2 1 1>; 773 iommu-map-mask = <0xff00>; 774 775 bus-range = <0 3>; 776 #address-cells = <3>; 777 #size-cells = <2>; 778 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 779 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 780 781 power-domains = <&ps_apcie_gp>; 782 pinctrl-0 = <&pcie_pins>; 783 pinctrl-names = "default"; 784 785 port00: pci@0,0 { 786 device_type = "pci"; 787 reg = <0x0 0x0 0x0 0x0 0x0>; 788 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 789 790 #address-cells = <3>; 791 #size-cells = <2>; 792 ranges; 793 794 interrupt-controller; 795 #interrupt-cells = <1>; 796 797 interrupt-map-mask = <0 0 0 7>; 798 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 799 <0 0 0 2 &port00 0 0 0 1>, 800 <0 0 0 3 &port00 0 0 0 2>, 801 <0 0 0 4 &port00 0 0 0 3>; 802 }; 803 804 port01: pci@1,0 { 805 device_type = "pci"; 806 reg = <0x800 0x0 0x0 0x0 0x0>; 807 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 808 809 #address-cells = <3>; 810 #size-cells = <2>; 811 ranges; 812 813 interrupt-controller; 814 #interrupt-cells = <1>; 815 816 interrupt-map-mask = <0 0 0 7>; 817 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 818 <0 0 0 2 &port01 0 0 0 1>, 819 <0 0 0 3 &port01 0 0 0 2>, 820 <0 0 0 4 &port01 0 0 0 3>; 821 status = "disabled"; 822 }; 823 824 port02: pci@2,0 { 825 device_type = "pci"; 826 reg = <0x1000 0x0 0x0 0x0 0x0>; 827 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 828 829 #address-cells = <3>; 830 #size-cells = <2>; 831 ranges; 832 833 interrupt-controller; 834 #interrupt-cells = <1>; 835 836 interrupt-map-mask = <0 0 0 7>; 837 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 838 <0 0 0 2 &port02 0 0 0 1>, 839 <0 0 0 3 &port02 0 0 0 2>, 840 <0 0 0 4 &port02 0 0 0 3>; 841 status = "disabled"; 842 }; 843 }; 844 }; 845}; 846 847#include "t8103-pmgr.dtsi" 848