1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8015 "A11" SoC 4 * 5 * Other names: H10, "Skye" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu-map { 32 cluster0 { 33 core0 { 34 cpu = <&cpu_e0>; 35 }; 36 core1 { 37 cpu = <&cpu_e1>; 38 }; 39 core2 { 40 cpu = <&cpu_e2>; 41 }; 42 core3 { 43 cpu = <&cpu_e3>; 44 }; 45 }; 46 47 cluster1 { 48 core0 { 49 cpu = <&cpu_p0>; 50 }; 51 core1 { 52 cpu = <&cpu_p1>; 53 }; 54 }; 55 }; 56 57 cpu_e0: cpu@0 { 58 compatible = "apple,mistral"; 59 reg = <0x0 0x0>; 60 cpu-release-addr = <0 0>; /* To be filled by loader */ 61 performance-domains = <&cpufreq_e>; 62 operating-points-v2 = <&mistral_opp>; 63 capacity-dmips-mhz = <633>; 64 enable-method = "spin-table"; 65 device_type = "cpu"; 66 next-level-cache = <&l2_cache_0>; 67 i-cache-size = <0x8000>; 68 d-cache-size = <0x8000>; 69 }; 70 71 cpu_e1: cpu@1 { 72 compatible = "apple,mistral"; 73 reg = <0x0 0x1>; 74 cpu-release-addr = <0 0>; /* To be filled by loader */ 75 performance-domains = <&cpufreq_e>; 76 operating-points-v2 = <&mistral_opp>; 77 capacity-dmips-mhz = <633>; 78 enable-method = "spin-table"; 79 device_type = "cpu"; 80 next-level-cache = <&l2_cache_0>; 81 i-cache-size = <0x8000>; 82 d-cache-size = <0x8000>; 83 }; 84 85 cpu_e2: cpu@2 { 86 compatible = "apple,mistral"; 87 reg = <0x0 0x2>; 88 cpu-release-addr = <0 0>; /* To be filled by loader */ 89 performance-domains = <&cpufreq_e>; 90 operating-points-v2 = <&mistral_opp>; 91 capacity-dmips-mhz = <633>; 92 enable-method = "spin-table"; 93 device_type = "cpu"; 94 next-level-cache = <&l2_cache_0>; 95 i-cache-size = <0x8000>; 96 d-cache-size = <0x8000>; 97 }; 98 99 cpu_e3: cpu@3 { 100 compatible = "apple,mistral"; 101 reg = <0x0 0x3>; 102 cpu-release-addr = <0 0>; /* To be filled by loader */ 103 performance-domains = <&cpufreq_e>; 104 operating-points-v2 = <&mistral_opp>; 105 capacity-dmips-mhz = <633>; 106 enable-method = "spin-table"; 107 device_type = "cpu"; 108 next-level-cache = <&l2_cache_0>; 109 i-cache-size = <0x8000>; 110 d-cache-size = <0x8000>; 111 }; 112 113 cpu_p0: cpu@10004 { 114 compatible = "apple,monsoon"; 115 reg = <0x0 0x10004>; 116 cpu-release-addr = <0 0>; /* To be filled by loader */ 117 performance-domains = <&cpufreq_p>; 118 operating-points-v2 = <&monsoon_opp>; 119 capacity-dmips-mhz = <1024>; 120 enable-method = "spin-table"; 121 device_type = "cpu"; 122 next-level-cache = <&l2_cache_1>; 123 i-cache-size = <0x10000>; 124 d-cache-size = <0x10000>; 125 }; 126 127 cpu_p1: cpu@10005 { 128 compatible = "apple,monsoon"; 129 reg = <0x0 0x10005>; 130 cpu-release-addr = <0 0>; /* To be filled by loader */ 131 performance-domains = <&cpufreq_p>; 132 operating-points-v2 = <&monsoon_opp>; 133 capacity-dmips-mhz = <1024>; 134 enable-method = "spin-table"; 135 device_type = "cpu"; 136 next-level-cache = <&l2_cache_1>; 137 i-cache-size = <0x10000>; 138 d-cache-size = <0x10000>; 139 }; 140 141 l2_cache_0: l2-cache-0 { 142 compatible = "cache"; 143 cache-level = <2>; 144 cache-unified; 145 cache-size = <0x100000>; 146 }; 147 148 l2_cache_1: l2-cache-1 { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 cache-size = <0x800000>; 153 }; 154 }; 155 156 mistral_opp: opp-table-0 { 157 compatible = "operating-points-v2"; 158 159 opp01 { 160 opp-hz = /bits/ 64 <300000000>; 161 opp-level = <1>; 162 clock-latency-ns = <1800>; 163 }; 164 opp02 { 165 opp-hz = /bits/ 64 <453000000>; 166 opp-level = <2>; 167 clock-latency-ns = <140000>; 168 }; 169 opp03 { 170 opp-hz = /bits/ 64 <672000000>; 171 opp-level = <3>; 172 clock-latency-ns = <105000>; 173 }; 174 opp04 { 175 opp-hz = /bits/ 64 <972000000>; 176 opp-level = <4>; 177 clock-latency-ns = <115000>; 178 }; 179 opp05 { 180 opp-hz = /bits/ 64 <1272000000>; 181 opp-level = <5>; 182 clock-latency-ns = <125000>; 183 }; 184 opp06 { 185 opp-hz = /bits/ 64 <1572000000>; 186 opp-level = <6>; 187 clock-latency-ns = <135000>; 188 }; 189#if 0 190 /* Not available until CPU deep sleep is implemented */ 191 opp07 { 192 opp-hz = /bits/ 64 <1680000000>; 193 opp-level = <7>; 194 clock-latency-ns = <135000>; 195 turbo-mode; 196 }; 197#endif 198 }; 199 200 monsoon_opp: opp-table-1 { 201 compatible = "operating-points-v2"; 202 203 opp01 { 204 opp-hz = /bits/ 64 <300000000>; 205 opp-level = <1>; 206 clock-latency-ns = <1400>; 207 }; 208 opp02 { 209 opp-hz = /bits/ 64 <453000000>; 210 opp-level = <2>; 211 clock-latency-ns = <140000>; 212 }; 213 opp03 { 214 opp-hz = /bits/ 64 <853000000>; 215 opp-level = <3>; 216 clock-latency-ns = <110000>; 217 }; 218 opp04 { 219 opp-hz = /bits/ 64 <1332000000>; 220 opp-level = <4>; 221 clock-latency-ns = <110000>; 222 }; 223 opp05 { 224 opp-hz = /bits/ 64 <1812000000>; 225 opp-level = <5>; 226 clock-latency-ns = <125000>; 227 }; 228 opp06 { 229 opp-hz = /bits/ 64 <2064000000>; 230 opp-level = <6>; 231 clock-latency-ns = <130000>; 232 }; 233 opp07 { 234 opp-hz = /bits/ 64 <2304000000>; 235 opp-level = <7>; 236 clock-latency-ns = <140000>; 237 }; 238#if 0 239 /* Not available until CPU deep sleep is implemented */ 240 opp08 { 241 opp-hz = /bits/ 64 <2376000000>; 242 opp-level = <8>; 243 clock-latency-ns = <140000>; 244 turbo-mode; 245 }; 246#endif 247 }; 248 249 soc { 250 compatible = "simple-bus"; 251 #address-cells = <2>; 252 #size-cells = <2>; 253 nonposted-mmio; 254 ranges; 255 256 cpufreq_e: performance-controller@208e20000 { 257 compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 258 reg = <0x2 0x08e20000 0 0x1000>; 259 #performance-domain-cells = <0>; 260 }; 261 262 cpufreq_p: performance-controller@208ea0000 { 263 compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 264 reg = <0x2 0x08ea0000 0 0x1000>; 265 #performance-domain-cells = <0>; 266 }; 267 268 serial0: serial@22e600000 { 269 compatible = "apple,s5l-uart"; 270 reg = <0x2 0x2e600000 0x0 0x4000>; 271 reg-io-width = <4>; 272 interrupt-parent = <&aic>; 273 interrupts = <AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH>; 274 /* Use the bootloader-enabled clocks for now. */ 275 clocks = <&clkref>, <&clkref>; 276 clock-names = "uart", "clk_uart_baud0"; 277 power-domains = <&ps_uart0>; 278 status = "disabled"; 279 }; 280 281 aic: interrupt-controller@232100000 { 282 compatible = "apple,t8015-aic", "apple,aic"; 283 reg = <0x2 0x32100000 0x0 0x8000>; 284 #interrupt-cells = <3>; 285 interrupt-controller; 286 power-domains = <&ps_aic>; 287 }; 288 289 pmgr: power-management@232000000 { 290 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 294 reg = <0x2 0x32000000 0 0x8c000>; 295 }; 296 297 dwi_bl: backlight@232200080 { 298 compatible = "apple,t8015-dwi-bl", "apple,dwi-bl"; 299 reg = <0x2 0x32200080 0x0 0x8>; 300 power-domains = <&ps_dwi>; 301 status = "disabled"; 302 }; 303 304 pinctrl_ap: pinctrl@233100000 { 305 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 306 reg = <0x2 0x33100000 0x0 0x1000>; 307 power-domains = <&ps_gpio>; 308 309 gpio-controller; 310 #gpio-cells = <2>; 311 gpio-ranges = <&pinctrl_ap 0 0 223>; 312 apple,npins = <223>; 313 314 interrupt-controller; 315 #interrupt-cells = <2>; 316 interrupt-parent = <&aic>; 317 interrupts = <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, 318 <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>, 319 <AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH>, 320 <AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH>, 321 <AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>, 322 <AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>, 323 <AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>; 324 }; 325 326 pinctrl_aop: pinctrl@2340f0000 { 327 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 328 reg = <0x2 0x340f0000 0x0 0x4000>; 329 330 gpio-controller; 331 #gpio-cells = <2>; 332 gpio-ranges = <&pinctrl_aop 0 0 49>; 333 apple,npins = <49>; 334 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 interrupt-parent = <&aic>; 338 interrupts = <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, 339 <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, 340 <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>, 341 <AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH>, 342 <AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH>, 343 <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>, 344 <AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>; 345 }; 346 347 pinctrl_nub: pinctrl@2351f0000 { 348 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 349 reg = <0x2 0x351f0000 0x0 0x4000>; 350 351 gpio-controller; 352 #gpio-cells = <2>; 353 gpio-ranges = <&pinctrl_nub 0 0 8>; 354 apple,npins = <8>; 355 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 interrupt-parent = <&aic>; 359 interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>, 360 <AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH>, 361 <AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>; 362 }; 363 364 pmgr_mini: power-management@235200000 { 365 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 369 reg = <0x2 0x35200000 0 0x84000>; 370 }; 371 372 wdt: watchdog@2352b0000 { 373 compatible = "apple,t8015-wdt", "apple,wdt"; 374 reg = <0x2 0x352b0000 0x0 0x4000>; 375 clocks = <&clkref>; 376 interrupt-parent = <&aic>; 377 interrupts = <AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH>; 378 }; 379 380 pinctrl_smc: pinctrl@236024000 { 381 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 382 reg = <0x2 0x36024000 0x0 0x4000>; 383 384 gpio-controller; 385 #gpio-cells = <2>; 386 gpio-ranges = <&pinctrl_smc 0 0 6>; 387 apple,npins = <6>; 388 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 interrupt-parent = <&aic>; 392 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 393 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 394 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 395 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 396 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 397 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 398 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 399 /* 400 * SMC is not yet supported and accessing this pinctrl while SMC is 401 * suspended results in a hang. 402 */ 403 status = "disabled"; 404 }; 405 }; 406 407 timer { 408 compatible = "arm,armv8-timer"; 409 interrupt-parent = <&aic>; 410 interrupt-names = "phys", "virt"; 411 /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */ 412 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 413 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 414 }; 415}; 416 417#include "t8015-pmgr.dtsi" 418