1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8015 "A11" SoC 4 * 5 * Other names: H10, "Skye" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu-map { 32 cluster0 { 33 core0 { 34 cpu = <&cpu_e0>; 35 }; 36 core1 { 37 cpu = <&cpu_e1>; 38 }; 39 core2 { 40 cpu = <&cpu_e2>; 41 }; 42 core3 { 43 cpu = <&cpu_e3>; 44 }; 45 }; 46 47 cluster1 { 48 core0 { 49 cpu = <&cpu_p0>; 50 }; 51 core1 { 52 cpu = <&cpu_p1>; 53 }; 54 }; 55 }; 56 57 cpu_e0: cpu@0 { 58 compatible = "apple,mistral"; 59 reg = <0x0 0x0>; 60 cpu-release-addr = <0 0>; /* To be filled by loader */ 61 enable-method = "spin-table"; 62 device_type = "cpu"; 63 }; 64 65 cpu_e1: cpu@1 { 66 compatible = "apple,mistral"; 67 reg = <0x0 0x1>; 68 cpu-release-addr = <0 0>; /* To be filled by loader */ 69 enable-method = "spin-table"; 70 device_type = "cpu"; 71 }; 72 73 cpu_e2: cpu@2 { 74 compatible = "apple,mistral"; 75 reg = <0x0 0x2>; 76 cpu-release-addr = <0 0>; /* To be filled by loader */ 77 enable-method = "spin-table"; 78 device_type = "cpu"; 79 }; 80 81 cpu_e3: cpu@3 { 82 compatible = "apple,mistral"; 83 reg = <0x0 0x3>; 84 cpu-release-addr = <0 0>; /* To be filled by loader */ 85 enable-method = "spin-table"; 86 device_type = "cpu"; 87 }; 88 89 cpu_p0: cpu@10004 { 90 compatible = "apple,monsoon"; 91 reg = <0x0 0x10004>; 92 cpu-release-addr = <0 0>; /* To be filled by loader */ 93 enable-method = "spin-table"; 94 device_type = "cpu"; 95 }; 96 97 cpu_p1: cpu@10005 { 98 compatible = "apple,monsoon"; 99 reg = <0x0 0x10005>; 100 cpu-release-addr = <0 0>; /* To be filled by loader */ 101 enable-method = "spin-table"; 102 device_type = "cpu"; 103 }; 104 }; 105 106 soc { 107 compatible = "simple-bus"; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 nonposted-mmio; 111 ranges; 112 113 serial0: serial@22e600000 { 114 compatible = "apple,s5l-uart"; 115 reg = <0x2 0x2e600000 0x0 0x4000>; 116 reg-io-width = <4>; 117 interrupt-parent = <&aic>; 118 interrupts = <AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH>; 119 /* Use the bootloader-enabled clocks for now. */ 120 clocks = <&clkref>, <&clkref>; 121 clock-names = "uart", "clk_uart_baud0"; 122 status = "disabled"; 123 }; 124 125 aic: interrupt-controller@232100000 { 126 compatible = "apple,t8015-aic", "apple,aic"; 127 reg = <0x2 0x32100000 0x0 0x8000>; 128 #interrupt-cells = <3>; 129 interrupt-controller; 130 }; 131 132 pinctrl_ap: pinctrl@233100000 { 133 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 134 reg = <0x2 0x33100000 0x0 0x1000>; 135 136 gpio-controller; 137 #gpio-cells = <2>; 138 gpio-ranges = <&pinctrl_ap 0 0 223>; 139 apple,npins = <223>; 140 141 interrupt-controller; 142 #interrupt-cells = <2>; 143 interrupt-parent = <&aic>; 144 interrupts = <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, 145 <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>, 146 <AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH>, 147 <AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH>, 148 <AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>, 149 <AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>, 150 <AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>; 151 }; 152 153 pinctrl_aop: pinctrl@2340f0000 { 154 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 155 reg = <0x2 0x340f0000 0x0 0x4000>; 156 157 gpio-controller; 158 #gpio-cells = <2>; 159 gpio-ranges = <&pinctrl_aop 0 0 49>; 160 apple,npins = <49>; 161 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 interrupt-parent = <&aic>; 165 interrupts = <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, 166 <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, 167 <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>, 168 <AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH>, 169 <AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH>, 170 <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>, 171 <AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>; 172 }; 173 174 pinctrl_nub: pinctrl@2351f0000 { 175 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 176 reg = <0x2 0x351f0000 0x0 0x4000>; 177 178 gpio-controller; 179 #gpio-cells = <2>; 180 gpio-ranges = <&pinctrl_nub 0 0 8>; 181 apple,npins = <8>; 182 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 interrupt-parent = <&aic>; 186 interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>, 187 <AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH>, 188 <AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 wdt: watchdog@2352b0000 { 192 compatible = "apple,t8015-wdt", "apple,wdt"; 193 reg = <0x2 0x352b0000 0x0 0x4000>; 194 clocks = <&clkref>; 195 interrupt-parent = <&aic>; 196 interrupts = <AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH>; 197 }; 198 199 pinctrl_smc: pinctrl@236024000 { 200 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 201 reg = <0x2 0x36024000 0x0 0x4000>; 202 203 gpio-controller; 204 #gpio-cells = <2>; 205 gpio-ranges = <&pinctrl_smc 0 0 6>; 206 apple,npins = <6>; 207 208 interrupt-controller; 209 #interrupt-cells = <2>; 210 interrupt-parent = <&aic>; 211 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 212 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 213 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 214 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 215 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 216 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 217 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 218 /* 219 * SMC is not yet supported and accessing this pinctrl while SMC is 220 * suspended results in a hang. 221 */ 222 status = "disabled"; 223 }; 224 }; 225 226 timer { 227 compatible = "arm,armv8-timer"; 228 interrupt-parent = <&aic>; 229 interrupt-names = "phys", "virt"; 230 /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */ 231 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 232 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 233 }; 234}; 235