1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8015 "A11" SoC 4 * 5 * Other names: H10, "Skye" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/spmi/spmi.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu-map { 33 cluster0 { 34 core0 { 35 cpu = <&cpu_e0>; 36 }; 37 core1 { 38 cpu = <&cpu_e1>; 39 }; 40 core2 { 41 cpu = <&cpu_e2>; 42 }; 43 core3 { 44 cpu = <&cpu_e3>; 45 }; 46 }; 47 48 cluster1 { 49 core0 { 50 cpu = <&cpu_p0>; 51 }; 52 core1 { 53 cpu = <&cpu_p1>; 54 }; 55 }; 56 }; 57 58 cpu_e0: cpu@0 { 59 compatible = "apple,mistral"; 60 reg = <0x0 0x0>; 61 cpu-release-addr = <0 0>; /* To be filled by loader */ 62 performance-domains = <&cpufreq_e>; 63 operating-points-v2 = <&mistral_opp>; 64 capacity-dmips-mhz = <633>; 65 enable-method = "spin-table"; 66 device_type = "cpu"; 67 next-level-cache = <&l2_cache_0>; 68 i-cache-size = <0x8000>; 69 d-cache-size = <0x8000>; 70 }; 71 72 cpu_e1: cpu@1 { 73 compatible = "apple,mistral"; 74 reg = <0x0 0x1>; 75 cpu-release-addr = <0 0>; /* To be filled by loader */ 76 performance-domains = <&cpufreq_e>; 77 operating-points-v2 = <&mistral_opp>; 78 capacity-dmips-mhz = <633>; 79 enable-method = "spin-table"; 80 device_type = "cpu"; 81 next-level-cache = <&l2_cache_0>; 82 i-cache-size = <0x8000>; 83 d-cache-size = <0x8000>; 84 }; 85 86 cpu_e2: cpu@2 { 87 compatible = "apple,mistral"; 88 reg = <0x0 0x2>; 89 cpu-release-addr = <0 0>; /* To be filled by loader */ 90 performance-domains = <&cpufreq_e>; 91 operating-points-v2 = <&mistral_opp>; 92 capacity-dmips-mhz = <633>; 93 enable-method = "spin-table"; 94 device_type = "cpu"; 95 next-level-cache = <&l2_cache_0>; 96 i-cache-size = <0x8000>; 97 d-cache-size = <0x8000>; 98 }; 99 100 cpu_e3: cpu@3 { 101 compatible = "apple,mistral"; 102 reg = <0x0 0x3>; 103 cpu-release-addr = <0 0>; /* To be filled by loader */ 104 performance-domains = <&cpufreq_e>; 105 operating-points-v2 = <&mistral_opp>; 106 capacity-dmips-mhz = <633>; 107 enable-method = "spin-table"; 108 device_type = "cpu"; 109 next-level-cache = <&l2_cache_0>; 110 i-cache-size = <0x8000>; 111 d-cache-size = <0x8000>; 112 }; 113 114 cpu_p0: cpu@10004 { 115 compatible = "apple,monsoon"; 116 reg = <0x0 0x10004>; 117 cpu-release-addr = <0 0>; /* To be filled by loader */ 118 performance-domains = <&cpufreq_p>; 119 operating-points-v2 = <&monsoon_opp>; 120 capacity-dmips-mhz = <1024>; 121 enable-method = "spin-table"; 122 device_type = "cpu"; 123 next-level-cache = <&l2_cache_1>; 124 i-cache-size = <0x10000>; 125 d-cache-size = <0x10000>; 126 }; 127 128 cpu_p1: cpu@10005 { 129 compatible = "apple,monsoon"; 130 reg = <0x0 0x10005>; 131 cpu-release-addr = <0 0>; /* To be filled by loader */ 132 performance-domains = <&cpufreq_p>; 133 operating-points-v2 = <&monsoon_opp>; 134 capacity-dmips-mhz = <1024>; 135 enable-method = "spin-table"; 136 device_type = "cpu"; 137 next-level-cache = <&l2_cache_1>; 138 i-cache-size = <0x10000>; 139 d-cache-size = <0x10000>; 140 }; 141 142 l2_cache_0: l2-cache-0 { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 cache-size = <0x100000>; 147 }; 148 149 l2_cache_1: l2-cache-1 { 150 compatible = "cache"; 151 cache-level = <2>; 152 cache-unified; 153 cache-size = <0x800000>; 154 }; 155 }; 156 157 mistral_opp: opp-table-0 { 158 compatible = "operating-points-v2"; 159 160 opp01 { 161 opp-hz = /bits/ 64 <300000000>; 162 opp-level = <1>; 163 clock-latency-ns = <1800>; 164 }; 165 opp02 { 166 opp-hz = /bits/ 64 <453000000>; 167 opp-level = <2>; 168 clock-latency-ns = <140000>; 169 }; 170 opp03 { 171 opp-hz = /bits/ 64 <672000000>; 172 opp-level = <3>; 173 clock-latency-ns = <105000>; 174 }; 175 opp04 { 176 opp-hz = /bits/ 64 <972000000>; 177 opp-level = <4>; 178 clock-latency-ns = <115000>; 179 }; 180 opp05 { 181 opp-hz = /bits/ 64 <1272000000>; 182 opp-level = <5>; 183 clock-latency-ns = <125000>; 184 }; 185 opp06 { 186 opp-hz = /bits/ 64 <1572000000>; 187 opp-level = <6>; 188 clock-latency-ns = <135000>; 189 }; 190#if 0 191 /* Not available until CPU deep sleep is implemented */ 192 opp07 { 193 opp-hz = /bits/ 64 <1680000000>; 194 opp-level = <7>; 195 clock-latency-ns = <135000>; 196 turbo-mode; 197 }; 198#endif 199 }; 200 201 monsoon_opp: opp-table-1 { 202 compatible = "operating-points-v2"; 203 204 opp01 { 205 opp-hz = /bits/ 64 <300000000>; 206 opp-level = <1>; 207 clock-latency-ns = <1400>; 208 }; 209 opp02 { 210 opp-hz = /bits/ 64 <453000000>; 211 opp-level = <2>; 212 clock-latency-ns = <140000>; 213 }; 214 opp03 { 215 opp-hz = /bits/ 64 <853000000>; 216 opp-level = <3>; 217 clock-latency-ns = <110000>; 218 }; 219 opp04 { 220 opp-hz = /bits/ 64 <1332000000>; 221 opp-level = <4>; 222 clock-latency-ns = <110000>; 223 }; 224 opp05 { 225 opp-hz = /bits/ 64 <1812000000>; 226 opp-level = <5>; 227 clock-latency-ns = <125000>; 228 }; 229 opp06 { 230 opp-hz = /bits/ 64 <2064000000>; 231 opp-level = <6>; 232 clock-latency-ns = <130000>; 233 }; 234 opp07 { 235 opp-hz = /bits/ 64 <2304000000>; 236 opp-level = <7>; 237 clock-latency-ns = <140000>; 238 }; 239#if 0 240 /* Not available until CPU deep sleep is implemented */ 241 opp08 { 242 opp-hz = /bits/ 64 <2376000000>; 243 opp-level = <8>; 244 clock-latency-ns = <140000>; 245 turbo-mode; 246 }; 247#endif 248 }; 249 250 soc { 251 compatible = "simple-bus"; 252 #address-cells = <2>; 253 #size-cells = <2>; 254 nonposted-mmio; 255 ranges; 256 257 cpufreq_e: performance-controller@208e20000 { 258 compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 259 reg = <0x2 0x08e20000 0 0x1000>; 260 #performance-domain-cells = <0>; 261 }; 262 263 cpufreq_p: performance-controller@208ea0000 { 264 compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 265 reg = <0x2 0x08ea0000 0 0x1000>; 266 #performance-domain-cells = <0>; 267 }; 268 269 i2c0: i2c@22e200000 { 270 compatible = "apple,t8015-i2c", "apple,i2c"; 271 reg = <0x2 0x2e200000 0x0 0x1000>; 272 clocks = <&clkref>; 273 interrupt-parent = <&aic>; 274 interrupts = <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>; 275 pinctrl-0 = <&i2c0_pins>; 276 pinctrl-names = "default"; 277 power-domains = <&ps_i2c0>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 }; 282 283 i2c1: i2c@22e204000 { 284 compatible = "apple,t8015-i2c", "apple,i2c"; 285 reg = <0x2 0x2e204000 0x0 0x1000>; 286 clocks = <&clkref>; 287 interrupt-parent = <&aic>; 288 interrupts = <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>; 289 pinctrl-0 = <&i2c1_pins>; 290 pinctrl-names = "default"; 291 power-domains = <&ps_i2c1>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 i2c2: i2c@22e208000 { 298 compatible = "apple,t8015-i2c", "apple,i2c"; 299 reg = <0x2 0x2e208000 0x0 0x1000>; 300 clocks = <&clkref>; 301 interrupt-parent = <&aic>; 302 interrupts = <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>; 303 pinctrl-0 = <&i2c2_pins>; 304 pinctrl-names = "default"; 305 power-domains = <&ps_i2c2>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 i2c3: i2c@22e20c000 { 312 compatible = "apple,t8015-i2c", "apple,i2c"; 313 reg = <0x2 0x2e20c000 0x0 0x1000>; 314 clocks = <&clkref>; 315 interrupt-parent = <&aic>; 316 interrupts = <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>; 317 pinctrl-0 = <&i2c3_pins>; 318 pinctrl-names = "default"; 319 power-domains = <&ps_i2c3>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 status = "disabled"; 323 }; 324 325 serial0: serial@22e600000 { 326 compatible = "apple,s5l-uart"; 327 reg = <0x2 0x2e600000 0x0 0x4000>; 328 reg-io-width = <4>; 329 interrupt-parent = <&aic>; 330 interrupts = <AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH>; 331 /* Use the bootloader-enabled clocks for now. */ 332 clocks = <&clkref>, <&clkref>; 333 clock-names = "uart", "clk_uart_baud0"; 334 power-domains = <&ps_uart0>; 335 status = "disabled"; 336 }; 337 338 aic: interrupt-controller@232100000 { 339 compatible = "apple,t8015-aic", "apple,aic"; 340 reg = <0x2 0x32100000 0x0 0x8000>; 341 #interrupt-cells = <3>; 342 interrupt-controller; 343 power-domains = <&ps_aic>; 344 }; 345 346 pmgr: power-management@232000000 { 347 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 348 #address-cells = <1>; 349 #size-cells = <1>; 350 351 reg = <0x2 0x32000000 0 0x8c000>; 352 }; 353 354 dwi_bl: backlight@232200080 { 355 compatible = "apple,t8015-dwi-bl", "apple,dwi-bl"; 356 reg = <0x2 0x32200080 0x0 0x8>; 357 power-domains = <&ps_dwi>; 358 status = "disabled"; 359 }; 360 361 pinctrl_ap: pinctrl@233100000 { 362 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 363 reg = <0x2 0x33100000 0x0 0x1000>; 364 power-domains = <&ps_gpio>; 365 366 gpio-controller; 367 #gpio-cells = <2>; 368 gpio-ranges = <&pinctrl_ap 0 0 223>; 369 apple,npins = <223>; 370 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 interrupt-parent = <&aic>; 374 interrupts = <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, 375 <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>, 376 <AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH>, 377 <AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH>, 378 <AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>, 379 <AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>, 380 <AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>; 381 382 i2c0_pins: i2c0-pins { 383 pinmux = <APPLE_PINMUX(73, 1)>, 384 <APPLE_PINMUX(72, 1)>; 385 }; 386 387 i2c1_pins: i2c1-pins { 388 pinmux = <APPLE_PINMUX(182, 1)>, 389 <APPLE_PINMUX(181, 1)>; 390 }; 391 392 i2c2_pins: i2c2-pins { 393 pinmux = <APPLE_PINMUX(4, 1)>, 394 <APPLE_PINMUX(3, 1)>; 395 }; 396 397 i2c3_pins: i2c3-pins { 398 pinmux = <APPLE_PINMUX(184, 1)>, 399 <APPLE_PINMUX(183, 1)>; 400 }; 401 }; 402 403 pinctrl_aop: pinctrl@2340f0000 { 404 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 405 reg = <0x2 0x340f0000 0x0 0x4000>; 406 407 gpio-controller; 408 #gpio-cells = <2>; 409 gpio-ranges = <&pinctrl_aop 0 0 49>; 410 apple,npins = <49>; 411 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 interrupt-parent = <&aic>; 415 interrupts = <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, 416 <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, 417 <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>, 418 <AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH>, 419 <AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH>, 420 <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>, 421 <AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>; 422 }; 423 424 spmi: spmi@235180700 { 425 compatible = "apple,t8015-spmi", "apple,t8103-spmi"; 426 reg = <0x2 0x35180700 0x0 0x100>; 427 #address-cells = <2>; 428 #size-cells = <0>; 429 }; 430 431 pinctrl_nub: pinctrl@2351f0000 { 432 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 433 reg = <0x2 0x351f0000 0x0 0x4000>; 434 435 gpio-controller; 436 #gpio-cells = <2>; 437 gpio-ranges = <&pinctrl_nub 0 0 8>; 438 apple,npins = <8>; 439 440 interrupt-controller; 441 #interrupt-cells = <2>; 442 interrupt-parent = <&aic>; 443 interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>, 444 <AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH>, 445 <AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>; 446 }; 447 448 pmgr_mini: power-management@235200000 { 449 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 453 reg = <0x2 0x35200000 0 0x84000>; 454 }; 455 456 wdt: watchdog@2352b0000 { 457 compatible = "apple,t8015-wdt", "apple,wdt"; 458 reg = <0x2 0x352b0000 0x0 0x4000>; 459 clocks = <&clkref>; 460 interrupt-parent = <&aic>; 461 interrupts = <AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH>; 462 }; 463 464 pinctrl_smc: pinctrl@236024000 { 465 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 466 reg = <0x2 0x36024000 0x0 0x4000>; 467 468 gpio-controller; 469 #gpio-cells = <2>; 470 gpio-ranges = <&pinctrl_smc 0 0 6>; 471 apple,npins = <6>; 472 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 interrupt-parent = <&aic>; 476 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 477 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 478 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 479 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 480 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 481 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 482 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 483 /* 484 * SMC is not yet supported and accessing this pinctrl while SMC is 485 * suspended results in a hang. 486 */ 487 status = "disabled"; 488 }; 489 490 ans_mbox: mbox@257008000 { 491 compatible = "apple,t8015-asc-mailbox"; 492 reg = <0x2 0x57008000 0x0 0x4000>; 493 interrupt-parent = <&aic>; 494 interrupts = <AIC_IRQ 265 IRQ_TYPE_LEVEL_HIGH>, 495 <AIC_IRQ 266 IRQ_TYPE_LEVEL_HIGH>, 496 <AIC_IRQ 267 IRQ_TYPE_LEVEL_HIGH>, 497 <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-names = "send-empty", "send-not-empty", 499 "recv-empty", "recv-not-empty"; 500 #mbox-cells = <0>; 501 power-domains = <&ps_ans2>; 502 }; 503 504 sart: iommu@259c50000 { 505 compatible = "apple,t8015-sart"; 506 reg = <0x2 0x59c50000 0x0 0x10000>; 507 power-domains = <&ps_ans2>; 508 }; 509 510 nvme@259cc0000 { 511 compatible = "apple,t8015-nvme-ans2"; 512 reg = <0x2 0x59cc0000 0x0 0x40000>, 513 <0x2 0x59d20000 0x0 0x2000>; 514 reg-names = "nvme", "ans"; 515 interrupt-parent = <&aic>; 516 interrupts = <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>; 517 mboxes = <&ans_mbox>; 518 apple,sart = <&sart>; 519 power-domains = <&ps_ans2>, <&ps_pcie>; 520 power-domain-names = "ans", "apcie0"; 521 resets = <&ps_ans2>; 522 }; 523 }; 524 525 timer { 526 compatible = "arm,armv8-timer"; 527 interrupt-parent = <&aic>; 528 interrupt-names = "phys", "virt"; 529 /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */ 530 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 531 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 532 }; 533}; 534 535#include "t8015-pmgr.dtsi" 536