1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8012 "T2" SoC 4 * 5 * Other names: H9M, "Gibraltar" 6 * 7 * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/spmi/spmi.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@10000 { 33 compatible = "apple,hurricane-zephyr"; 34 reg = <0x0 0x10000>; 35 cpu-release-addr = <0 0>; /* To be filled by loader */ 36 operating-points-v2 = <&fusion_opp>; 37 performance-domains = <&cpufreq>; 38 enable-method = "spin-table"; 39 device_type = "cpu"; 40 next-level-cache = <&l2_cache>; 41 i-cache-size = <0x10000>; /* P-core */ 42 d-cache-size = <0x10000>; /* P-core */ 43 }; 44 45 cpu1: cpu@10001 { 46 compatible = "apple,hurricane-zephyr"; 47 reg = <0x0 0x10001>; 48 cpu-release-addr = <0 0>; /* To be filled by loader */ 49 operating-points-v2 = <&fusion_opp>; 50 performance-domains = <&cpufreq>; 51 enable-method = "spin-table"; 52 device_type = "cpu"; 53 next-level-cache = <&l2_cache>; 54 i-cache-size = <0x10000>; /* P-core */ 55 d-cache-size = <0x10000>; /* P-core */ 56 }; 57 58 l2_cache: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 cache-size = <0x300000>; /* P-cluster */ 63 }; 64 }; 65 66 fusion_opp: opp-table { 67 compatible = "operating-points-v2"; 68 69 /* 70 * Apple Fusion Architecture: Hardware big.LITTLE switcher 71 * that use p-state transitions to switch between cores. 72 * Only one type of core can be active at a given time. 73 * 74 * The E-core frequencies are adjusted so performance scales 75 * linearly with reported clock speed. 76 */ 77 78 opp01 { 79 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ 80 opp-level = <1>; 81 clock-latency-ns = <11000>; 82 }; 83 opp02 { 84 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ 85 opp-level = <2>; 86 clock-latency-ns = <140000>; 87 }; 88 opp03 { 89 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ 90 opp-level = <3>; 91 clock-latency-ns = <110000>; 92 }; 93 opp04 { 94 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ 95 opp-level = <4>; 96 clock-latency-ns = <130000>; 97 }; 98 opp05 { 99 opp-hz = /bits/ 64 <756000000>; 100 opp-level = <5>; 101 clock-latency-ns = <130000>; 102 }; 103 opp06 { 104 opp-hz = /bits/ 64 <1056000000>; 105 opp-level = <6>; 106 clock-latency-ns = <130000>; 107 }; 108 opp07 { 109 opp-hz = /bits/ 64 <1356000000>; 110 opp-level = <7>; 111 clock-latency-ns = <130000>; 112 }; 113 opp08 { 114 opp-hz = /bits/ 64 <1644000000>; 115 opp-level = <8>; 116 clock-latency-ns = <135000>; 117 }; 118 opp09 { 119 opp-hz = /bits/ 64 <1944000000>; 120 opp-level = <9>; 121 clock-latency-ns = <140000>; 122 }; 123 opp10 { 124 opp-hz = /bits/ 64 <2244000000>; 125 opp-level = <10>; 126 clock-latency-ns = <150000>; 127 }; 128#if 0 129 /* Not available until CPU deep sleep is implemented */ 130 opp11 { 131 opp-hz = /bits/ 64 <2340000000>; 132 opp-level = <11>; 133 clock-latency-ns = <150000>; 134 turbo-mode; 135 }; 136#endif 137 }; 138 139 soc { 140 compatible = "simple-bus"; 141 #address-cells = <2>; 142 #size-cells = <2>; 143 nonposted-mmio; 144 ranges; 145 146 cpufreq: performance-controller@202f20000 { 147 compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 148 reg = <0x2 0x02f20000 0 0x1000>; 149 #performance-domain-cells = <0>; 150 }; 151 152 serial0: serial@20a600000 { 153 compatible = "apple,s5l-uart"; 154 reg = <0x2 0x0a600000 0x0 0x4000>; 155 reg-io-width = <4>; 156 interrupt-parent = <&aic>; 157 interrupts = <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>; 158 /* Use the bootloader-enabled clocks for now. */ 159 clocks = <&clkref>, <&clkref>; 160 clock-names = "uart", "clk_uart_baud0"; 161 power-domains = <&ps_uart0>; 162 status = "disabled"; 163 }; 164 165 pmgr: power-management@20e000000 { 166 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 170 reg = <0x2 0xe000000 0 0x8c000>; 171 }; 172 173 aic: interrupt-controller@20e100000 { 174 compatible = "apple,t8010-aic", "apple,aic"; 175 reg = <0x2 0x0e100000 0x0 0x100000>; 176 #interrupt-cells = <3>; 177 interrupt-controller; 178 power-domains = <&ps_aic>; 179 }; 180 181 pinctrl_ap: pinctrl@20f100000 { 182 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 183 reg = <0x2 0x0f100000 0x0 0x100000>; 184 power-domains = <&ps_gpio>; 185 186 gpio-controller; 187 #gpio-cells = <2>; 188 gpio-ranges = <&pinctrl_ap 0 0 221>; 189 apple,npins = <221>; 190 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 interrupt-parent = <&aic>; 194 interrupts = <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 197 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>, 198 <AIC_IRQ 49 IRQ_TYPE_LEVEL_HIGH>, 199 <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, 200 <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>; 201 }; 202 203 pinctrl_aop: pinctrl@2100f0000 { 204 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 205 reg = <0x2 0x0100f0000 0x0 0x10000>; 206 207 gpio-controller; 208 #gpio-cells = <2>; 209 gpio-ranges = <&pinctrl_aop 0 0 41>; 210 apple,npins = <41>; 211 212 interrupt-controller; 213 #interrupt-cells = <2>; 214 interrupt-parent = <&aic>; 215 interrupts = <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 216 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 217 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 218 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>, 219 <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, 220 <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, 221 <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 spmi: spmi@211180700 { 225 compatible = "apple,t8012-spmi", "apple,t8103-spmi"; 226 reg = <0x2 0x11180700 0x0 0x100>; 227 #address-cells = <2>; 228 #size-cells = <0>; 229 }; 230 231 pinctrl_nub: pinctrl@2111f0000 { 232 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 233 reg = <0x2 0x111f0000 0x0 0x1000>; 234 235 gpio-controller; 236 #gpio-cells = <2>; 237 gpio-ranges = <&pinctrl_nub 0 0 19>; 238 apple,npins = <19>; 239 240 interrupt-controller; 241 #interrupt-cells = <2>; 242 interrupt-parent = <&aic>; 243 interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>, 244 <AIC_IRQ 165 IRQ_TYPE_LEVEL_HIGH>, 245 <AIC_IRQ 166 IRQ_TYPE_LEVEL_HIGH>; 246 }; 247 248 pmgr_mini: power-management@211200000 { 249 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 253 reg = <0x2 0x11200000 0 0x84000>; 254 }; 255 256 wdt: watchdog@2112b0000 { 257 compatible = "apple,t8010-wdt", "apple,wdt"; 258 reg = <0x2 0x112b0000 0x0 0x4000>; 259 clocks = <&clkref>; 260 interrupt-parent = <&aic>; 261 interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 264 pinctrl_smc: pinctrl@212024000 { 265 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 266 reg = <0x2 0x12024000 0x0 0x1000>; 267 power-domains = <&ps_smc_cpu>; 268 269 gpio-controller; 270 #gpio-cells = <2>; 271 gpio-ranges = <&pinctrl_smc 0 0 81>; 272 apple,npins = <81>; 273 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 interrupt-parent = <&aic>; 277 interrupts = <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 278 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>, 279 <AIC_IRQ 197 IRQ_TYPE_LEVEL_HIGH>, 280 <AIC_IRQ 198 IRQ_TYPE_LEVEL_HIGH>, 281 <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 282 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 283 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>; 284 /* 285 * SMC is not yet supported and accessing this pinctrl while SMC is 286 * suspended results in a hang. 287 */ 288 status = "disabled"; 289 }; 290 }; 291 292 timer { 293 compatible = "arm,armv8-timer"; 294 interrupt-parent = <&aic>; 295 interrupt-names = "phys", "virt"; 296 /* Note that T2 doesn't actually have a hypervisor (EL2 is not implemented). */ 297 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 298 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 299 }; 300}; 301 302#include "t8012-pmgr.dtsi" 303