1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8011 "A10X" SoC 4 * 5 * Other names: H9G, "Myst" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,hurricane-zephyr"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 operating-points-v2 = <&fusion_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 next-level-cache = <&l2_cache>; 40 i-cache-size = <0x10000>; /* P-core */ 41 d-cache-size = <0x10000>; /* P-core */ 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "apple,hurricane-zephyr"; 46 reg = <0x0 0x1>; 47 cpu-release-addr = <0 0>; /* To be filled by loader */ 48 operating-points-v2 = <&fusion_opp>; 49 performance-domains = <&cpufreq>; 50 enable-method = "spin-table"; 51 device_type = "cpu"; 52 next-level-cache = <&l2_cache>; 53 i-cache-size = <0x10000>; /* P-core */ 54 d-cache-size = <0x10000>; /* P-core */ 55 }; 56 57 cpu2: cpu@2 { 58 compatible = "apple,hurricane-zephyr"; 59 reg = <0x0 0x2>; 60 cpu-release-addr = <0 0>; /* To be filled by loader */ 61 operating-points-v2 = <&fusion_opp>; 62 performance-domains = <&cpufreq>; 63 enable-method = "spin-table"; 64 device_type = "cpu"; 65 next-level-cache = <&l2_cache>; 66 i-cache-size = <0x10000>; /* P-core */ 67 d-cache-size = <0x10000>; /* P-core */ 68 }; 69 70 l2_cache: l2-cache { 71 compatible = "cache"; 72 cache-level = <2>; 73 cache-unified; 74 cache-size = <0x800000>; /* P-cluster */ 75 }; 76 }; 77 78 fusion_opp: opp-table { 79 compatible = "operating-points-v2"; 80 81 /* 82 * Apple Fusion Architecture: Hardwired big.LITTLE switcher 83 * that use p-state transitions to switch between cores. 84 * 85 * The E-core frequencies are adjusted so performance scales 86 * linearly with reported clock speed. 87 */ 88 89 opp01 { 90 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ 91 opp-level = <1>; 92 clock-latency-ns = <12000>; 93 }; 94 opp02 { 95 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ 96 opp-level = <2>; 97 clock-latency-ns = <135000>; 98 }; 99 opp03 { 100 opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */ 101 opp-level = <3>; 102 clock-latency-ns = <105000>; 103 }; 104 opp04 { 105 opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */ 106 opp-level = <4>; 107 clock-latency-ns = <115000>; 108 }; 109 opp05 { 110 opp-hz = /bits/ 64 <804000000>; 111 opp-level = <5>; 112 clock-latency-ns = <122000>; 113 }; 114 opp06 { 115 opp-hz = /bits/ 64 <1140000000>; 116 opp-level = <6>; 117 clock-latency-ns = <120000>; 118 }; 119 opp07 { 120 opp-hz = /bits/ 64 <1548000000>; 121 opp-level = <7>; 122 clock-latency-ns = <125000>; 123 }; 124 opp08 { 125 opp-hz = /bits/ 64 <1956000000>; 126 opp-level = <8>; 127 clock-latency-ns = <135000>; 128 }; 129 opp09 { 130 opp-hz = /bits/ 64 <2316000000>; 131 opp-level = <9>; 132 clock-latency-ns = <140000>; 133 }; 134#if 0 135 /* Not available until CPU deep sleep is implemented */ 136 opp10 { 137 opp-hz = /bits/ 64 <2400000000>; 138 opp-level = <10>; 139 clock-latency-ns = <140000>; 140 turbo-mode; 141 }; 142#endif 143 }; 144 145 soc { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 nonposted-mmio; 150 ranges; 151 152 cpufreq: performance-controller@202f20000 { 153 compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 154 reg = <0x2 0x02f20000 0 0x1000>; 155 #performance-domain-cells = <0>; 156 }; 157 158 serial0: serial@20a0c0000 { 159 compatible = "apple,s5l-uart"; 160 reg = <0x2 0x0a0c0000 0x0 0x4000>; 161 reg-io-width = <4>; 162 interrupt-parent = <&aic>; 163 interrupts = <AIC_IRQ 216 IRQ_TYPE_LEVEL_HIGH>; 164 /* Use the bootloader-enabled clocks for now. */ 165 clocks = <&clkref>, <&clkref>; 166 clock-names = "uart", "clk_uart_baud0"; 167 power-domains = <&ps_uart0>; 168 status = "disabled"; 169 }; 170 171 i2c0: i2c@20a110000 { 172 compatible = "apple,t8010-i2c", "apple,i2c"; 173 reg = <0x2 0x0a110000 0x0 0x1000>; 174 clocks = <&clkref>; 175 interrupt-parent = <&aic>; 176 interrupts = <AIC_IRQ 230 IRQ_TYPE_LEVEL_HIGH>; 177 pinctrl-0 = <&i2c0_pins>; 178 pinctrl-names = "default"; 179 power-domains = <&ps_i2c0>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 status = "disabled"; 183 }; 184 185 i2c1: i2c@20a111000 { 186 compatible = "apple,t8010-i2c", "apple,i2c"; 187 reg = <0x2 0x0a111000 0x0 0x1000>; 188 clocks = <&clkref>; 189 interrupt-parent = <&aic>; 190 interrupts = <AIC_IRQ 231 IRQ_TYPE_LEVEL_HIGH>; 191 pinctrl-0 = <&i2c1_pins>; 192 pinctrl-names = "default"; 193 power-domains = <&ps_i2c1>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 status = "disabled"; 197 }; 198 199 i2c2: i2c@20a112000 { 200 compatible = "apple,t8010-i2c", "apple,i2c"; 201 reg = <0x2 0x0a112000 0x0 0x1000>; 202 clocks = <&clkref>; 203 interrupt-parent = <&aic>; 204 interrupts = <AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH>; 205 pinctrl-0 = <&i2c2_pins>; 206 pinctrl-names = "default"; 207 power-domains = <&ps_i2c2>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 status = "disabled"; 211 }; 212 213 i2c3: i2c@20a113000 { 214 compatible = "apple,t8010-i2c", "apple,i2c"; 215 reg = <0x2 0x0a113000 0x0 0x1000>; 216 clocks = <&clkref>; 217 interrupt-parent = <&aic>; 218 interrupts = <AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH>; 219 pinctrl-0 = <&i2c3_pins>; 220 pinctrl-names = "default"; 221 power-domains = <&ps_i2c3>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 status = "disabled"; 225 }; 226 227 pmgr: power-management@20e000000 { 228 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 232 reg = <0x2 0xe000000 0 0x8c000>; 233 }; 234 235 aic: interrupt-controller@20e100000 { 236 compatible = "apple,t8010-aic", "apple,aic"; 237 reg = <0x2 0x0e100000 0x0 0x100000>; 238 #interrupt-cells = <3>; 239 interrupt-controller; 240 power-domains = <&ps_aic>; 241 }; 242 243 pinctrl_ap: pinctrl@20f100000 { 244 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 245 reg = <0x2 0x0f100000 0x0 0x100000>; 246 power-domains = <&ps_gpio>; 247 248 gpio-controller; 249 #gpio-cells = <2>; 250 gpio-ranges = <&pinctrl_ap 0 0 219>; 251 apple,npins = <219>; 252 253 interrupt-controller; 254 #interrupt-cells = <2>; 255 interrupt-parent = <&aic>; 256 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 257 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 258 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 259 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 260 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 261 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 262 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 263 264 i2c0_pins: i2c0-pins { 265 pinmux = <APPLE_PINMUX(211, 1)>, 266 <APPLE_PINMUX(210, 1)>; 267 }; 268 269 i2c1_pins: i2c1-pins { 270 pinmux = <APPLE_PINMUX(156, 1)>, 271 <APPLE_PINMUX(155, 1)>; 272 }; 273 274 i2c2_pins: i2c2-pins { 275 pinmux = <APPLE_PINMUX(58, 1)>, 276 <APPLE_PINMUX(57, 1)>; 277 }; 278 279 i2c3_pins: i2c3-pins { 280 pinmux = <APPLE_PINMUX(158, 1)>, 281 <APPLE_PINMUX(157, 1)>; 282 }; 283 }; 284 285 pinctrl_aop: pinctrl@2100f0000 { 286 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 287 reg = <0x2 0x100f0000 0x0 0x100000>; 288 power-domains = <&ps_aop_gpio>; 289 290 gpio-controller; 291 #gpio-cells = <2>; 292 gpio-ranges = <&pinctrl_aop 0 0 42>; 293 apple,npins = <42>; 294 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 interrupt-parent = <&aic>; 298 interrupts = <AIC_IRQ 125 IRQ_TYPE_LEVEL_HIGH>, 299 <AIC_IRQ 126 IRQ_TYPE_LEVEL_HIGH>, 300 <AIC_IRQ 127 IRQ_TYPE_LEVEL_HIGH>, 301 <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 302 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 303 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 304 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>; 305 }; 306 307 pmgr_mini: power-management@210200000 { 308 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 309 #address-cells = <1>; 310 #size-cells = <1>; 311 312 reg = <0x2 0x10200000 0 0x84000>; 313 }; 314 315 wdt: watchdog@2102b0000 { 316 compatible = "apple,t8010-wdt", "apple,wdt"; 317 reg = <0x2 0x102b0000 0x0 0x4000>; 318 clocks = <&clkref>; 319 interrupt-parent = <&aic>; 320 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 321 }; 322 }; 323 324 timer { 325 compatible = "arm,armv8-timer"; 326 interrupt-parent = <&aic>; 327 interrupt-names = "phys", "virt"; 328 /* Note that A10X doesn't actually have a hypervisor (EL2 is not implemented). */ 329 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 330 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 331 }; 332}; 333 334#include "t8011-pmgr.dtsi" 335