1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8011 "A10X" SoC 4 * 5 * Other names: H9G, "Myst" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,hurricane-zephyr"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 enable-method = "spin-table"; 36 device_type = "cpu"; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "apple,hurricane-zephyr"; 41 reg = <0x0 0x1>; 42 cpu-release-addr = <0 0>; /* To be filled by loader */ 43 enable-method = "spin-table"; 44 device_type = "cpu"; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "apple,hurricane-zephyr"; 49 reg = <0x0 0x2>; 50 cpu-release-addr = <0 0>; /* To be filled by loader */ 51 enable-method = "spin-table"; 52 device_type = "cpu"; 53 }; 54 }; 55 56 soc { 57 compatible = "simple-bus"; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 nonposted-mmio; 61 ranges; 62 63 serial0: serial@20a0c0000 { 64 compatible = "apple,s5l-uart"; 65 reg = <0x2 0x0a0c0000 0x0 0x4000>; 66 reg-io-width = <4>; 67 interrupt-parent = <&aic>; 68 interrupts = <AIC_IRQ 216 IRQ_TYPE_LEVEL_HIGH>; 69 /* Use the bootloader-enabled clocks for now. */ 70 clocks = <&clkref>, <&clkref>; 71 clock-names = "uart", "clk_uart_baud0"; 72 status = "disabled"; 73 }; 74 75 aic: interrupt-controller@20e100000 { 76 compatible = "apple,t8010-aic", "apple,aic"; 77 reg = <0x2 0x0e100000 0x0 0x100000>; 78 #interrupt-cells = <3>; 79 interrupt-controller; 80 }; 81 82 pinctrl_ap: pinctrl@20f100000 { 83 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 84 reg = <0x2 0x0f100000 0x0 0x100000>; 85 86 gpio-controller; 87 #gpio-cells = <2>; 88 gpio-ranges = <&pinctrl_ap 0 0 219>; 89 apple,npins = <219>; 90 91 interrupt-controller; 92 #interrupt-cells = <2>; 93 interrupt-parent = <&aic>; 94 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 97 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 98 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 99 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 100 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 101 }; 102 103 pinctrl_aop: pinctrl@2100f0000 { 104 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 105 reg = <0x2 0x100f0000 0x0 0x100000>; 106 107 gpio-controller; 108 #gpio-cells = <2>; 109 gpio-ranges = <&pinctrl_aop 0 0 42>; 110 apple,npins = <42>; 111 112 interrupt-controller; 113 #interrupt-cells = <2>; 114 interrupt-parent = <&aic>; 115 interrupts = <AIC_IRQ 125 IRQ_TYPE_LEVEL_HIGH>, 116 <AIC_IRQ 126 IRQ_TYPE_LEVEL_HIGH>, 117 <AIC_IRQ 127 IRQ_TYPE_LEVEL_HIGH>, 118 <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 119 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 120 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 121 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 124 wdt: watchdog@2102b0000 { 125 compatible = "apple,t8010-wdt", "apple,wdt"; 126 reg = <0x2 0x102b0000 0x0 0x4000>; 127 clocks = <&clkref>; 128 interrupt-parent = <&aic>; 129 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 }; 132 133 timer { 134 compatible = "arm,armv8-timer"; 135 interrupt-parent = <&aic>; 136 interrupt-names = "phys", "virt"; 137 /* Note that A10X doesn't actually have a hypervisor (EL2 is not implemented). */ 138 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 139 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 140 }; 141}; 142