1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8011 "A10X" SoC 4 * 5 * Other names: H9G, "Myst" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,hurricane-zephyr"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 operating-points-v2 = <&fusion_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "apple,hurricane-zephyr"; 43 reg = <0x0 0x1>; 44 cpu-release-addr = <0 0>; /* To be filled by loader */ 45 operating-points-v2 = <&fusion_opp>; 46 performance-domains = <&cpufreq>; 47 enable-method = "spin-table"; 48 device_type = "cpu"; 49 }; 50 51 cpu2: cpu@2 { 52 compatible = "apple,hurricane-zephyr"; 53 reg = <0x0 0x2>; 54 cpu-release-addr = <0 0>; /* To be filled by loader */ 55 operating-points-v2 = <&fusion_opp>; 56 performance-domains = <&cpufreq>; 57 enable-method = "spin-table"; 58 device_type = "cpu"; 59 }; 60 }; 61 62 fusion_opp: opp-table { 63 compatible = "operating-points-v2"; 64 65 /* 66 * Apple Fusion Architecture: Hardwired big.LITTLE switcher 67 * that use p-state transitions to switch between cores. 68 * 69 * The E-core frequencies are adjusted so performance scales 70 * linearly with reported clock speed. 71 */ 72 73 opp01 { 74 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ 75 opp-level = <1>; 76 clock-latency-ns = <12000>; 77 }; 78 opp02 { 79 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ 80 opp-level = <2>; 81 clock-latency-ns = <135000>; 82 }; 83 opp03 { 84 opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */ 85 opp-level = <3>; 86 clock-latency-ns = <105000>; 87 }; 88 opp04 { 89 opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */ 90 opp-level = <4>; 91 clock-latency-ns = <115000>; 92 }; 93 opp05 { 94 opp-hz = /bits/ 64 <804000000>; 95 opp-level = <5>; 96 clock-latency-ns = <122000>; 97 }; 98 opp06 { 99 opp-hz = /bits/ 64 <1140000000>; 100 opp-level = <6>; 101 clock-latency-ns = <120000>; 102 }; 103 opp07 { 104 opp-hz = /bits/ 64 <1548000000>; 105 opp-level = <7>; 106 clock-latency-ns = <125000>; 107 }; 108 opp08 { 109 opp-hz = /bits/ 64 <1956000000>; 110 opp-level = <8>; 111 clock-latency-ns = <135000>; 112 }; 113 opp09 { 114 opp-hz = /bits/ 64 <2316000000>; 115 opp-level = <9>; 116 clock-latency-ns = <140000>; 117 }; 118#if 0 119 /* Not available until CPU deep sleep is implemented */ 120 opp10 { 121 opp-hz = /bits/ 64 <2400000000>; 122 opp-level = <10>; 123 clock-latency-ns = <140000>; 124 turbo-mode; 125 }; 126#endif 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 nonposted-mmio; 134 ranges; 135 136 cpufreq: performance-controller@202f20000 { 137 compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 138 reg = <0x2 0x02f20000 0 0x1000>; 139 #performance-domain-cells = <0>; 140 }; 141 142 serial0: serial@20a0c0000 { 143 compatible = "apple,s5l-uart"; 144 reg = <0x2 0x0a0c0000 0x0 0x4000>; 145 reg-io-width = <4>; 146 interrupt-parent = <&aic>; 147 interrupts = <AIC_IRQ 216 IRQ_TYPE_LEVEL_HIGH>; 148 /* Use the bootloader-enabled clocks for now. */ 149 clocks = <&clkref>, <&clkref>; 150 clock-names = "uart", "clk_uart_baud0"; 151 power-domains = <&ps_uart0>; 152 status = "disabled"; 153 }; 154 155 pmgr: power-management@20e000000 { 156 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 160 reg = <0x2 0xe000000 0 0x8c000>; 161 }; 162 163 aic: interrupt-controller@20e100000 { 164 compatible = "apple,t8010-aic", "apple,aic"; 165 reg = <0x2 0x0e100000 0x0 0x100000>; 166 #interrupt-cells = <3>; 167 interrupt-controller; 168 power-domains = <&ps_aic>; 169 }; 170 171 pinctrl_ap: pinctrl@20f100000 { 172 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 173 reg = <0x2 0x0f100000 0x0 0x100000>; 174 power-domains = <&ps_gpio>; 175 176 gpio-controller; 177 #gpio-cells = <2>; 178 gpio-ranges = <&pinctrl_ap 0 0 219>; 179 apple,npins = <219>; 180 181 interrupt-controller; 182 #interrupt-cells = <2>; 183 interrupt-parent = <&aic>; 184 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 185 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 186 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 187 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 188 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 189 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 190 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 191 }; 192 193 pinctrl_aop: pinctrl@2100f0000 { 194 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 195 reg = <0x2 0x100f0000 0x0 0x100000>; 196 power-domains = <&ps_aop_gpio>; 197 198 gpio-controller; 199 #gpio-cells = <2>; 200 gpio-ranges = <&pinctrl_aop 0 0 42>; 201 apple,npins = <42>; 202 203 interrupt-controller; 204 #interrupt-cells = <2>; 205 interrupt-parent = <&aic>; 206 interrupts = <AIC_IRQ 125 IRQ_TYPE_LEVEL_HIGH>, 207 <AIC_IRQ 126 IRQ_TYPE_LEVEL_HIGH>, 208 <AIC_IRQ 127 IRQ_TYPE_LEVEL_HIGH>, 209 <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 210 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 211 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 212 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>; 213 }; 214 215 pmgr_mini: power-management@210200000 { 216 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 220 reg = <0x2 0x10200000 0 0x84000>; 221 }; 222 223 wdt: watchdog@2102b0000 { 224 compatible = "apple,t8010-wdt", "apple,wdt"; 225 reg = <0x2 0x102b0000 0x0 0x4000>; 226 clocks = <&clkref>; 227 interrupt-parent = <&aic>; 228 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 229 }; 230 }; 231 232 timer { 233 compatible = "arm,armv8-timer"; 234 interrupt-parent = <&aic>; 235 interrupt-names = "phys", "virt"; 236 /* Note that A10X doesn't actually have a hypervisor (EL2 is not implemented). */ 237 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 238 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 239 }; 240}; 241 242#include "t8011-pmgr.dtsi" 243