1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T7001 "A8X" SoC 4 * 5 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 6 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 7 */ 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 interrupt-parent = <&aic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 serial0 = &serial0; 21 }; 22 23 clkref: clock-ref { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <24000000>; 27 clock-output-names = "clkref"; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "apple,typhoon"; 36 reg = <0x0 0x0>; 37 cpu-release-addr = <0 0>; /* To be filled in by loader */ 38 performance-domains = <&cpufreq>; 39 operating-points-v2 = <&typhoon_opp>; 40 enable-method = "spin-table"; 41 device_type = "cpu"; 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "apple,typhoon"; 46 reg = <0x0 0x1>; 47 cpu-release-addr = <0 0>; /* To be filled in by loader */ 48 performance-domains = <&cpufreq>; 49 operating-points-v2 = <&typhoon_opp>; 50 enable-method = "spin-table"; 51 device_type = "cpu"; 52 }; 53 54 cpu2: cpu@2 { 55 compatible = "apple,typhoon"; 56 reg = <0x0 0x2>; 57 cpu-release-addr = <0 0>; /* To be filled by loader */ 58 performance-domains = <&cpufreq>; 59 operating-points-v2 = <&typhoon_opp>; 60 enable-method = "spin-table"; 61 device_type = "cpu"; 62 }; 63 }; 64 65 typhoon_opp: opp-table { 66 compatible = "operating-points-v2"; 67 68 opp01 { 69 opp-hz = /bits/ 64 <300000000>; 70 opp-level = <1>; 71 clock-latency-ns = <300>; 72 }; 73 opp02 { 74 opp-hz = /bits/ 64 <396000000>; 75 opp-level = <2>; 76 clock-latency-ns = <49000>; 77 }; 78 opp03 { 79 opp-hz = /bits/ 64 <600000000>; 80 opp-level = <3>; 81 clock-latency-ns = <31000>; 82 }; 83 opp04 { 84 opp-hz = /bits/ 64 <840000000>; 85 opp-level = <4>; 86 clock-latency-ns = <32000>; 87 }; 88 opp05 { 89 opp-hz = /bits/ 64 <1128000000>; 90 opp-level = <5>; 91 clock-latency-ns = <32000>; 92 }; 93 opp06 { 94 opp-hz = /bits/ 64 <1392000000>; 95 opp-level = <6>; 96 clock-latency-ns = <37000>; 97 }; 98 opp07 { 99 opp-hz = /bits/ 64 <1512000000>; 100 opp-level = <7>; 101 clock-latency-ns = <41000>; 102 }; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <2>; 108 #size-cells = <2>; 109 nonposted-mmio; 110 ranges; 111 112 cpufreq: performance-controller@202220000 { 113 compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; 114 reg = <0x2 0x02220000 0 0x1000>; 115 #performance-domain-cells = <0>; 116 }; 117 118 serial0: serial@20a0c0000 { 119 compatible = "apple,s5l-uart"; 120 reg = <0x2 0x0a0c0000 0x0 0x4000>; 121 reg-io-width = <4>; 122 interrupt-parent = <&aic>; 123 interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>; 124 /* Use the bootloader-enabled clocks for now. */ 125 clocks = <&clkref>, <&clkref>; 126 clock-names = "uart", "clk_uart_baud0"; 127 power-domains = <&ps_uart0>; 128 status = "disabled"; 129 }; 130 131 pmgr: power-management@20e000000 { 132 compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 136 reg = <0x2 0xe000000 0 0x24000>; 137 }; 138 139 wdt: watchdog@20e027000 { 140 compatible = "apple,t7000-wdt", "apple,wdt"; 141 reg = <0x2 0x0e027000 0x0 0x1000>; 142 clocks = <&clkref>; 143 interrupt-parent = <&aic>; 144 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 145 }; 146 147 aic: interrupt-controller@20e100000 { 148 compatible = "apple,t7000-aic", "apple,aic"; 149 reg = <0x2 0x0e100000 0x0 0x100000>; 150 #interrupt-cells = <3>; 151 interrupt-controller; 152 power-domains = <&ps_aic>; 153 }; 154 155 pinctrl: pinctrl@20e300000 { 156 compatible = "apple,t7000-pinctrl", "apple,pinctrl"; 157 reg = <0x2 0x0e300000 0x0 0x100000>; 158 power-domains = <&ps_gpio>; 159 160 gpio-controller; 161 #gpio-cells = <2>; 162 gpio-ranges = <&pinctrl 0 0 184>; 163 apple,npins = <184>; 164 165 interrupt-controller; 166 #interrupt-cells = <2>; 167 interrupt-parent = <&aic>; 168 interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>, 169 <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>, 170 <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>, 171 <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>, 172 <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, 173 <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, 174 <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 }; 177 178 timer { 179 compatible = "arm,armv8-timer"; 180 interrupt-parent = <&aic>; 181 interrupt-names = "phys", "virt"; 182 /* Note that A8X doesn't actually have a hypervisor (EL2 is not implemented). */ 183 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 184 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 185 }; 186}; 187 188#include "t7001-pmgr.dtsi" 189